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| author | Michal Simek <michal.simek@xilinx.com> | 2015-12-11 14:45:29 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-01-27 15:55:53 +0100 |
| commit | 44a3a91cb0424e887105c2bfc670b863e8f2ee71 (patch) | |
| tree | 18570ade3a6e1257fad9b9d17b4db8e30354306b /board | |
| parent | 85916e29df41d16cf89e48113acafe9a670770c9 (diff) | |
| download | u-boot-imx-44a3a91cb0424e887105c2bfc670b863e8f2ee71.zip u-boot-imx-44a3a91cb0424e887105c2bfc670b863e8f2ee71.tar.gz u-boot-imx-44a3a91cb0424e887105c2bfc670b863e8f2ee71.tar.bz2 | |
microblaze: Read information about RAM from DT
Do not setup ram start/size in board file. Read it from DT instead.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/xilinx/microblaze-generic/microblaze-generic.c | 9 | ||||
| -rw-r--r-- | board/xilinx/microblaze-generic/xparameters.h | 4 |
2 files changed, 0 insertions, 13 deletions
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 0e7509d..0d7bed5 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; static int reset_pin = -1; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) ulong ram_base; void dram_init_banksize(void) @@ -57,14 +56,6 @@ int dram_init(void) return 0; }; -#else -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} -#endif int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 552aaf4..ccb528e 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -35,10 +35,6 @@ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 |