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| author | Tim Harvey <tharvey@gateworks.com> | 2015-04-08 12:54:55 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-04-22 14:39:11 +0200 |
| commit | 7f14c31bba70ee339c8c730e263a143b869f2828 (patch) | |
| tree | 0d9552e738563d988945f33ff93533372a9095b4 /board | |
| parent | 06edcb9d3787dc03ad6be87d083a7bcb15aa4c09 (diff) | |
| download | u-boot-imx-7f14c31bba70ee339c8c730e263a143b869f2828.zip u-boot-imx-7f14c31bba70ee339c8c730e263a143b869f2828.tar.gz u-boot-imx-7f14c31bba70ee339c8c730e263a143b869f2828.tar.bz2 | |
imx: ventana: remove 128x16 calibration (share with 128x32)
The calibration data for dual 2Gb density chips can be used for a single 2Gb
density chip.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/gateworks/gw_ventana/gw_ventana_spl.c | 27 |
1 files changed, 3 insertions, 24 deletions
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index baa2c6e..b839b89 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -220,17 +220,6 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { * calibration - these are the various CPU/DDR3 combinations we support */ -static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, -}; - static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x001B0016, @@ -244,17 +233,6 @@ static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { .p0_mpwrdlctl = 0x40403D36, }; -static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, -}; - static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x00420043, @@ -412,11 +390,12 @@ static void spl_dram_init(int width, int size_mb, int board_model) * mx6_ddr_cfg - chip specific timing/layout details */ if (width == 16 && size_mb == 256) { + /* 1x 2Gb density chip - same calib as 2x 2Gb */ mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_128x16_mmdc_calib; + calib = &mx6dq_128x32_mmdc_calib; else - calib = &mx6sdl_128x16_mmdc_calib; + calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); } else if (width == 16 && size_mb == 512) { mem = &mt41k256m16ha_125; |