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| author | Ye Li <ye.li@nxp.com> | 2016-03-14 14:58:44 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-03-25 16:06:05 +0800 |
| commit | 5e48e6dbacde61bb9290086368df73b7bad86a07 (patch) | |
| tree | 3fa1f2d86e6758043a01ae9939f2c542dada9927 /board | |
| parent | b315d6b36a913d75d25284320e69050ebdf7a7eb (diff) | |
| download | u-boot-imx-5e48e6dbacde61bb9290086368df73b7bad86a07.zip u-boot-imx-5e48e6dbacde61bb9290086368df73b7bad86a07.tar.gz u-boot-imx-5e48e6dbacde61bb9290086368df73b7bad86a07.tar.bz2 | |
MLK-12553 mx6sabresd: Add RGMII support
Need to configure the phy AR8031 to output 125Mhz clock for ENET
reference clock. And introduce a TX clock delay.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 8a12965..b7afb28 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -613,6 +613,39 @@ void epdc_power_off(void) } #endif +int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) { |