Merge branch 'master' of git://git.denx.de/u-boot-arm

105 files changed, 4349 insertions, 8235 deletions

diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
index 744b927..c280029 100644
--- a/board/ait/cam_enc_4xx/config.mk
+++ b/board/ait/cam_enc_4xx/config.mk
@@ -8,7 +8,7 @@
 #
 
 #Provide at least 16MB spacing between us and the Linux Kernel image
-PAD_TO	:= 12320
+CONFIG_SPL_PAD_TO := 12320
 UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
 ifndef CONFIG_SPL_BUILD
 ALL-y += $(obj)u-boot.ubl
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts
index f916122..e46afbe 100644
--- a/board/avionic-design/dts/tegra20-medcom-wide.dts
+++ b/board/avionic-design/dts/tegra20-medcom-wide.dts
@@ -14,18 +14,17 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
+	host1x {
+		status = "okay";
 
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
+		dc@54200000 {
+			status = "okay";
 
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
+			rgb {
+				nvidia,panel = <&lcd_panel>;
+				status = "okay";
+			};
+		};
 	};
 
 	serial@70006300 {
@@ -55,4 +54,23 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	lcd_panel: panel {
+		clock = <61715000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <2>;
+		right-margin = <47>;
+		hsync-len = <136>;
+		lower-margin = <21>;
+		upper-margin = <11>;
+		vsync-len = <4>;
+
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 500000>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+		nvidia,panel-timings = <0 0 0 0>;
+	};
 };
diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts
index 78c394f..3e6cce0 100644
--- a/board/avionic-design/dts/tegra20-plutux.dts
+++ b/board/avionic-design/dts/tegra20-plutux.dts
@@ -14,20 +14,6 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = <216000000>;
 	};
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 50ea3b5..bf3ff1d 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -14,24 +14,34 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
+	host1x {
+		status = "okay";
 
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
+		dc@54200000 {
+			status = "okay";
 
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
+			rgb {
+				nvidia,panel = <&lcd_panel>;
+				status = "okay";
+			};
+		};
 	};
 
 	serial@70006300 {
 		clock-frequency = <216000000>;
 	};
 
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
 	i2c@7000c000 {
 		status = "disabled";
 	};
@@ -56,14 +66,22 @@
 		status = "disabled";
 	};
 
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
+	lcd_panel: panel {
+		clock = <33260000>;
+		xres = <800>;
+		yres = <480>;
+		left-margin = <120>;
+		right-margin = <120>;
+		hsync-len = <16>;
+		lower-margin = <15>;
+		upper-margin = <15>;
+		vsync-len = <15>;
+
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 500000>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+		nvidia,panel-timings = <0 0 0 0>;
 	};
 };
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index b25887b..c0ea1c6 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -44,7 +44,6 @@
 
 #ifdef CONFIG_OF_LIBFDT
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif /* CONFIG_OF_LIBFDT */
 
diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
index 9e3e169..31b064d 100644
--- a/board/compal/dts/tegra20-paz00.dts
+++ b/board/compal/dts/tegra20-paz00.dts
@@ -14,17 +14,15 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
 		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
 	};
 
 	serial@70006000 {
@@ -54,4 +52,25 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	lcd_panel: panel {
+		/* PAZ00 has 1024x600 */
+		clock = <54030000>;
+		xres = <1024>;
+		yres = <600>;
+		right-margin = <160>;
+		left-margin = <24>;
+		hsync-len = <136>;
+		upper-margin = <3>;
+		lower-margin = <61>;
+		vsync-len = <6>;
+		hsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 0>;
+		nvidia,backlight-enable-gpios = <&gpio 164 0>;	/* PU4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 102 0>;	/* PM6 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 4 0>;		/* PA4 */
+		nvidia,panel-timings = <400 4 203 17 15>;
+	};
 };
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 6492d41..1447f47 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -71,3 +71,14 @@ int board_mmc_init(bd_t *bd)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_LCD
+/* this is a weak define that we are overriding */
+void pin_mux_display(void)
+{
+	debug("init display pinmux\n");
+
+	/* EN_VDD_PANEL GPIO A4 */
+	pinmux_tristate_disable(PINGRP_DAP2);
+}
+#endif
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts
index 4450674..7aeed67 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -15,19 +15,6 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006000 {
 		clock-frequency = <216000000>;
 	};
@@ -36,6 +23,11 @@
 		status = "disabled";
 	};
 
+	spi@7000c380 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
 	i2c@7000c400 {
 		status = "disabled";
 	};
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
deleted file mode 100644
index 8a871cf..0000000
--- a/board/dbau1x00/u-boot.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data*) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata*) }
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		#include <u-boot.lst>
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss*) }
-	.bss (NOLOAD)  : { *(.bss*) . = ALIGN(4); }
-	uboot_end = .;
-}
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
deleted file mode 100644
index 2f26470..0000000
--- a/board/eNET/eNET.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc520.h>
-#include <net.h>
-#include <netdev.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-#include "hardware.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-static void enet_timer_isr(void);
-static void enet_toggle_run_led(void);
-static void enet_setup_pars(void);
-
-/*
- * Miscellaneous platform dependent initializations
- */
-int board_early_init_f(void)
-{
-	u16 pio_out_cfg = 0x0000;
-
-	/* Configure General Purpose Bus timing */
-	writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
-	writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
-	writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
-	writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
-	writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
-	writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
-	writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
-
-	/* Configure Programmable Input/Output Pins */
-	writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
-	writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
-	writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
-	writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
-	writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
-	writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
-
-	/*
-	 * Turn off top board
-	 * Set StrataFlash chips to 16-bit width
-	 * Set StrataFlash chips to normal (non reset/power down) mode
-	 */
-	pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
-	writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
-
-	/* Turn off auxiliary power output */
-	writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
-
-	/* Clear FPGA program mode */
-	writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
-
-	enet_setup_pars();
-
-	/* Disable Watchdog */
-	writew(0x3333, &sc520_mmcr->wdtmrctl);
-	writew(0xcccc, &sc520_mmcr->wdtmrctl);
-	writew(0x0000, &sc520_mmcr->wdtmrctl);
-
-	/* Chip Select Configuration */
-	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
-	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
-	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
-
-	writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
-	writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
-	writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
-
-	writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
-	writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
-
-	/* enable posted-writes */
-	writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
-
-	return 0;
-}
-
-static void enet_setup_pars(void)
-{
-	/*
-	 * PARs 11 and 12 are 2MB SRAM @ 0x19000000
-	 *
-	 * These are setup now because older version of U-Boot have them
-	 * mapped to a different PAR which gets clobbered which prevents
-	 * using SRAM for warm-booting a new image
-	 */
-	writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
-	writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
-
-	/* PARs 0 and 1 are Compact Flash slots (4kB each) */
-	writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
-	writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
-
-	/* PAR 2 is used for Cache-As-RAM */
-
-	/*
-	 * PARs 5 through 8 are additional NS16550 UARTS
-	 * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
-	 */
-	writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
-	writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
-	writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
-	writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
-
-	/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
-	writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
-	writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
-
-	/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
-	writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
-
-	/*
-	 * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
-	 * Already configured in board_init16 (eNET_start16.S)
-	 *
-	 * PAR 15 is Boot ROM
-	 * Already configured in board_init16 (eNET_start16.S)
-	 */
-}
-
-
-int board_early_init_r(void)
-{
-	/* CPU Speed to 100MHz */
-	gd->cpu_clk = 100000000;
-
-	/* Crystal is 33.000MHz */
-	gd->bus_clk = 33000000;
-
-	return 0;
-}
-
-void show_boot_progress(int val)
-{
-	uchar led_mask;
-
-	led_mask = 0x00;
-
-	if (val < 0)
-		led_mask |= LED_ERR_BITMASK;
-
-	led_mask |= (uchar)(val & 0x001f);
-	outb(led_mask, LED_LATCH_ADDRESS);
-}
-
-
-int last_stage_init(void)
-{
-	outb(0x00, LED_LATCH_ADDRESS);
-
-	register_timer_isr(enet_timer_isr);
-
-	printf("Serck Controls eNET\n");
-
-	return 0;
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	if (banknum == 0) {	/* non-CFI boot flash */
-		info->portwidth = FLASH_CFI_8BIT;
-		info->chipwidth = FLASH_CFI_BY8;
-		info->interface = FLASH_CFI_X8;
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void setup_pcat_compatibility()
-{
-	/* disable global interrupt mode */
-	writeb(0x40, &sc520_mmcr->picicr);
-
-	/* set all irqs to edge */
-	writeb(0x00, &sc520_mmcr->pic_mode[0]);
-	writeb(0x00, &sc520_mmcr->pic_mode[1]);
-	writeb(0x00, &sc520_mmcr->pic_mode[2]);
-
-	/*
-	 *  active low polarity on PIC interrupt pins,
-	 *  active high polarity on all other irq pins
-	 */
-	writew(0x0000, &sc520_mmcr->intpinpol);
-
-	/*
-	 * PIT 0 -> IRQ0
-	 * RTC -> IRQ8
-	 * FP error -> IRQ13
-	 * UART1 -> IRQ4
-	 * UART2 -> IRQ3
-	 */
-	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
-	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
-	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
-	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
-	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
-
-	/* Disable all other interrupt sources */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
-}
-
-void enet_timer_isr(void)
-{
-	static long enet_ticks;
-
-	enet_ticks++;
-
-	/* Toggle Watchdog every 100ms */
-	if ((enet_ticks % 100) == 0)
-		hw_watchdog_reset();
-
-	/* Toggle Run LED every 500ms */
-	if ((enet_ticks % 500) == 0)
-		enet_toggle_run_led();
-}
-
-void hw_watchdog_reset(void)
-{
-	/* Watchdog Reset must be atomic */
-	long flag = disable_interrupts();
-
-	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
-		sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
-	else
-		sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
-
-	if (flag)
-		enable_interrupts();
-}
-
-void enet_toggle_run_led(void)
-{
-	unsigned char leds_state = inb(LED_LATCH_ADDRESS);
-	if (leds_state & LED_RUN_BITMASK)
-		outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-	else
-		outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-}
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
deleted file mode 100644
index 5af4ef7..0000000
--- a/board/eNET/eNET_pci.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/pci.h>
-#include <asm/arch/pci.h>
-
-static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	/* a configurable lists of IRQs to steal when we need one */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index;
-
-	uchar tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin -= 1; /* PCI config space use 1-based numbering */
-	if (pin == -1)
-		return; /* device use no irq */
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 12:	/* First Ethernet Chip */
-		pin += SC520_PCI_INTA;
-		break;
-
-	case 13:	/* Second Ethernet Chip */
-		pin += SC520_PCI_INTB;
-		break;
-
-	default:
-		return;
-	}
-
-	pin &= 3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3)
-			return;
-
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
-			return;
-
-		next_irq_index++;
-	}
-
-	if (-1 != sc520_pci_ints[pin])
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-
-	printf("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-}
-
-static struct pci_controller enet_hose = {
-	fixup_irq: pci_enet_fixup_irq,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&enet_hose);
-}
-
-int pci_set_regions(struct pci_controller *hose)
-{
-	/* System memory space */
-	pci_set_region(hose->regions + 0,
-		       SC520_PCI_MEMORY_BUS,
-		       SC520_PCI_MEMORY_PHYS,
-		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* ISA/PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       SC520_ISA_MEM_BUS,
-		       SC520_ISA_MEM_PHYS,
-		       SC520_ISA_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region(hose->regions + 2,
-		       SC520_PCI_IO_BUS,
-		       SC520_PCI_IO_PHYS,
-		       SC520_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	/* ISA/PCI I/O space */
-	pci_set_region(hose->regions + 3,
-		       SC520_ISA_IO_BUS,
-		       SC520_ISA_IO_PHYS,
-		       SC520_ISA_IO_SIZE,
-		       PCI_REGION_IO);
-
-	return 4;
-}
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
deleted file mode 100644
index 5e3f44c..0000000
--- a/board/eNET/eNET_start16.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * 16bit initialization code.
- * This code have to map the area of the boot flash
- * that is used by U-boot to its final destination.
- */
-
-#include "config.h"
-#include "hardware.h"
-#include <asm/arch/sc520.h>
-#include <generated/asm-offsets.h>
-
-.text
-.section .start16, "ax"
-.code16
-.globl board_init16
-board_init16:
-	/* Alias MMCR to 0xdf000 */
-	movw	$0xfffc, %dx
-	movl	$0x800df0cb, %eax
-	outl	%eax, %dx
-
-	/* Set ds to point to MMCR alias */
-	movw	$0xdf00, %ax
-	movw	%ax, %ds
-
-	/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
-	movl    $GENERATED_SC520_PAR14, %edi
-	movl	$CONFIG_SYS_SC520_BOOTCS_PAR, %eax
-	movl	%eax, (%di)
-
-	/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
-	movl    $GENERATED_SC520_PAR15, %edi
-	movl	$CONFIG_SYS_SC520_LLIO_PAR, %eax
-	movl	%eax, (%di)
-
-	/* Disabe MMCR alias */
-	movw	$0xfffc, %dx
-	movl	$0x000000cb, %eax
-	outl	%eax, %dx
-
-	jmp	board_init16_ret
-
-.section .bios, "ax"
-.code16
-.globl realmode_reset
-.hidden realmode_reset
-.type realmode_reset, @function
-realmode_reset:
-	/* Alias MMCR to 0xdf000 */
-	movw	$0xfffc, %dx
-	movl	$0x800df0cb, %eax
-	outl	%eax, %dx
-
-	/* Set ds to point to MMCR alias */
-	movw	$0xdf00, %ax
-	movw	%ax, %ds
-
-	/* issue software reset thorugh MMCR */
-	movl    $0xd72, %edi
-	movb	$0x01, %al
-	movb	%al, (%di)
-
-1:	hlt
-	jmp	1
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index f3dc20b..9c211ac 100644
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -88,7 +88,7 @@ static void galsdma_enable_rx(void);
 
 
 /* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
-#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack[0]))
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0]))
 
 #define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
 #define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
diff --git a/board/eNET/Makefile b/board/freescale/b4860qds/Makefile
index ad1c5b1..06018f4 100644
--- a/board/eNET/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -1,12 +1,5 @@
 #
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+# Copyright 2012 Freescale Semiconductor, Inc.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -18,7 +11,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -31,16 +24,25 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS-y	+= eNET.o
-COBJS-$(CONFIG_PCI) += eNET_pci.o
-SOBJS-y	+= eNET_start16.o
-SOBJS-y	+= eNET_start.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
+COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
 
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
 
 #########################################################################
 
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
new file mode 100644
index 0000000..41887c2
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "b4860qds.h"
+#include "b4860qds_qixis.h"
+#include "b4860qds_crossbar_con.h"
+
+#define CLK_MUX_SEL_MASK	0x4
+#define ETH_PHY_CLK_OUT		0x4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	unsigned int i;
+	static const char *const freq[] = {"100", "125", "156.25", "161.13",
+						"122.88", "122.88", "122.88"};
+	int clock;
+
+	printf("Board: %sQDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+		QIXIS_READ(id), QIXIS_READ(arch));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw >= 0x8 && sw <= 0xE)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d (%s), build %d",
+		(int)QIXIS_READ(scver), qixis_read_tag(buf),
+		(int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 5) & 7;
+	printf("Bank1=%sMHz ", freq[clock]);
+	sw = QIXIS_READ(brdcfg[4]);
+	clock = (sw >> 6) & 3;
+	printf("Bank2=%sMHz\n", freq[clock]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca(u8 ch)
+{
+	int ret;
+
+	/* Selecting proper channel via PCA*/
+	ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
+	if (ret) {
+		printf("PCA: failed to select proper channel.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int configure_vsc3316_3308(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	unsigned int num_vsc16_con, num_vsc08_con;
+	u32 serdes1_prtcl, serdes2_prtcl;
+	int ret;
+
+	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	if (!serdes1_prtcl) {
+		printf("SERDES1 is not enabled\n");
+		return 0;
+	}
+	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	if (!serdes2_prtcl) {
+		printf("SERDES2 is not enabled\n");
+		return 0;
+	}
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+	switch (serdes1_prtcl) {
+	case 0x2a:
+	case 0x2C:
+	case 0x2D:
+	case 0x2E:
+			/*
+			 * Configuration:
+			 * SERDES: 1
+			 * Lanes: A,B: SGMII
+			 * Lanes: C,D,E,F,G,H: CPRI
+			 */
+		debug("Configuring crossbar to use onboard SGMII PHYs:"
+				"srds_prctl:%x\n", serdes1_prtcl);
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+
+#ifdef CONFIG_PPC_B4420
+	case 0x18:
+			/*
+			 * Configuration:
+			 * SERDES: 1
+			 * Lanes: A,B,C,D: SGMII
+			 * Lanes: E,F,G,H: CPRI
+			 */
+		debug("Configuring crossbar to use onboard SGMII PHYs:"
+				"srds_prctl:%x\n", serdes1_prtcl);
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_sgmii_lane_cd, num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_sgmii_lane_cd, num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+#endif
+
+	case 0x3E:
+	case 0x0D:
+	case 0x0E:
+	case 0x12:
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_sfp, num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_sfp, num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+	default:
+		printf("WARNING:VSC crossbars programming not supported for:%x"
+					" SerDes1 Protocol.\n", serdes1_prtcl);
+		return -1;
+	}
+
+	switch (serdes2_prtcl) {
+	case 0x9E:
+	case 0x9A:
+	case 0x98:
+	case 0xb2:
+	case 0x49:
+	case 0x4E:
+	case 0x8D:
+	case 0x7A:
+		num_vsc08_con = NUM_CON_VSC3308;
+		/* Configure VSC3308 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3308);
+		if (!ret) {
+			ret = vsc3308_config(VSC3308_TX_ADDRESS,
+					vsc08_tx_amc, num_vsc08_con);
+			if (ret)
+				return ret;
+			ret = vsc3308_config(VSC3308_RX_ADDRESS,
+					vsc08_rx_amc, num_vsc08_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+	default:
+		printf("WARNING:VSC crossbars programming not supported for: %x"
+					" SerDes2 Protocol.\n", serdes2_prtcl);
+		return -1;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	/* Configure VSC3316 and VSC3308 crossbar switches */
+	if (configure_vsc3316_3308())
+		printf("VSC:failed to configure VSC3316/3308.\n");
+	else
+		printf("VSC:VSC3316/3308 successfully configured.\n");
+
+	select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((sysclk_conf & 0x0C) >> 2) {
+	case QIXIS_CLK_100:
+		return 100000000;
+	case QIXIS_CLK_125:
+		return 125000000;
+	case QIXIS_CLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (ddrclk_conf & 0x03) {
+	case QIXIS_CLK_100:
+		return 100000000;
+	case QIXIS_CLK_125:
+		return 125000000;
+	case QIXIS_CLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+static int serdes_refclock(u8 sw, u8 sdclk)
+{
+	unsigned int clock;
+	int ret = -1;
+	u8 brdcfg4;
+
+	if (sdclk == 1) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
+			return SRDS_PLLCR0_RFCK_SEL_125;
+		else
+			clock = (sw >> 5) & 7;
+	} else
+		clock = (sw >> 6) & 3;
+
+	switch (clock) {
+	case 0:
+		ret = SRDS_PLLCR0_RFCK_SEL_100;
+		break;
+	case 1:
+		ret = SRDS_PLLCR0_RFCK_SEL_125;
+		break;
+	case 2:
+		ret = SRDS_PLLCR0_RFCK_SEL_156_25;
+		break;
+	case 3:
+		ret = SRDS_PLLCR0_RFCK_SEL_161_13;
+		break;
+	case 4:
+	case 5:
+	case 6:
+		ret = SRDS_PLLCR0_RFCK_SEL_122_88;
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.13";
+	default:
+		return "122.88";
+	}
+}
+
+#define NUM_SRDS_BANKS	2
+
+int misc_init_r(void)
+{
+	u8 sw;
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	int clock;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = serdes_refclock(sw, 1);
+	if (clock >= 0)
+		actual[0] = clock;
+	else
+		printf("Warning: SDREFCLK1 switch setting is unsupported\n");
+
+	sw = QIXIS_READ(brdcfg[4]);
+	clock = serdes_refclock(sw, 2);
+	if (clock >= 0)
+		actual[1] = clock;
+	else
+		printf("Warning: SDREFCLK2 switch setting unsupported\n");
+
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 pllcr0 = srds_regs->bank[i].pllcr0;
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * Dump board switch settings.
+ * The bits that cannot be read/sampled via some FPGA or some
+ * registers, they will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+	int i;
+	u8 sw[5];
+
+	/*
+	 * Any bit with 1 means that bit cannot be reverse engineered.
+	 * It will be displayed as _ in binary format.
+	 */
+	static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
+	char buf[10];
+	u8 brdcfg[16], dutcfg[16];
+
+	for (i = 0; i < 16; i++) {
+		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+	}
+
+	sw[0] = ((brdcfg[0] & 0x0f) << 4)	| \
+		(brdcfg[9] & 0x08);
+	sw[1] = ((dutcfg[1] & 0x01) << 7)	| \
+		((dutcfg[2] & 0x07) << 4)       | \
+		((dutcfg[6] & 0x10) >> 1)       | \
+		((dutcfg[6] & 0x80) >> 5)       | \
+		((dutcfg[1] & 0x40) >> 5)       | \
+		(dutcfg[6] & 0x01);
+	sw[2] = dutcfg[0];
+	sw[3] = 0;
+	sw[4] = ((brdcfg[1] & 0x30) << 2)	| \
+		((brdcfg[1] & 0xc0) >> 2)	| \
+		(brdcfg[1] & 0x0f);
+
+	puts("DIP switch settings:\n");
+	for (i = 0; i < 5; i++) {
+		printf("SW%d         = 0b%s (0x%02x)\n",
+			i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+	}
+}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
new file mode 100644
index 0000000..f290f3c
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
new file mode 100644
index 0000000..994dec5
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_CONNECTIONS_H__
+#define __CROSSBAR_CONNECTIONS_H__
+
+#define NUM_CON_VSC3316	8
+#define NUM_CON_VSC3308	4
+
+static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
+				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
+
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
+				{5, 15}, {4, 14}, {2, 12}, {12, 13} };
+
+static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15},
+		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+#ifdef CONFIG_PPC_B4420
+static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
+			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
+				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
+
+static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12},
+		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+#ifdef CONFIG_PPC_B4420
+static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+
+static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
+
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+
+static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
+
+static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+
+#endif
diff --git a/board/qi/qi_lb60/u-boot.lds b/board/freescale/b4860qds/b4860qds_qixis.h
index b3cb869..575b2ae 100644
--- a/board/qi/qi_lb60/u-boot.lds
+++ b/board/freescale/b4860qds/b4860qds_qixis.h
@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ * Copyright 2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -18,46 +17,21 @@
  * MA 02111-1307 USA
  */
 
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+#ifndef __B4860QDS_QIXIS_H__
+#define __B4860QDS_QIXIS_H__
 
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
+/* Definitions of QIXIS Registers for B4860QDS */
 
-	. = ALIGN(4);
-	.text :
-	{
-	  *(.text*)
-	}
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
 
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+/* CLK */
+#define QIXIS_CLK_66		0x0
+#define QIXIS_CLK_100		0x1
+#define QIXIS_CLK_125		0x2
+#define QIXIS_CLK_133		0x3
 
-	. = ALIGN(4);
-	.data  : { *(.data*) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata*) }
-
-
-	. = ALIGN(4);
-	.u_boot_list : {
-	#include <u-boot.lst>
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss*) }
-	.bss  : { *(.bss*) . = ALIGN(4); }
-	uboot_end = .;
-}
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
new file mode 100644
index 0000000..dd4c0f6
--- /dev/null
+++ b/board/freescale/b4860qds/ddr.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 2147483648u,
+	.capacity = 4294967296u,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 1,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,	/* ECC */
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1071,
+	.caslat_X = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
+	.tAA_ps = 13910,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13910,
+	.tRRD_ps = 6000,
+	.tRP_ps = 13910,
+	.tRAS_ps = 34000,
+	.tRC_ps = 48910,
+	.tRFC_ps = 260000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 35000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "RAW timing DDR";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
+	{2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
+	{2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
+	{1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
+	{1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
+	{1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->twoT_en = pbsp->force_2T;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->twoT_en = pbsp_highest->force_2T;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
new file mode 100644
index 0000000..68e2725
--- /dev/null
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Author: Sandeep Kumar Singh <sandeep@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
+ * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
+ * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
+ * one Fman device on B4860. The SERDES configuration is used to determine
+ * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
+ * to which PHYs. So for a given Fman MAC, there is one and only PHY it
+ * connects to. MACs cannot be routed to PHYs dynamically. This configuration
+ * is done at boot time by reading SERDES protocol from RCW.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+#define EMI_NONE       0xFFFFFFFF
+
+#ifdef CONFIG_FMAN_ENET
+
+/*
+ * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
+ * lane at index is mapped to slot number n. A value of '0' will mean
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	1, 1, 1, 1,
+	0, 0, 0, 0
+};
+
+/*
+ * This function initializes the lane_to_slot[] array. It reads RCW to check
+ * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
+ * lane_to_slot[] accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+	unsigned int  serdes2_prtcl;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Initializing lane to slot: Serdes2 protocol: %x\n",
+			serdes2_prtcl);
+
+	switch (serdes2_prtcl) {
+	case 0x18:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: SGMII
+		 * Lanes: E,F: Aur
+		 * Lanes: G,H: SRIO
+		 */
+	case 0x91:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B: SGMII
+		 * Lanes: C,D: SRIO2
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x93:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: SGMII
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x98:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: XAUI2
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x9a:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B: PCI
+		 * Lanes: C,D: SGMII
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x9e:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: PCI
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0xb2:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: PCI
+		 * Lanes: E,F: SGMII 3&4
+		 * Lanes: G,H: XFI
+		 */
+	case 0xc2:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B: SGMII
+		 * Lanes: C,D: SRIO2
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+		lane_to_slot[12] = 2;
+		lane_to_slot[13] = lane_to_slot[12];
+		lane_to_slot[14] = lane_to_slot[12];
+		lane_to_slot[15] = lane_to_slot[12];
+		break;
+
+	default:
+		printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+				serdes2_prtcl);
+			break;
+	}
+	return;
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	struct memac_mdio_info tg_memac_mdio_info;
+	unsigned int i;
+	unsigned int  serdes1_prtcl, serdes2_prtcl;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	if (!serdes1_prtcl) {
+		printf("SERDES1 is not enabled\n");
+		return 0;
+	}
+	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	if (!serdes2_prtcl) {
+		printf("SERDES2 is not enabled\n");
+		return 0;
+	}
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+	printf("Initializing Fman\n");
+
+	initialize_lane_to_slot();
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	tg_memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the real 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tg_memac_mdio_info);
+
+	/*
+	 * Program the two on board DTSEC PHY addresses assuming that they are
+	 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
+	 * 6 to on board SGMII phys
+	 */
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+
+	switch (serdes1_prtcl) {
+	case 0x2a:
+		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
+		debug("Setting phy addresses for FM1_DTSEC5: %x and"
+			"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+			CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		/* Fixing Serdes clock by programming FPGA register */
+		QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+		fm_info_set_phy_address(FM1_DTSEC5,
+				CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6,
+				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		break;
+#ifdef CONFIG_PPC_B4420
+	case 0x18:
+		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
+		debug("Setting phy addresses for FM1_DTSEC3: %x and"
+			"FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+			CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		/* Fixing Serdes clock by programming FPGA register */
+		QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+		fm_info_set_phy_address(FM1_DTSEC3,
+				CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4,
+				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		break;
+#endif
+	default:
+		printf("Fman:  Unsupported SerDes1 Protocol 0x%02x\n",
+				serdes1_prtcl);
+		break;
+	}
+	switch (serdes2_prtcl) {
+	case 0x18:
+		debug("Setting phy addresses on SGMII Riser card for"
+				"FM1_DTSEC ports: \n");
+		fm_info_set_phy_address(FM1_DTSEC1,
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2,
+				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3,
+				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4,
+				CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
+		break;
+	case 0x49:
+		debug("Setting phy addresses on SGMII Riser card for"
+				"FM1_DTSEC ports: \n");
+		fm_info_set_phy_address(FM1_DTSEC1,
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2,
+				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3,
+				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+		break;
+	case 0x8d:
+	case 0xb2:
+		debug("Setting phy addresses on SGMII Riser card for"
+				"FM1_DTSEC ports: \n");
+		fm_info_set_phy_address(FM1_DTSEC3,
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4,
+				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+		break;
+	default:
+		printf("Fman:  Unsupported SerDes2 Protocol 0x%02x\n",
+				serdes2_prtcl);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			fm_info_set_mdio(i,
+				miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+					idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	int phy;
+	char alias[32];
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		phy = fm_info_get_phy_address(port);
+
+		sprintf(alias, "phy_sgmii_%x", phy);
+		fdt_set_phy_handle(fdt, compat, addr, alias);
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i;
+	char alias[32];
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_NONE:
+			sprintf(alias, "ethernet%u", i);
+			fdt_status_disabled_by_alias(fdt, alias);
+			break;
+		default:
+			break;
+		}
+	}
+}
diff --git a/board/micronas/vct/u-boot.lds b/board/freescale/b4860qds/law.c
index 2ce8d0e..4142e01 100644
--- a/board/micronas/vct/u-boot.lds
+++ b/board/freescale/b4860qds/law.c
@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,49 +20,25 @@
  * MA 02111-1307 USA
  */
 
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data*) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata*) }
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		#include <u-boot.lst>
-	}
-
-	. = ALIGN(4);
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss*) }
-	. = ALIGN(4);
-	.bss (NOLOAD)  : { *(.bss*) }
-	uboot_end = .;
-}
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/eNET/eNET_start.S b/board/freescale/b4860qds/pci.c
index 0dec7ea..b130d13 100644
--- a/board/eNET/eNET_start.S
+++ b/board/freescale/b4860qds/pci.c
@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,10 +20,20 @@
  * MA 02111-1307 USA
  */
 
-#include "hardware.h"
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
 
-/* board early intialization */
-.globl early_board_init
-early_board_init:
-	/* No 32-bit board specific initialisation */
-	jmp	early_board_init_ret
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
new file mode 100644
index 0000000..373cb78
--- /dev/null
+++ b/board/freescale/b4860qds/tlb.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+                      CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 11, BOOKE_PAGESZ_64K, 1),
+#endif
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_4K, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 2e0e55f..fe870b6 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -59,7 +59,7 @@ int checkboard(void)
 {
 	struct cpu_type *cpu;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	printf("Board: %sRDB\n", cpu->name);
 
 	return 0;
diff --git a/board/isee/igep0030/Makefile b/board/freescale/bsc9132qds/Makefile
index cbc03d4..267400b 100644
--- a/board/isee/igep0030/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -1,6 +1,5 @@
 #
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2013 Freescale Semiconductor, Inc.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -12,7 +11,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -25,14 +24,24 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= igep0030.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
 
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS)
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
new file mode 100644
index 0000000..4a3dbfe
--- /dev/null
+++ b/board/freescale/bsc9132qds/README
@@ -0,0 +1,150 @@
+Overview
+--------
+ The BSC9132 is a highly integrated device that targets the evolving
+ Microcell, Picocell, and Enterprise-Femto base station market subsegments.
+
+ The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
+ core technologies with MAPLE-B2P baseband acceleration processing elements
+ to address the need for a high performance, low cost, integrated solution
+ that handles all required processing layers without the need for an
+ external device except for an RF transceiver or, in a Micro base station
+ configuration, a host device that handles the L3/L4 and handover between
+ sectors.
+
+ The BSC9132 SoC includes the following function and features:
+    - Power Architecture subsystem including two e500 processors with
+	512-Kbyte shared L2 cache
+    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
+	cache
+    - 32 Kbyte of shared M3 memory
+    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
+      Processing (MAPLE-B2P)
+    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
+      ECC), up to 1333 MHz data rate
+    - Dedicated security engine featuring trusted boot
+    - Two DMA controllers
+         - OCNDMA with four bidirectional channels
+         - SysDMA with sixteen bidirectional channels
+    - Interfaces
+        - Four-lane SerDes PHY
+	    - PCI Express controller complies with the PEX Specification-Rev 2.0
+        - Two Common Public Radio Interface (CPRI) controller lanes
+	    - High-speed USB 2.0 host and device controller with ULPI interface
+        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
+	    - Antenna interface controller (AIC), supporting four industry
+		standard JESD207/four custom ADI RF interfaces
+       - ADI lanes support both full duplex FDD support & half duplex TDD
+       - Universal Subscriber Identity Module (USIM) interface that
+	   facilitates communication to SIM cards or Eurochip pre-paid phone
+	   cards
+       - Two DUART, two eSPI, and two I2C controllers
+       - Integrated Flash memory controller (IFC)
+       - GPIO
+     - Sixteen 32-bit timers
+
+The SC3850 core subsystem consists of the following:
+ - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
+ - 32 KB, 8-way, level 1 data cache (L1 DCache)
+ - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
+ - Memory management unit (MMU)
+ - Global interrupt controller ( GIC)
+ - Debug and profiling unit (DPU)
+ - Two 32-bit quad timers
+
+BSC9132QDS board Overview
+-------------------------
+ 2Gbyte DDR3 (on board DDR), Dual Ranki
+ 32Mbyte 16bit NOR flash
+ 128Mbyte 2K page size NAND Flash
+ 256 Kbit M24256 I2C EEPROM
+ 128 Mbit SPI Flash memory
+ SD slot
+ USB-ULPI
+ eTSEC1: Connected to SGMII PHY
+ eTSEC2: Connected to SGMII PHY
+ PCIe
+ CPRI
+ SerDes
+ I2C RTC
+ DUART interface: supports one UARTs up to 115200 bps for console display
+
+Frequency Combinations Supported
+--------------------------------
+Core MHz/CCB MHz/DDR(MT/s)
+1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
+     (SYSCLK = 100MHz, DDRCLK = 100MHz)
+2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
+     (SYSCLK = 100MHz, DDRCLK = 133MHz)
+
+Boot Methods Supported
+-----------------------
+1. NOR Flash
+2. NAND Flash
+3. SD Card
+4. SPI flash
+
+Default Boot Method
+--------------------
+NOR boot
+
+Building U-boot
+--------------
+To build the u-boot for BSC9132QDS:
+1. NOR Flash
+	make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
+	make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
+2. NAND Flash : It is currently not supported
+3. SPI Flash
+	make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
+	make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
+4. SD Card
+	make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
+	make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
+
+Memory map
+-----------
+ 0x0000_0000	0x7FFF_FFFF	DDR			2G cacheable
+ 0x8000_0000	0x8FFF_FFFF	NOR Flash		256M
+ 0x9000_0000	0x9FFF_FFFF	PCIe Memory 		256M
+ 0xA000_0000	0xA7FF_FFFF	DSP core1 L2 space	128M
+ 0xB000_0000	0xB0FF_FFFF	DSP core0 M2 space	16M
+ 0xB100_0000	0xB1FF_FFFF	DSP core1 M2 space	16M
+ 0xC000_0000	0xC000_7FFF	M3 Memory		32K
+ 0xC001_0000	0xC001_FFFF	PCI Express I/O		64K
+ 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
+ 0xC1F0_0000	0xC1F7_FFFF	PA SRAM Region 0	512K
+ 0xC1F8_0000	0xC1FB_FFFF	PA SRAM Region 1	512K
+ 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
+ 0xFEE0_0000	0xFEE0_0FFF	DSP Boot ROM		4K
+ 0xFF60_0000	0xFF6F_FFFF 	DSP CCSR		1M
+ 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
+ 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND Buffer 8M
+
+Flashing Images
+---------------
+To place a new u-boot image in the NAND flash and then boot
+with that new image temporarily, use this:
+	tftp 1000000 u-boot-nand.bin
+	nand erase 0 100000
+	nand write 1000000 0 100000
+	reset
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+	dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
+
+Likely, that .dts file will come from here;
+
+	linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+	tftp 1000000 uImage
+	tftp 2000000 rootfs.ext2.gz.uboot
+	tftp c00000 bsc9132qds.dtb
+	bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
new file mode 100644
index 0000000..6e1b558
--- /dev/null
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <asm/fsl_ifc.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#endif
+
+#include "../common/qixis.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+
+int board_early_init_f(void)
+{
+	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+	return 0;
+}
+
+void board_config_serdes_mux(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+	switch (srds_cfg) {
+	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
+	case  1:
+	case  2:
+	case  3:
+	case  4:
+	case  5:
+	case 22:
+	case 23:
+	case 24:
+	case 25:
+	case 26:
+		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
+		break;
+
+	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
+	case  6:
+	case  7:
+	case  8:
+	case  9:
+	case 10:
+	case 27:
+	case 28:
+	case 29:
+	case 30:
+	case 31:
+		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
+		break;
+
+	/* PEX(1) PEX(2) SGMII1 SGMII2 */
+	case 11:
+	case 32:
+		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
+		break;
+
+	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+	case 16:
+	case 33:
+	case 34:
+	case 35:
+	case 36:
+	case 37:
+		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
+		break;
+
+	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
+	case 17:
+	case 18:
+	case 19:
+	case 20:
+	case 21:
+	case 38:
+	case 39:
+	case 40:
+	case 41:
+	case 42:
+		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
+		break;
+
+	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
+	case 43:
+	case 44:
+	case 45:
+	case 46:
+	case 47:
+		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
+		break;
+
+
+	default:
+		break;
+	}
+}
+
+int board_early_init_r(void)
+{
+#ifndef CONFIG_SYS_NO_FLASH
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+	set_tlb(1, flashbase + 0x4000000,
+			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
+#endif
+	board_config_serdes_mux();
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int checkboard(void)
+{
+	struct cpu_type *cpu;
+	u8 sw;
+
+	cpu = gd->arch.cpu;
+	printf("Board: %sQDS\n", cpu->name);
+
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
+	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	printf("IFC chip select:");
+	switch (sw) {
+	case 0:
+		printf("NOR\n");
+		break;
+	case 2:
+		printf("Promjet\n");
+		break;
+	case 4:
+		printf("NAND\n");
+		break;
+	default:
+		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+		break;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+
+#endif
+
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+	tsec_eth_init(bis, tsec_info, num);
+
+	#ifdef CONFIG_PCI
+	pci_eth_init(bis);
+	#endif
+
+	return 0;
+}
+#endif
+
+#define USBMUX_SEL_MASK		0xc0
+#define USBMUX_SEL_UART2	0xc0
+#define USBMUX_SEL_USB		0x40
+#define SPIMUX_SEL_UART3	0x80
+#define GPS_MUX_SEL_GPS		0x40
+
+#define TSEC_1588_CLKIN_MASK	0x03
+#define CON_XCVR_REF_CLK	0x00
+
+int misc_init_r(void)
+{
+	u8 val;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 porbmsr = in_be32(&gur->porbmsr);
+	u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+	/*Configure 1588 clock-in source from RF Card*/
+	val = QIXIS_READ_I2C(brdcfg[5]);
+	QIXIS_WRITE_I2C(brdcfg[5],
+		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
+
+	if (hwconfig("uart2") && hwconfig("usb1")) {
+		printf("UART2 and USB cannot work together on the board\n");
+		printf("Remove one from hwconfig and reset\n");
+	} else {
+		if (hwconfig("uart2")) {
+			val = QIXIS_READ_I2C(brdcfg[5]);
+			QIXIS_WRITE_I2C(brdcfg[5],
+				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
+			clrbits_be32(&gur->pmuxcr3,
+						MPC85xx_PMUXCR3_USB_SEL_MASK);
+			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
+		} else {
+			/* By default USB should be selected.
+			* Programming FPGA to select USB. */
+			val = QIXIS_READ_I2C(brdcfg[5]);
+			QIXIS_WRITE_I2C(brdcfg[5],
+				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
+		}
+
+	}
+
+	if (hwconfig("sim")) {
+		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+			romloc == PORBMSR_ROMLOC_NOR ||
+			romloc == PORBMSR_ROMLOC_SPI) {
+
+			val = QIXIS_READ_I2C(brdcfg[3]);
+			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
+			clrbits_be32(&gur->pmuxcr,
+				MPC85xx_PMUXCR0_SIM_SEL_MASK);
+			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
+		}
+	}
+
+	if (hwconfig("uart3")) {
+		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+			romloc == PORBMSR_ROMLOC_NOR ||
+			romloc == PORBMSR_ROMLOC_SDHC) {
+
+			/* UART3 and SPI1 (Flashes) are muxed together */
+			val = QIXIS_READ_I2C(brdcfg[3]);
+			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
+			clrbits_be32(&gur->pmuxcr3,
+						MPC85xx_PMUXCR3_UART3_SEL_MASK);
+			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
+
+			/* MUX to select UART3 connection to J24 header
+			 * or to GPS */
+			val = QIXIS_READ_I2C(brdcfg[6]);
+			if (hwconfig("gps"))
+				QIXIS_WRITE_I2C(brdcfg[6],
+						(val | GPS_MUX_SEL_GPS));
+			else
+				QIXIS_WRITE_I2C(brdcfg[6],
+						(val & ~(GPS_MUX_SEL_GPS)));
+		}
+	}
+	return 0;
+}
+
+void fdt_del_node_compat(void *blob, const char *compatible)
+{
+	int err;
+	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
+	if (off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+			compatible, fdt_strerror(off));
+		return;
+	}
+	err = fdt_del_node(blob, off);
+	if (err < 0) {
+		printf("WARNING: could not remove %s: %s.\n",
+			compatible, fdt_strerror(err));
+	}
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	#if defined(CONFIG_PCI)
+	FT_FSL_PCI_SETUP;
+	#endif
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 porbmsr = in_be32(&gur->porbmsr);
+	u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
+		/* If uart2 is there in hwconfig remove usb node from
+		 *  device tree */
+
+		if (hwconfig("uart2")) {
+			/* remove dts usb node */
+			fdt_del_node_compat(blob, "fsl-usb2-dr");
+		} else {
+			fdt_fixup_dr_usb(blob, bd);
+			fdt_del_node_and_alias(blob, "serial2");
+		}
+	}
+
+	if (hwconfig("uart3")) {
+		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+			romloc == PORBMSR_ROMLOC_NOR ||
+			romloc == PORBMSR_ROMLOC_SDHC)
+			/* Delete SPI node from the device tree */
+				fdt_del_node_and_alias(blob, "spi1");
+	} else
+		fdt_del_node_and_alias(blob, "serial3");
+
+	if (hwconfig("sim")) {
+		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+			romloc == PORBMSR_ROMLOC_NOR ||
+			romloc == PORBMSR_ROMLOC_SPI) {
+
+			/* remove dts sdhc node */
+			fdt_del_node_compat(blob, "fsl,esdhc");
+		} else if (romloc == PORBMSR_ROMLOC_SDHC) {
+
+			/* remove dts sim node */
+			fdt_del_node_compat(blob, "fsl,sim-v1.0");
+			printf("SIM & SDHC can't work together on the board");
+			printf("\nRemove sim from hwconfig and reset\n");
+		}
+	}
+}
+#endif
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
new file mode 100644
index 0000000..946ad19
--- /dev/null
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{750, 850, &ddr_cfg_regs_800},
+	{1060, 1333, &ddr_cfg_regs_1333},
+	{0, 0, NULL}
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+							sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+					strmhz(buf, ddr_freq));
+
+	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+					LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	}
+
+	return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1870,
+	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
+	.tAA_ps = 13125,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13125,
+	.tRRD_ps = 7500,
+	.tRP_ps = 13125,
+	.tRAS_ps = 37500,
+	.tRC_ps = 50625,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	int i;
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
new file mode 100644
index 0000000..dc23658
--- /dev/null
+++ b/board/freescale/bsc9132qds/law.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
+#endif
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
new file mode 100644
index 0000000..0e4545f
--- /dev/null
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR (PA) */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 3, BOOKE_PAGESZ_64M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_64K, 1),
+#endif
+
+		/* *I*G - Board FPGA  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 9, BOOKE_PAGESZ_256K, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index c92902a..2b74d02 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,8 +14,23 @@
 #include <common.h>
 #include <command.h>
 #include <asm/io.h>
+#include <linux/time.h>
+#include <i2c.h>
 #include "qixis.h"
 
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg)
+{
+	return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+}
+
+void qixis_write_i2c(unsigned int reg, u8 value)
+{
+	u8 val = value;
+	i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+}
+#endif
+
 u8 qixis_read(unsigned int reg)
 {
 	void *p = (void *)QIXIS_BASE;
@@ -30,6 +45,72 @@ void qixis_write(unsigned int reg, u8 value)
 	out_8(p + reg, value);
 }
 
+u16 qixis_read_minor(void)
+{
+	u16 minor;
+
+	/* this data is in little endian */
+	QIXIS_WRITE(tagdata, 5);
+	minor = QIXIS_READ(tagdata);
+	QIXIS_WRITE(tagdata, 6);
+	minor += QIXIS_READ(tagdata) << 8;
+
+	return minor;
+}
+
+char *qixis_read_time(char *result)
+{
+	time_t time = 0;
+	int i;
+
+	/* timestamp is in 32-bit big endian */
+	for (i = 8; i <= 11; i++) {
+		QIXIS_WRITE(tagdata, i);
+		time =  (time << 8) + QIXIS_READ(tagdata);
+	}
+
+	return ctime_r(&time, result);
+}
+
+char *qixis_read_tag(char *buf)
+{
+	int i;
+	char tag, *ptr = buf;
+
+	for (i = 16; i <= 63; i++) {
+		QIXIS_WRITE(tagdata, i);
+		tag = QIXIS_READ(tagdata);
+		*(ptr++) = tag;
+		if (!tag)
+			break;
+	}
+	if (i > 63)
+		*ptr = '\0';
+
+	return buf;
+}
+
+/*
+ * return the string of binary of u8 in the format of
+ * 1010 10_0. The masked bit is filled as underscore.
+ */
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
+{
+	char *ptr;
+	int i;
+
+	ptr = buf;
+	for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
+		*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+	*(ptr++) = ' ';
+	for (i = 0x08; i > 0 ; i >>= 1, ptr++)
+		*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+
+	*ptr = '\0';
+
+	return buf;
+}
+
 void qixis_reset(void)
 {
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
@@ -61,7 +142,6 @@ void set_altbank(void)
 	QIXIS_WRITE(brdcfg[0], reg);
 }
 
-#ifdef DEBUG
 static void qixis_dump_regs(void)
 {
 	int i;
@@ -91,7 +171,14 @@ static void qixis_dump_regs(void)
 	printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
 	printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
 }
-#endif
+
+static void __qixis_dump_switch(void)
+{
+	puts("Reverse engineering switch is not implemented for this board\n");
+}
+
+void qixis_dump_switch(void)
+	__attribute__((weak, alias("__qixis_dump_switch")));
 
 int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -122,16 +209,13 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				return 0;
 			}
 		}
-	}
-
-#ifdef DEBUG
-	else if (strcmp(argv[1], "dump") == 0) {
+	} else if (strcmp(argv[1], "dump") == 0) {
 		qixis_dump_regs();
 		return 0;
-	}
-#endif
-
-	else {
+	} else if (strcmp(argv[1], "switch") == 0) {
+		qixis_dump_switch();
+		return 0;
+	} else {
 		printf("Invalid option: %s\n", argv[1]);
 		return 1;
 	}
@@ -146,7 +230,6 @@ U_BOOT_CMD(
 	"qixis_reset altbank - reset to alternate bank\n"
 	"qixis watchdog <watchdog_period> - set the watchdog period\n"
 	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
-#ifdef DEBUG
 	"qixis_reset dump - display the QIXIS registers\n"
-#endif
+	"qixis_reset switch - display switch\n"
 	);
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index b98b180..8d914d5 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -88,8 +88,21 @@ struct qixis {
 
 u8 qixis_read(unsigned int reg);
 void qixis_write(unsigned int reg, u8 value);
+u16 qixis_read_minor(void);
+char *qixis_read_time(char *result);
+char *qixis_read_tag(char *buf);
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg);
+void qixis_write_i2c(unsigned int reg, u8 value);
+#endif
 
 #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE_I2C(reg, value) \
+			qixis_write_i2c(offsetof(struct qixis, reg), value)
+#endif
 
 #endif
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 21428e3..48f7155 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int checkboard (void)
 {
 	u8 sw;
-	struct cpu_type *cpu = gd->cpu;
+	struct cpu_type *cpu = gd->arch.cpu;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 	unsigned int i;
 	static const char * const freq[] = {"100", "125", "156.25", "212.5" };
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
new file mode 100644
index 0000000..8df19dd
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 58000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 1071803..648f0ec 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -31,7 +31,7 @@
 #include <vsc7385.h>
 #include <ns16550.h>
 #include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
 #include <asm/gpio.h>
 #endif
 
@@ -45,7 +45,7 @@ int board_early_init_f(void)
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		gd->flags |= GD_FLG_SILENT;
 #endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
 	mpc83xx_gpio_init_f();
 #endif
 
@@ -54,7 +54,7 @@ int board_early_init_f(void)
 
 int board_early_init_r(void)
 {
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
 	mpc83xx_gpio_init_r();
 #endif
 
@@ -67,7 +67,7 @@ int checkboard(void)
 	return 0;
 }
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 static struct pci_region pci_regions[] = {
 	{
 		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
@@ -140,7 +140,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 }
 #endif
-#else /* CONFIG_NAND_SPL */
+#else /* CONFIG_SPL_BUILD */
 void board_init_f(ulong bootflag)
 {
 	board_early_init_f();
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 6d00caf..49310bd 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -99,7 +99,7 @@ unsigned long get_sdram_size(void)
 	struct cpu_type *cpu;
 	phys_size_t ddr_size;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	/* P1014 and it's derivatives support max 16it DDR width */
 	if (cpu->soc_ver == SVR_P1014)
 		ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
@@ -144,7 +144,7 @@ phys_size_t fixed_sdram(void)
 		panic("Unsupported DDR data rate %s MT/s data rate\n",
 					strmhz(buf, ddr_freq));
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	/* P1014 and it's derivatives support max 16bit DDR width */
 	if (cpu->soc_ver == SVR_P1014) {
 		ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
@@ -237,7 +237,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->trwt_override = 1;
 	popts->trwt = 0;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	/* P1014 and it's derivatives support max 16it DDR width */
 	if (cpu->soc_ver == SVR_P1014)
 		popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index dfeb86f..11e2e8a 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -164,7 +164,7 @@ int checkboard(void)
 {
 	struct cpu_type *cpu;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	printf("Board: %sRDB\n", cpu->name);
 
 	return 0;
@@ -178,7 +178,7 @@ int board_eth_init(bd_t *bis)
 	struct cpu_type *cpu;
 	int num = 0;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 
 #ifdef CONFIG_TSEC1
 	SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -283,7 +283,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 	phys_size_t size;
 	struct cpu_type *cpu;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 
 	ft_cpu_setup(blob, bd);
 
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 916439c..b16b8c8 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -202,7 +202,7 @@ phys_size_t fixed_sdram (void)
 	struct cpu_type *cpu;
 	ulong ddr_freq, ddr_freq_mhz;
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	/* P1020 and it's derivatives support max 32bit DDR width */
 	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
 		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 437eaf0..9c6683d 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -108,7 +108,7 @@ int checkboard (void)
 	else
 		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
 
 	setbits_be32(&pgpio->gpdir, GPIO_DIR);
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index fec9777..4b0d577 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -136,11 +136,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
 
-#define CPLD_LANE_A_SEL	0x1
-#define CPLD_LANE_G_SEL	0x2
-#define CPLD_LANE_C_SEL	0x4
-#define CPLD_LANE_D_SEL	0x8
-
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
@@ -148,10 +143,6 @@ int board_eth_init(bd_t *bis)
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
 	int lane;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-	u8 mux = CPLD_READ(serdes_mux);
 
 	printf("Initializing Fman\n");
 
@@ -181,36 +172,6 @@ int board_eth_init(bd_t *bis)
 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
 
-	mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
-	switch (srds_prtcl) {
-	case 0x2:
-	case 0xf:
-		mux &= ~CPLD_LANE_G_SEL;
-		break;
-	case 0x5:
-	case 0x9:
-	case 0xa:
-	case 0x17:
-		mux |= CPLD_LANE_G_SEL;
-		break;
-	case 0x14:
-		mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
-		break;
-	case 0x8:
-	case 0x16:
-	case 0x19:
-	case 0x1a:
-		mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
-		break;
-	case 0x1c:
-		mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
-		break;
-	default:
-		printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
-		break;
-	}
-	CPLD_WRITE(serdes_mux, mux);
-
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;
 
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index d2732f5..a706a6d 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
 	u8 sw;
-	struct cpu_type *cpu = gd->cpu;
+	struct cpu_type *cpu = gd->arch.cpu;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 	unsigned int i;
 
@@ -101,6 +101,49 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#define CPLD_LANE_A_SEL	0x1
+#define CPLD_LANE_G_SEL	0x2
+#define CPLD_LANE_C_SEL	0x4
+#define CPLD_LANE_D_SEL	0x8
+
+void board_config_lanes_mux(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	u8 mux = 0;
+	switch (srds_prtcl) {
+	case 0x2:
+	case 0x5:
+	case 0x9:
+	case 0xa:
+	case 0xf:
+		break;
+	case 0x8:
+		mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+		break;
+	case 0x14:
+		mux |= CPLD_LANE_A_SEL;
+		break;
+	case 0x17:
+		mux |= CPLD_LANE_G_SEL;
+		break;
+	case 0x16:
+	case 0x19:
+	case 0x1a:
+		mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+		break;
+	case 0x1c:
+		mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+		break;
+	default:
+		printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+		break;
+	}
+	CPLD_WRITE(serdes_mux, mux);
+}
+
 int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@@ -124,6 +167,7 @@ int board_early_init_r(void)
 
 	set_liodns();
 	setup_portals();
+	board_config_lanes_mux();
 
 	return 0;
 }
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 5debcf6..6f2c5c8 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -40,7 +40,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 88b8ced..3c95f3f 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -42,16 +42,29 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
+
 int checkboard(void)
 {
+	char buf[64];
 	u8 sw;
-	struct cpu_type *cpu = gd->cpu;
+	struct cpu_type *cpu = gd->arch.cpu;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 	unsigned int i;
 
 	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+		QIXIS_READ(id), QIXIS_READ(arch));
 
 	sw = QIXIS_READ(brdcfg[0]);
 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -65,6 +78,12 @@ int checkboard(void)
 	else
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
+	printf("FPGA: v%d (%s), build %d",
+		(int)QIXIS_READ(scver), qixis_read_tag(buf),
+		(int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
 	/* Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
@@ -393,3 +412,63 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_board_enet(blob);
 #endif
 }
+
+/*
+ * Reverse engineering switch settings.
+ * Some bits cannot be figured out. They will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+	int i;
+	u8 sw[9];
+
+	/*
+	 * Any bit with 1 means that bit cannot be reverse engineered.
+	 * It will be displayed as _ in binary format.
+	 */
+	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
+	char buf[10];
+	u8 brdcfg[16], dutcfg[16];
+
+	for (i = 0; i < 16; i++) {
+		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+	}
+
+	sw[0] = dutcfg[0];
+	sw[1] = (dutcfg[1] << 0x07)		| \
+		((dutcfg[12] & 0xC0) >> 1)	| \
+		((dutcfg[11] & 0xE0) >> 3)	| \
+		((dutcfg[6] & 0x80) >> 6)	| \
+		((dutcfg[1] & 0x80) >> 7);
+	sw[2] = ((brdcfg[1] & 0x0f) << 4)	| \
+		((brdcfg[1] & 0x30) >> 2)	| \
+		((brdcfg[1] & 0x40) >> 5)	| \
+		((brdcfg[1] & 0x80) >> 7);
+	sw[3] = brdcfg[2];
+	sw[4] = ((dutcfg[2] & 0x01) << 7)	| \
+		((dutcfg[2] & 0x06) << 4)	| \
+		((~QIXIS_READ(present)) & 0x10)	| \
+		((brdcfg[3] & 0x80) >> 4)	| \
+		((brdcfg[3] & 0x01) << 2)	| \
+		((brdcfg[6] == 0x62) ? 3 :	\
+		((brdcfg[6] == 0x5a) ? 2 :	\
+		((brdcfg[6] == 0x5e) ? 1 : 0)));
+	sw[5] = ((brdcfg[0] & 0x0f) << 4)	| \
+		((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
+		((brdcfg[0] & 0x40) >> 5);
+	sw[6] = (brdcfg[11] & 0x20);
+	sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
+		((brdcfg[5] & 0x10) << 2);
+	sw[8] = ((brdcfg[12] & 0x08) << 4)	| \
+		((brdcfg[12] & 0x03) << 5);
+
+	puts("DIP switch (reverse-engineering)\n");
+	for (i = 0; i < 9; i++) {
+		printf("SW%d         = 0b%s (0x%02x)\n",
+			i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+	}
+}
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
index c6a3492..f290f3c 100644
--- a/board/freescale/t4qds/t4qds.h
+++ b/board/freescale/t4qds/t4qds.h
@@ -23,15 +23,4 @@
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
-				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
-				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
-				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
-				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
 #endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 078a6e4..80eb511 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -125,7 +125,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 16, BOOKE_PAGESZ_1M, 1),
+			0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
 	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index bc9b7d0..6221171 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -38,14 +38,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int get_fpga_state(unsigned dev)
 {
-	return gd->fpga_state[dev];
+	return gd->arch.fpga_state[dev];
 }
 
 void print_fpga_state(unsigned dev)
 {
-	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
 		puts("       Waiting for FPGA-DONE timed out.\n");
-	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
 		puts("       FPGA reflection test failed.\n");
 }
 
@@ -54,7 +54,7 @@ int board_early_init_f(void)
 	unsigned k;
 
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-		gd->fpga_state[k] = 0;
+		gd->arch.fpga_state[k] = 0;
 
 	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
@@ -78,7 +78,7 @@ int board_early_init_r(void)
 	unsigned ctr;
 
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-		gd->fpga_state[k] = 0;
+		gd->arch.fpga_state[k] = 0;
 
 	/*
 	 * reset FPGA
@@ -94,7 +94,8 @@ int board_early_init_r(void)
 		while (!gd405ep_get_fpga_done(k)) {
 			udelay(100000);
 			if (ctr++ > 5) {
-				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
 				break;
 			}
 		}
@@ -126,7 +127,7 @@ int board_early_init_r(void)
 
 			udelay(100000);
 			if (ctr++ > 5) {
-				gd->fpga_state[k] |=
+				gd->arch.fpga_state[k] |=
 					FPGA_STATE_REFLECTION_FAILED;
 				break;
 			}
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index 5766c0f..32e24c0 100644
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -15,14 +15,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int get_fpga_state(unsigned dev)
 {
-	return gd->fpga_state[dev];
+	return gd->arch.fpga_state[dev];
 }
 
 void print_fpga_state(unsigned dev)
 {
-	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
 		puts("       Waiting for FPGA-DONE timed out.\n");
-	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
 		puts("       FPGA reflection test failed.\n");
 }
 
@@ -192,7 +192,7 @@ int board_early_init_r(void)
 	unsigned ctr;
 
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-		gd->fpga_state[k] = 0;
+		gd->arch.fpga_state[k] = 0;
 
 	/*
 	 * reset FPGA
@@ -208,7 +208,8 @@ int board_early_init_r(void)
 		while (!gd405ex_get_fpga_done(k)) {
 			udelay(100000);
 			if (ctr++ > 5) {
-				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
 				break;
 			}
 		}
@@ -240,7 +241,7 @@ int board_early_init_r(void)
 
 			udelay(100000);
 			if (ctr++ > 5) {
-				gd->fpga_state[k] |=
+				gd->arch.fpga_state[k] |=
 					FPGA_STATE_REFLECTION_FAILED;
 				break;
 			}
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 41fdef7..7d2899d 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -359,7 +359,7 @@ void gd405ex_init(void)
 
 	if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
 		for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-			gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
+			gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
 	} else {
 		pca9698_direction_output(0x22, 39, 1);
 	}
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index f41bf05..09cd45d 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -88,5 +88,6 @@ void dram_init_banksize(void)
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
-	asm("	wfi");
+
+	wfi();
 }
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
deleted file mode 100644
index 8a871cf..0000000
--- a/board/incaip/u-boot.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data*) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata*) }
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		#include <u-boot.lst>
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss*) }
-	.bss (NOLOAD)  : { *(.bss*) . = ALIGN(4); }
-	uboot_end = .;
-}
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
index cf82f61..1c01bb4 100644
--- a/board/inka4x0/inkadiag.c
+++ b/board/inka4x0/inkadiag.c
@@ -187,7 +187,7 @@ static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
 	/* select clock sources */
 
 	out_be16(&psc->psc_clock_select, 0);
-	baseclk = (gd->ipb_clk + 16) / 32;
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
 
 	/* switch to UART mode */
 	out_be32(&psc->sicr, 0);
@@ -369,7 +369,7 @@ static void buzzer_turn_on(unsigned int freq)
 {
 	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
 
-	const u32 prescale = gd->ipb_clk / freq / 128;
+	const u32 prescale = gd->arch.ipb_clk / freq / 128;
 	const u32 count = 128;
 	const u32 width = 64;
 
@@ -405,9 +405,9 @@ static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
 
 	freq = simple_strtol(argv[0], NULL, 0);
 	/* avoid zero prescale in buzzer_turn_on() */
-	if (freq > gd->ipb_clk / 128) {
+	if (freq > gd->arch.ipb_clk / 128) {
 		printf("%dHz exceeds maximum (%ldHz)\n", freq,
-		       gd->ipb_clk / 128);
+		       gd->arch.ipb_clk / 128);
 	} else if (!freq)
 		printf("Zero frequency is senseless\n");
 	else
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
deleted file mode 100644
index a41e752..0000000
--- a/board/isee/igep0030/igep0030.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "igep0030.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: omap_rev_string
- * Description: For SPL builds output board rev
- */
-void omap_rev_string(void)
-{
-}
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-	timings->mr = MICRON_V_MR_165;
-#ifdef CONFIG_BOOT_NAND
-	timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-	timings->ctrla = MICRON_V_ACTIMA_200;
-	timings->ctrlb = MICRON_V_ACTIMB_200;
-	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-#else
-	if (get_cpu_family() == CPU_OMAP34XX) {
-		timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
-		timings->ctrla = NUMONYX_V_ACTIMA_165;
-		timings->ctrlb = NUMONYX_V_ACTIMB_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-
-	} else {
-		timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
-		timings->ctrla = NUMONYX_V_ACTIMA_200;
-		timings->ctrlb = NUMONYX_V_ACTIMB_200;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-	}
-#endif
-}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(0, 0, 0);
-	return 0;
-}
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	twl4030_power_init();
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_DEFAULT();
-}
diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h
deleted file mode 100644
index a93339d..0000000
--- a/board/isee/igep0030/igep0030.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _IGEP0030_H_
-#define _IGEP0030_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 IGEP module",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	"ONENAND",
-#else
-	"NAND",
-#endif
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-#define MUX_DEFAULT()\
-	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
-	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
-	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
-	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
-	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
-	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
-	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
-	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
-	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
-	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
-	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
-	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
-	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
-	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
-	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
-	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
-	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
-	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
-	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
-	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
-	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
-	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
-	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
-	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
-	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
-	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
-	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
-	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
-	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
-	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
-	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
-	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
-	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
-	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
-	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
-	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
-	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
-	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
-	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
-	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
-	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
-	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
-	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
-	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
-	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
-	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
-	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
-	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
-	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
-	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
-	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
-	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
-	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
-	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
-	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
-	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
-	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
-	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
-	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
-	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
-	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
-	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
-	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
-	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
-	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
-	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
-	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
-	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
-	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
-	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
-	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
-	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
-	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
-	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
-	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
-	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
-	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
-	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
-	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
-	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
-	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
-	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
-	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
-	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
-	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */\
-	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
-	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
-	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
-	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
-	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
-	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
-	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
-	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
-	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
-	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
-	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
-	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
-	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
-	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
-	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
-#endif
diff --git a/board/isee/igep0020/Makefile b/board/isee/igep00x0/Makefile
index 00463e1..f595954 100644
--- a/board/isee/igep0020/Makefile
+++ b/board/isee/igep00x0/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= igep0020.o
+COBJS	:= igep00x0.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep00x0/igep00x0.c
index a0f2aa3..49fcf34 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -21,29 +21,31 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <netdev.h>
 #include <twl4030.h>
-#include <asm/io.h>
+#include <netdev.h>
 #include <asm/gpio.h>
+#include <asm/arch/omap_gpmc.h>
+#include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/omap_gpmc.h>
 #include <asm/mach-types.h>
-#include "igep0020.h"
+#include "igep00x0.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_CMD_NET)
 /* GPMC definitions for LAN9221 chips */
 static const u32 gpmc_lan_config[] = {
-    NET_LAN9221_GPMC_CONFIG1,
-    NET_LAN9221_GPMC_CONFIG2,
-    NET_LAN9221_GPMC_CONFIG3,
-    NET_LAN9221_GPMC_CONFIG4,
-    NET_LAN9221_GPMC_CONFIG5,
-    NET_LAN9221_GPMC_CONFIG6,
+	NET_LAN9221_GPMC_CONFIG1,
+	NET_LAN9221_GPMC_CONFIG2,
+	NET_LAN9221_GPMC_CONFIG3,
+	NET_LAN9221_GPMC_CONFIG4,
+	NET_LAN9221_GPMC_CONFIG5,
+	NET_LAN9221_GPMC_CONFIG6,
 };
+#endif
 
 /*
  * Routine: board_init
@@ -58,6 +60,19 @@ int board_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
+void show_boot_progress(int val)
+{
+	if (val < 0) {
+		/* something went wrong */
+		return;
+	}
+
+	if (!gpio_request(IGEP00X0_GPIO_LED, ""))
+		gpio_direction_output(IGEP00X0_GPIO_LED, 1);
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 /*
  * Routine: omap_rev_string
@@ -97,12 +112,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 }
 #endif
 
+#if defined(CONFIG_CMD_NET)
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
  *		Ethernet hardware.
  */
-#if defined(CONFIG_CMD_NET)
 static void setup_net_chip(void)
 {
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
@@ -128,6 +143,8 @@ static void setup_net_chip(void)
 		gpio_set_value(64, 1);
 	}
 }
+#else
+static inline void setup_net_chip(void) {}
 #endif
 
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
@@ -146,9 +163,7 @@ int misc_init_r(void)
 {
 	twl4030_power_init();
 
-#if defined(CONFIG_CMD_NET)
 	setup_net_chip();
-#endif
 
 	dieid_num_r();
 
@@ -164,8 +179,17 @@ int misc_init_r(void)
 void set_muxconf_regs(void)
 {
 	MUX_DEFAULT();
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+	MUX_IGEP0020();
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+	MUX_IGEP0030();
+#endif
 }
 
+#if defined(CONFIG_CMD_NET)
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
@@ -174,3 +198,4 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+#endif
diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep00x0/igep00x0.h
index 3335ecc..5ef22ae 100644
--- a/board/isee/igep0020/igep0020.h
+++ b/board/isee/igep00x0/igep00x0.h
@@ -20,12 +20,28 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-#ifndef _IGEP0020_H_
-#define _IGEP0020_H_
+#ifndef _IGEP00X0_H_
+#define _IGEP00X0_H_
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+#define IGEP00X0_GPIO_LED 27
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define IGEP00X0_GPIO_LED 16
+#endif
 
 const omap3_sysinfo sysinfo = {
 	DDR_STACKED,
-	"IGEP v2 board",
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+	"IGEPv2",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+	"IGEP COM MODULE/ELECTRON",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
+	"IGEP COM PROTON",
+#endif
 #if defined(CONFIG_ENV_IS_IN_ONENAND)
 	"ONENAND",
 #else
@@ -125,7 +141,6 @@ static void setup_net_chip(void);
 	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
 	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
 	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
-	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
 	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
 	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
 	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
@@ -149,3 +164,10 @@ static void setup_net_chip(void);
 	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
 	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
 #endif
+
+#define MUX_IGEP0020() \
+	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+
+#define MUX_IGEP0030() \
+	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index 54f25e0..0d895c2 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -84,7 +84,7 @@ static void sbsc_init(struct sh73a0_sbsc *sbsc)
 	writel(0x0017040a, &sbsc->sdwcr01);
 	writel(0x31020707, &sbsc->sdwcr10);
 	writel(0x0017040a, &sbsc->sdwcr11);
-	writel(0x05555555, &sbsc->sddrvcr0);
+	writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
 	writel(0x30000000, &sbsc->sdwcr2);
 
 	writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
@@ -112,7 +112,7 @@ static void sbsc_init(struct sh73a0_sbsc *sbsc)
 		writel(0x0, SDMRA1A);
 		writel(0x00000402, &sbsc->sdmracr0);
 		writel(0x0, SDMRA1A);
-		writel(0x00000403, &sbsc->sdmracr0);
+		writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
 		writel(0x0, SDMRA1A);
 		writel(0x0, SDMRA2A);
 	} else {
@@ -120,7 +120,7 @@ static void sbsc_init(struct sh73a0_sbsc *sbsc)
 		writel(0x0, SDMRA1B);
 		writel(0x00000402, &sbsc->sdmracr0);
 		writel(0x0, SDMRA1B);
-		writel(0x00000403, &sbsc->sdmracr0);
+		writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
 		writel(0x0, SDMRA1B);
 		writel(0x0, SDMRA2B);
 	}
@@ -195,7 +195,7 @@ void s_init(void)
 
 	/* FRQCR Init */
 	writel(0x0012453C, &cpg->frqcra);
-	writel(0x80331350, &cpg->frqcrb);
+	writel(0x80431350, &cpg->frqcrb);    /* ETM TRCLK  78MHz */
 	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
 	writel(0x00000B0B, &cpg->frqcrd);
 	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
@@ -301,8 +301,19 @@ int board_early_init_f(void)
 	return 0;
 }
 
+void adjust_core_voltage(void)
+{
+	u8 data;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	data = 0x35;
+	i2c_set_bus_num(0);
+	i2c_write(0x40, 3, 1, &data, 1);
+}
+
 int board_init(void)
 {
+	adjust_core_voltage();
 	sh73a0_pinmux_init();
 
     /* SCIFA 4 */
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index b5e524b..34c6675 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -482,7 +482,7 @@ static void kbd_init (void)
 
 	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
-	gd->kbd_status = 0;
+	gd->arch.kbd_status = 0;
 
 	/* Forced by PIC. Delays <= 175us loose */
 	udelay(1000);
@@ -496,7 +496,7 @@ static void kbd_init (void)
 	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
 	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
 	if (errcd) {
-		gd->kbd_status |= errcd << 8;
+		gd->arch.kbd_status |= errcd << 8;
 	}
 	/* Reset error code and verify */
 	val = KEYBD_CMD_RESET_ERRORS;
@@ -509,7 +509,7 @@ static void kbd_init (void)
 
 	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
 	if (val) {			/* permanent error, report it */
-		gd->kbd_status |= val;
+		gd->arch.kbd_status |= val;
 		return;
 	}
 
@@ -568,8 +568,8 @@ int misc_init_r (void)
 {
 	uchar kbd_data[KEYBD_DATALEN];
 	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar kbd_init_status = gd->kbd_status >> 8;
-	uchar kbd_status = gd->kbd_status;
+	uchar kbd_init_status = gd->arch.kbd_status >> 8;
+	uchar kbd_status = gd->arch.kbd_status;
 	uchar val;
 	char *str;
 	int i;
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
index 5231c7a..b66f681 100644
--- a/board/lwmon5/kbd.c
+++ b/board/lwmon5/kbd.c
@@ -113,7 +113,7 @@ static void kbd_init (void)
 
 	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
-	gd->kbd_status = 0;
+	gd->arch.kbd_status = 0;
 
 	/* Forced by PIC. Delays <= 175us loose */
 	udelay(1000);
@@ -127,7 +127,7 @@ static void kbd_init (void)
 	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
 	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
 	if (errcd) {
-		gd->kbd_status |= errcd << 8;
+		gd->arch.kbd_status |= errcd << 8;
 	}
 	/* Reset error code and verify */
 	val = KEYBD_CMD_RESET_ERRORS;
@@ -140,7 +140,7 @@ static void kbd_init (void)
 
 	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
 	if (val) {			/* permanent error, report it */
-		gd->kbd_status |= val;
+		gd->arch.kbd_status |= val;
 		return;
 	}
 
@@ -216,8 +216,8 @@ int misc_init_r_kbd (void)
 {
 	uchar kbd_data[KEYBD_DATALEN];
 	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar kbd_init_status = gd->kbd_status >> 8;
-	uchar kbd_status = gd->kbd_status;
+	uchar kbd_init_status = gd->arch.kbd_status >> 8;
+	uchar kbd_status = gd->arch.kbd_status;
 	uchar val;
 	ushort data, inv_data;
 	char *str;
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index ecd9536..29e24fb 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -357,16 +357,16 @@ void hw_watchdog_reset(void)
 	 * Don't allow watch-dog triggering more frequently than
 	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
 	 */
-	if (ct >= gd->wdt_last) {
-		if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
+	if (ct >= gd->arch.wdt_last) {
+		if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
 			return;
 	} else {
 		/* Time base counter had been reset */
-		if (((unsigned long long)(-1) - gd->wdt_last + ct) <
+		if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
 		    CONFIG_WD_MAX_RATE)
 			return;
 	}
-	gd->wdt_last = get_ticks();
+	gd->arch.wdt_last = get_ticks();
 #endif
 
 	/*
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
index dacc138..3fcf968 100644
--- a/board/matrix_vision/mvblx/fpga.c
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -31,6 +31,7 @@
 #include <ACEX1K.h>
 #include <command.h>
 #include <asm/gpio.h>
+#include <linux/byteorder/generic.h>
 #include "fpga.h"
 
 #ifdef FPGA_DEBUG
@@ -209,9 +210,20 @@ int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
 {
 	unsigned char *data = (unsigned char *) buf;
 	int i;
+	int headerlen = len - cyclone2.size;
+
+	if (headerlen < 0)
+		return FPGA_FAIL;
+	else if (headerlen == sizeof(uint32_t)) {
+		const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
+		char fpgavers_str[fpgavers_len];
+		snprintf(fpgavers_str, fpgavers_len, "0x%08x",
+				be32_to_cpup((uint32_t*)data));
+		setenv("fpgavers", fpgavers_str);
+	}
 
 	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = 0; i < len; i++)
+	for (i = headerlen; i < len; i++)
 		_write_fpga(data[i]);
 	fpga_debug("-%s\n", __func__);
 
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
index 945a36d..15269c6 100644
--- a/board/matrix_vision/mvblx/sys_eeprom.c
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -326,10 +326,28 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+static inline int is_portrait(void)
+{
+	int i;
+	unsigned int orient_index = 0; /* idx of char which determines orientation */
+
+	for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
+		if (e.id[i] == '-') {
+			orient_index = i+1;
+			break;
+		}
+	}
+
+	return (orient_index &&
+			(e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
+}
+
 int mac_read_from_eeprom(void)
 {
 	u32 crc, crc_offset = offsetof(struct eeprom, crc);
 	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
+#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
 
 	if (read_eeprom()) {
 		printf("EEPROM Read failed.\n");
@@ -374,6 +392,12 @@ int mac_read_from_eeprom(void)
 			setenv("serial#", serial_num);
 	}
 
+	/* decide which fpga file to load depending on orientation */
+	if (is_portrait())
+		setenv("fpgafilename", FILENAME_PORTRAIT);
+	else
+		setenv("fpgafilename", FILENAME_LANDSCAPE);
+
 	/* TODO should I calculate CRC here? */
 	return 0;
 }
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
new file mode 100644
index 0000000..913f1ce
--- /dev/null
+++ b/board/nvidia/cardhu/Makefile
@@ -0,0 +1,44 @@
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/eNET/hardware.h b/board/nvidia/cardhu/cardhu.c
index dec2cd8..df4cb6b 100644
--- a/board/eNET/hardware.h
+++ b/board/nvidia/cardhu/cardhu.c
@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,16 +21,19 @@
  * MA 02111-1307 USA
  */
 
-#ifndef HARDWARE_H_
-#define HARDWARE_H_
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
 
-#define LED_LATCH_ADDRESS	0x1002
-#define LED_RUN_BITMASK		0x01
-#define LED_1_BITMASK		0x02
-#define LED_2_BITMASK		0x04
-#define LED_RX_BITMASK		0x08
-#define LED_TX_BITMASK		0x10
-#define LED_ERR_BITMASK		0x20
-#define WATCHDOG_PIO_BIT	0x8000
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra3_pinmux_common,
+		ARRAY_SIZE(tegra3_pinmux_common));
 
-#endif /* HARDWARE_H_ */
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+}
diff --git a/board/nvidia/cardhu/cardhu.c.mmc b/board/nvidia/cardhu/cardhu.c.mmc
new file mode 100644
index 0000000..9e83b6f
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.c.mmc
@@ -0,0 +1,151 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
+
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/sdmmc.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <mmc.h>
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra3_pinmux_common,
+		ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+}
+
+#if defined(CONFIG_MMC)
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+}
+
+/* Do I2C/PMU writes to bring up SD card bus power */
+static void board_sdmmc_voltage_init(void)
+{
+        uchar reg, data_buffer[1];
+        int i;
+
+        i2c_set_bus_num(0);             /* PMU is on bus 0 */
+
+        data_buffer[0] = 0x65;
+        reg = 0x32;
+
+        for (i = 0; i < MAX_I2C_RETRY; ++i) {
+                if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                        udelay(100);
+        }
+
+        data_buffer[0] = 0x09;
+        reg = 0x67;
+
+        for (i = 0; i < MAX_I2C_RETRY; ++i) {
+                if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                        udelay(100);
+        }
+}
+
+static void pad_init_mmc(struct tegra_mmc *reg)
+{
+        struct apb_misc_gp_ctlr *const gpc =
+                (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+        struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
+        u32 val, offset = (unsigned int)reg;
+        u32 padcfg, padmask;
+
+        debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
+
+        /* Set the pad drive strength for SDMMC1 or 3 only */
+        if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
+                debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+                        __func__);
+                return;
+        }
+
+        /* Set pads as per T30 TRM, section 24.6.1.2 */
+        padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
+                GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
+        padmask = 0x00000FFF;
+        if (offset == TEGRA_SDMMC1_BASE) {
+                val = readl(&gpc->sdio1cfg);
+                val &= padmask;
+                val |= padcfg;
+                writel(val, &gpc->sdio1cfg);
+        } else {                                /* SDMMC3 */
+                val = readl(&gpc->sdio3cfg);
+                val &= padmask;
+                val |= padcfg;
+                writel(val, &gpc->sdio3cfg);
+        }
+
+        val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
+        val &= 0xFFFFFFF0;
+        val |= MEMCOMP_PADCTRL_VREF;
+        writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
+
+        val = readl(&sdmmc->sdmmc_auto_cal_config);
+        val &= 0xFFFF0000;
+        val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+        writel(val, &sdmmc->sdmmc_auto_cal_config);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	debug("board_mmc_init called\n");
+
+	/* Turn on SD-card bus power */
+	board_sdmmc_voltage_init();
+
+	/* Set up the SDMMC pads as per the TRM */
+	pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
+
+	/* Enable muxes, etc. for SDMMC controllers */
+	pin_mux_mmc();
+
+	/* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
+	tegra_mmc_init(0, 8, -1, -1);
+
+	/* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
+	tegra_mmc_init(1, 8, -1, -1);
+
+	return 0;
+}
+#endif	/* MMC */
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
new file mode 100644
index 0000000..8428bba
--- /dev/null
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_CARDHU_H_
+#define _PINMUX_CONFIG_CARDHU_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+static struct pingroup_config tegra3_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+	DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+	DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+	DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* KBC keys */
+	DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+	/* SDMMC1 WP gpio */
+	LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* Touch panel GPIO */
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+
+	LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 76ec687..d1d8a29 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -26,22 +26,30 @@
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#ifdef CONFIG_LCD
 #include <asm/arch/display.h>
-#include <asm/arch/emc.h>
+#endif
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
+#ifdef CONFIG_PWM_TEGRA
 #include <asm/arch/pwm.h>
+#endif
 #include <asm/arch/tegra.h>
-#include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>
 #include <asm/arch-tegra/uart.h>
 #include <asm/arch-tegra/warmboot.h>
-#include <spi.h>
+#ifdef CONFIG_TEGRA_CLOCK_SCALING
+#include <asm/arch/emc.h>
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#include <asm/arch/usb.h>
+#endif
 #include <i2c.h>
+#include <spi.h>
 #include "emc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -87,6 +95,12 @@ void __pin_mux_nand(void)
 
 void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
 
+void __pin_mux_display(void)
+{
+}
+
+void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
+
 /*
  * Routine: power_det_init
  * Description: turn off power detects
@@ -117,15 +131,17 @@ int board_init(void)
 #ifdef CONFIG_SPI_UART_SWITCH
 	gpio_config_uart();
 #endif
-#ifdef CONFIG_TEGRA_SPI
+#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
 	pin_mux_spi();
 	spi_init();
 #endif
+
 #ifdef CONFIG_PWM_TEGRA
 	if (pwm_init(gd->fdt_blob))
 		debug("%s: Failed to init pwm\n", __func__);
 #endif
 #ifdef CONFIG_LCD
+	pin_mux_display();
 	tegra_lcd_check_next_stage(gd->fdt_blob, 0);
 #endif
 	/* boot param addr */
@@ -181,6 +197,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
 
 int board_early_init_f(void)
 {
+#if !defined(CONFIG_TEGRA20)
+	pinmux_init();
+#endif
 	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile
new file mode 100644
index 0000000..699b9f6
--- /dev/null
+++ b/board/nvidia/dalmore/Makefile
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
new file mode 100644
index 0000000..aca3c7d
--- /dev/null
+++ b/board/nvidia/dalmore/dalmore.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-dalmore.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra114_pinmux_common,
+		ARRAY_SIZE(tegra114_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+}
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
new file mode 100644
index 0000000..3dd47da
--- /dev/null
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_DALMORE_H_
+#define _PINMUX_CONFIG_DALMORE_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)   \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset  \
+	}
+
+static struct pingroup_config tegra114_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,      SDMMC1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,      SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_WP_N,     SDMMC1,	  UP,     NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL,   OUTPUT),
+
+	DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3,   UP,     NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK,  SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N,	RSVD1, DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL,	I2C3, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA,	I2C3, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL,	I2C4, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA,	I2C4, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL,	I2CPWR,	NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0,      UARTA,    NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,      UARTA,    UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2,      UARTA,    NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3,      UARTA,    NORMAL, NORMAL,   INPUT),
+
+	DEFAULT_PINMUX(ULPI_DATA4,      UARTA,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,      UARTA,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,      UARTA,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,      UARTA,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK,	UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR,	UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,	UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_STP,	UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS,	        I2S2,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,	I2S2,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT,       I2S2,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK,       I2S2,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(CLK2_OUT,	EXTPERIPH2, NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK2_REQ,	DAP,      NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART2_RXD,       UARTB,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART2_TXD,       UARTB,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,     UARTB,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(UART2_CTS_N,     UARTB,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART3_TXD,       UARTC,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,       UARTC,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N,     UARTC,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,     UARTC,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU0,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PU1,	RSVD1,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU2,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PU3,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PU4,	PWM1,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5,	PWM2,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_FS,         I2S3,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_DIN,	I2S3,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,       I2S3,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,       I2S3,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(CLK3_OUT,	EXTPERIPH3, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ,	DEV3,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_WP_N,	GMI,      NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N,       RSVD1,	  UP,     NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_AD8,	        PWM0,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GMI_AD10,	NAND,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GMI_A16,	        UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GMI_A17,	        UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_A18,	        UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_A19,	        UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(CAM_MCLK,	VI_ALT2,  UP,     NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3,       VGP3,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5,       VGP5,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6,       VGP6,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7,       I2S4,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2,       I2S4,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK,       RTCK,	  NORMAL, NORMAL,     OUTPUT),
+
+	/*  KBC keys */
+	DEFAULT_PINMUX(KB_ROW0,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW1,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW2,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW3,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW4,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW5,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW6,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW7,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW8,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW9,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW10,   KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL0,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL1,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL2,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL3,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL4,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL5,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL6,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL7,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV0,   RSVD1,  UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,   RSVD1,  UP,    NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,	  NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,	  NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(OWR,	        OWR,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_FS,	        I2S0,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_DIN,	I2S0,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,       I2S0,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,       I2S0,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK1_REQ,	DAP,      NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK1_OUT,	EXTPERIPH1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_IN,	SPDIF,    NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,	  NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS,	        I2S1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_DIN,	I2S1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,       I2S1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,       I2S1,	  NORMAL, NORMAL,   INPUT),
+
+	DEFAULT_PINMUX(SPI1_MOSI,       SPI1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_SCK,	SPI1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_CS1_N,      SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_CS2_N,      SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_MISO,       SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(HDMI_CEC,	CEC,      NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(HDMI_INT,        RSVD1,    NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY,       RSVD1,	  UP,     NORMAL,   INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14,	NAND,     NORMAL, NORMAL,   OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK,	GMI,      NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4,       VGP4,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW8,	        KBC,      UP,     NORMAL,   INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_CS0_N,       NAND,	  UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N,       NAND,	  UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS4_N,       NAND,	  UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N,       NAND,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD0,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD1,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD2,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD3,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD4,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD5,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD6,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD7,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD9,	        PWM1,     NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11,	NAND,     NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13,	NAND,     UP,	  NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N,	NAND,     NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_DALMORE_H_ */
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
new file mode 100644
index 0000000..7315577
--- /dev/null
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Dalmore";
+	compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+};
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index 5645a8d..aeda3a1 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -15,23 +15,20 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
 
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
 	i2c@7000c000 {
 		status = "disabled";
 	};
@@ -55,14 +52,4 @@
 	usb@c5004000 {
 		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
 	};
-
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
-	};
 };
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index dd98ca4..527a296 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -27,6 +27,17 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
 	/* This is not used in U-Boot, but is expected to be in kernel .dts */
 	i2c@7000d000 {
 		clock-frequency = <100000>;
@@ -45,37 +56,18 @@
 		};
 	};
 
-	clocks {
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
 
-	sdhci@c8000400 {
-		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
-	};
-
-	sdhci@c8000600 {
-		support-8bit;
-	};
-
-	usb@c5000000 {
-		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
-		dr_mode = "otg";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
 	};
 
 	i2c@7000c000 {
@@ -90,6 +82,33 @@
 		clock-frequency = <100000>;
 	};
 
+	kbc@7000e200 {
+		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
+			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
+			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
+			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
+			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
+			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
+			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
+			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
+			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
+			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
+			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
+			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
+			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
+			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
+			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
+			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
+			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
+			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
+			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
+			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
+			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
+			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
+			0x1f04008a>;
+		linux,fn-keymap = <0x05040002>;
+	};
+
 	emc@7000f400 {
 		emc-table@190000 {
 			reg = < 190000 >;
@@ -127,52 +146,23 @@
 		};
 	};
 
-	kbc@7000e200 {
-		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
-			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
-			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
-			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
-			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
-			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
-			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
-			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
-			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
-			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
-			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
-			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
-			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
-			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
-			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
-			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
-			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
-			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
-			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
-			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
-			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
-			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
-			0x1f04008a>;
-		linux,fn-keymap = <0x05040002>;
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		dr_mode = "otg";
 	};
 
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
+	usb@c5004000 {
+		status = "disabled";
 	};
 
-	host1x {
-		status = "okay";
-		dc@54200000 {
-			status = "okay";
-			rgb {
-				status = "okay";
-				nvidia,panel = <&lcd_panel>;
-			};
-		};
+	sdhci@c8000400 {
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+	};
+
+	sdhci@c8000600 {
+		support-8bit;
 	};
 
 	lcd_panel: panel {
@@ -195,5 +185,4 @@
 		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
 		nvidia,panel-timings = <400 4 203 17 15>;
 	};
-
 };
diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts
index 38b7b13..3e5e39d 100644
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ b/board/nvidia/dts/tegra20-ventana.dts
@@ -14,19 +14,6 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts
index f830cf3..4579557 100644
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ b/board/nvidia/dts/tegra20-whistler.dts
@@ -16,16 +16,6 @@
 		reg = < 0x00000000 0x20000000 >;
 	};
 
-	clocks {
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006000 {
 		clock-frequency = < 216000000 >;
 	};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
new file mode 100644
index 0000000..f9f80c5
--- /dev/null
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -0,0 +1,47 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Cardhu";
+	compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		clock-frequency = <100000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+};
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
deleted file mode 100644
index 07ddd36..0000000
--- a/board/pb1x00/u-boot.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data*) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata*) }
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		#include <u-boot.lst>
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss*) }
-	.bss (NOLOAD)  : { *(.bss*) . = ALIGN(4); }
-	uboot_end = .;
-}
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
new file mode 100644
index 0000000..67a87a1
--- /dev/null
+++ b/board/phytec/pcm051/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= board.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
new file mode 100644
index 0000000..55bc018
--- /dev/null
+++ b/board/phytec/pcm051/board.c
@@ -0,0 +1,266 @@
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define MII_MODE_ENABLE		0x0
+#define RGMII_MODE_ENABLE	0xA
+#define RMII_RGMII2_MODE_ENABLE	0x49
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
+	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
+	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41J256M8HX15E_RATIO,
+	.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J256M8HX15E_RATIO,
+	.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J256M8HX15E_RATIO,
+	.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
+	.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
+	.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
+	.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
+	.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
+	.zq_config = MT41J256M8HX15E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+	/*
+	 * WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+
+#ifdef CONFIG_SPL_BUILD
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* UART softreset */
+	u32 regval;
+
+	enable_uart0_pin_mux();
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &	UART_CLK_RUNNING_MASK)
+		!= UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	/* Initalize the board header */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	enable_board_pin_mux();
+
+	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_id		= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= AM335X_CPSW_MDIO_BASE,
+	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+#ifdef CONFIG_DRIVER_TI_CPSW
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			goto try_usbether;
+	}
+
+	writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+try_usbether:
+#endif
+
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h
new file mode 100644
index 0000000..c2630d7
--- /dev/null
+++ b/board/phytec/pcm051/board.h
@@ -0,0 +1,33 @@
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013, Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c
new file mode 100644
index 0000000..6e9c3d2
--- /dev/null
+++ b/board/phytec/pcm051/mux.c
@@ -0,0 +1,127 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+#ifdef CONFIG_I2C
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+#endif
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
+	{-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+	configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/board/qemu-mips/README b/board/qemu-mips/README
deleted file mode 100644
index 9fd97e1..0000000
--- a/board/qemu-mips/README
+++ /dev/null
@@ -1,182 +0,0 @@
-By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01
-----------------------------------------
-Qemu is a full system emulator. See
-
-http://www.nongnu.org/qemu/
-
-Limitations & comments
-----------------------
-Supports the "-m mips" configuration of qemu: serial,NE2000,IDE.
-Support is big endian only for now (or at least this is what I tested).
-Derived from au1x00 with a lot of things cut out.
-
-Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
-recent qemu versions. When using emulated flash, launch with
--pflash <filename> and erase mips_bios.bin.
-
-
-
-Notes for the Qemu MIPS port
-----------------------------
-
-I) Example usage:
-
-# ln -s u-boot.bin mips_bios.bin
-start it:
-qemu-system-mips -L . /dev/null -nographic
-
-or
-
-if you use a qemu version after commit 4224
-
-create image:
-# dd of=flash bs=1k count=4k if=/dev/zero
-# dd of=flash bs=1k conv=notrunc if=u-boot.bin
-start it:
-# qemu-system-mips -M mips -pflash flash -monitor null -nographic
-
-2) Download kernel + initrd
-
-On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
-you can downland
-
-#config to build the kernel
-qemu_mips_defconfig
-#patch to fix mips interrupt init on 2.6.24.y kernel
-qemu_mips_kernel.patch
-initrd.gz
-vmlinux
-vmlinux.bin
-System.map
-
-4) Generate uImage
-
-# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
-
-5) Copy uImage to Flash
-# dd if=uImage bs=1k conv=notrunc seek=224 of=flash
-
-6) Generate Ide Disk
-
-# dd of=ide bs=1k cout=100k if=/dev/zero
-
-# sfdisk -C 261 -d ide
-# partition table of ide
-unit: sectors
-
-     ide1 : start=       63, size=    32067, Id=83
-     ide2 : start=    32130, size=    32130, Id=83
-     ide3 : start=    64260, size=  4128705, Id=83
-     ide4 : start=        0, size=        0, Id= 0
-
-7) Copy to ide
-
-# dd if=uImage bs=512 conv=notrunc seek=63 of=ide
-
-8) Generate ext2 on part 2 on Copy uImage and initrd.gz
-
-# Attached as loop device ide offset = 32130 * 512
-# losetup -o 16450560 -f ide
-# Format as ext2 ( arg2 : nb blocks)
-# mke2fs /dev/loop0 16065
-# losetup -d /dev/loop0
-# Mount and copy uImage and initrd.gz to it
-# mount -o loop,offset=16450560 -t ext2 ide /mnt
-# mkdir /mnt/boot
-# cp {initrd.gz,uImage} /mnt/boot/
-# Umount it
-# umount /mnt
-
-9) Set Environment
-
-setenv rd_start 0x80800000
-setenv rd_size 2663940
-setenv kernel BFC38000
-setenv oad_addr 80500000
-setenv load_addr2 80F00000
-setenv kernel_flash BFC38000
-setenv load_addr_hello 80200000
-setenv bootargs 'root=/dev/ram0 init=/bin/sh'
-setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
-setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
-setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
-setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
-setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
-setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
-setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
-setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
-setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
-setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
-setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
-setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
-setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
-setenv bootcmd 'run boot_tftp_flash'
-
-10) Now you can boot from flash, ide, ide+ext2 and tfp
-
-# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-II) How to debug U-Boot
-
-In order to debug U-Boot you need to start qemu with gdb server support (-s)
-and waiting the connection to start the CPU (-S)
-
-# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-in an other console you start gdb
-
-1) Debugging of U-Boot Before Relocation
-
-Before relocation, the addresses in the ELF file can be used without any problems
-by connecting to the gdb server localhost:1234
-
-# mipsel-unknown-linux-gnu-gdb u-boot
-GNU gdb 6.6
-Copyright (C) 2006 Free Software Foundation, Inc.
-GDB is free software, covered by the GNU General Public License, and you are
-welcome to change it and/or distribute copies of it under certain conditions.
-Type "show copying" to see the conditions.
-There is absolutely no warranty for GDB.  Type "show warranty" for details.
-This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
-(gdb)  target remote localhost:1234
-Remote debugging using localhost:1234
-_start () at start.S:64
-64		RVECENT(reset,0)	/* U-boot entry point */
-Current language:  auto; currently asm
-(gdb)  b board.c:289
-Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
-(gdb) c
-Continuing.
-
-Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
-290		relocate_code (addr_sp, id, addr);
-Current language:  auto; currently c
-(gdb) p/x addr
-$1 = 0x87fa0000
-
-2) Debugging of U-Boot After Relocation
-
-For debugging U-Boot after relocation we need to know the address to which
-U-Boot relocates itself to 0x87fa0000 by default.
-And replace the symbol table to this offset.
-
-(gdb) symbol-file
-Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
-Error in re-setting breakpoint 1:
-No symbol table is loaded.  Use the "file" command.
-No symbol file now.
-(gdb) add-symbol-file u-boot 0x87fa0000
-add symbol table from file "u-boot" at
-	.text_addr = 0x87fa0000
-(y or n) y
-Reading symbols from /private/u-boot-arm/u-boot...done.
-Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
-(gdb) c
-Continuing.
-
-Program received signal SIGINT, Interrupt.
-0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
-78		while ((tmo - read_c0_count()) < 0x7fffffff)
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
deleted file mode 100644
index cb2356f..0000000
--- a/board/qemu-mips/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-#if defined(CONFIG_64BIT)
-OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
-#else
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-#endif
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data*) }
-
-	. = .;
-	_gp = ALIGN(16) +0x7ff0;
-
-	.got  : {
-	__got_start = .;
-		*(.got)
-	__got_end = .;
-	}
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata*) }
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		#include <u-boot.lst>
-	}
-
-	uboot_end_data = .;
-#if defined(CONFIG_64BIT)
-	num_got_entries = (__got_end - __got_start) >> 3;
-#else
-	num_got_entries = (__got_end - __got_start) >> 2;
-#endif
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss*) }
-	.bss  : { *(.bss*) . = ALIGN(4); }
-	uboot_end = .;
-}
diff --git a/board/sc3/init.S b/board/sc3/init.S
index d374db4..6352368 100644
--- a/board/sc3/init.S
+++ b/board/sc3/init.S
@@ -71,7 +71,8 @@ ext_bus_cntlr_init:
  * This is need for the external flash access
  */
 		lis r25,0x0800
-		ori r25,r25,0x0280			/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
+		/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
+		ori r25,r25,0x0280
 /*
  * Second, create a fast timing:
  * 90ns first cycle - 3 clock access
@@ -79,7 +80,8 @@ ext_bus_cntlr_init:
  * This is used for the internal access
  */
 		lis r26,0x8900
-		ori r26,r26,0x0280			/* 1000 1001 0xxx 0000 0000 0010 100x xxxx
+		/* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
+		ori r26,r26,0x0280
 /*
  * We can't change settings on CS# if we currently use them.
  * -> load a few instructions into cache and run this code from cache
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ed4229e..441758f 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -73,6 +73,17 @@ static inline int board_is_idk(void)
 	return !strncmp(header.config, "SKU#02", 6);
 }
 
+static int board_is_gp_evm(void)
+{
+	return !strncmp("A33515BB", header.name, 8);
+}
+
+int board_is_evm_15_or_later(void)
+{
+	return (!strncmp("A33515BB", header.name, 8) &&
+		strncmp("1.5", header.version, 3) <= 0);
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -197,6 +208,14 @@ static const struct ddr_data ddr3_data = {
 	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
+static const struct ddr_data ddr3_evm_data = {
+	.datardsratio0 = MT41J512M8RH125_RD_DQS,
+	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
+	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
@@ -211,6 +230,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 
+static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
+	.cmd0csratio = MT41J512M8RH125_RATIO,
+	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J512M8RH125_RATIO,
+	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J512M8RH125_RATIO,
+	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+};
+
 static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -220,6 +253,16 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
 };
+
+static struct emif_regs ddr3_evm_emif_reg_data = {
+	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
+	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
+	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
+	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+	.zq_config = MT41J512M8RH125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+};
 #endif
 
 /*
@@ -301,6 +344,9 @@ void s_init(void)
 	if (board_is_evm_sk() || board_is_bone_lt())
 		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+	else if (board_is_evm_15_or_later())
+		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
@@ -343,7 +389,8 @@ int board_late_init(void)
 }
 #endif
 
-#ifdef CONFIG_DRIVER_TI_CPSW
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
 {
 	/* VTP can be added here */
@@ -388,26 +435,26 @@ static struct cpsw_platform_data cpsw_data = {
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
-#ifdef CONFIG_DRIVER_TI_CPSW
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
 
-	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		debug("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 
 		if (is_valid_ether_addr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
-		else
-			goto try_usbether;
 	}
 
 	if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
@@ -425,9 +472,34 @@ int board_eth_init(bd_t *bis)
 		printf("Error %d registering CPSW switch\n", rv);
 	else
 		n += rv;
+
+	/*
+	 *
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device in U-Boot, we only do this for the first instance.
+	 */
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+
+	if (board_is_evm_sk() || board_is_gp_evm()) {
+		const char *devname;
+		devname = miiphy_get_current_dev();
+
+		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+				AR8051_DEBUG_RGMII_CLK_DLY_REG);
+		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+				AR8051_RGMII_TX_CLK_DLY);
+	}
 #endif
-try_usbether:
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ether_addr(mac_addr))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
 	rv = usb_eth_initialize(bis);
 	if (rv < 0)
 		printf("Error %d registering USB_ETHER\n", rv);
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index b829a79..58bd556 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -72,6 +72,7 @@
 #define BBTOYS_LCD			0x03000B00
 #define BCT_BRETTL3			0x01000F00
 #define BCT_BRETTL4			0x02000F00
+#define LSR_COM6L_ADPT			0x01001300
 #define BEAGLE_NO_EEPROM		0xffffffff
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -227,6 +228,14 @@ static unsigned int get_expansion_id(void)
 	i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
 		 sizeof(expansion_config));
 
+	/* retry reading configuration data with 16bit addressing */
+	if ((expansion_config.device_vendor == 0xFFFFFF00) ||
+	    (expansion_config.device_vendor == 0xFFFFFFFF)) {
+		printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
+		i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
+			 sizeof(expansion_config));
+	}
+
 	i2c_set_bus_num(TWL4030_I2C_BUS);
 
 	return expansion_config.device_vendor;
@@ -454,6 +463,11 @@ int misc_init_r(void)
 	case BCT_BRETTL4:
 		printf("Recognized bct electronic GmbH brettl4 board\n");
 		break;
+	case LSR_COM6L_ADPT:
+		printf("Recognized LSR COM6L Adapter Board\n");
+		MUX_BBTOYS_WIFI()
+		setenv("buddy", "lsr-com6l-adpt");
+		break;
 	case BEAGLE_NO_EEPROM:
 		printf("No EEPROM on expansion board\n");
 		setenv("buddy", "none");
diff --git a/board/xilinx/common/xbasic_types.c b/board/xilinx/common/xbasic_types.c
deleted file mode 100644
index c3a171a..0000000
--- a/board/xilinx/common/xbasic_types.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-     *
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.c
-*
-* This file contains basic functions for Xilinx software IP.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-unsigned int XAssertStatus;
-
-/**
- * This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-u32 XWaitInAssert = TRUE;
-
-/* The callback function to be invoked when an assert is taken */
-static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Implements assert. Currently, it calls a user-defined callback function
-* if one has been set.  Then, it potentially enters an infinite loop depending
-* on the value of the XWaitInAssert variable.
-*
-* @param    File is the name of the filename of the source
-* @param    Line is the linenumber within File
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XAssert(char *File, int Line)
-{
-	/* if the callback has been set then invoke it */
-	if (XAssertCallbackRoutine != NULL) {
-		(*XAssertCallbackRoutine) (File, Line);
-	}
-
-	/* if specified, wait indefinitely such that the assert will show up
-	 * in testing
-	 */
-	while (XWaitInAssert) {
-	}
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets up a callback function to be invoked when an assert occurs. If there
-* was already a callback installed, then it is replaced.
-*
-* @param    Routine is the callback to be invoked when an assert is taken
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void
-XAssertSetCallback(XAssertCallback Routine)
-{
-	XAssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* Null handler function. This follows the XInterruptHandler signature for
-* interrupt handlers. It can be used to assign a null handler (a stub) to an
-* interrupt controller vector table.
-*
-* @param    NullParameter is an arbitrary void pointer and not used.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XNullHandler(void *NullParameter)
-{
-}
diff --git a/board/xilinx/common/xbasic_types.h b/board/xilinx/common/xbasic_types.h
deleted file mode 100644
index ef0b7c2..0000000
--- a/board/xilinx/common/xbasic_types.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-* This file contains basic types for Xilinx software IP.  These types do not
-* follow the standard naming convention with respect to using the component
-* name in front of each name because they are considered to be primitives.
-*
-* @note
-*
-* This file contains items which are architecture dependent.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver	Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rmm  12/14/01 First release
-*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
-*		      compiler warnings
-* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H		/* prevent circular inclusions */
-#define XBASIC_TYPES_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-/** Null */
-
-#define XCOMPONENT_IS_READY	0x11111111	/* component has been initialized */
-#define XCOMPONENT_IS_STARTED	0x22222222	/* component has been started */
-
-/* the following constants and declarations are for unit test purposes and are
- * designed to be used in test applications.
- */
-#define XTEST_PASSED	0
-#define XTEST_FAILED	1
-
-#define XASSERT_NONE	 0
-#define XASSERT_OCCURRED 1
-
-extern unsigned int XAssertStatus;
-extern void XAssert(char *, int);
-
-/**************************** Type Definitions *******************************/
-
-/** @name Primitive types
- * These primitive types are created for transportability.
- * They are dependent upon the target architecture.
- * @{
- */
-#include <linux/types.h>
-
-typedef struct {
-	u32 Upper;
-	u32 Lower;
-} Xuint64;
-
-/*@}*/
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The upper 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The lower 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the XWaitInAssert boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-*	 the assert occurs.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID(expression)			\
-{							\
-	if (expression) {				\
-		XAssertStatus = XASSERT_NONE;		\
-	} else {					\
-		XAssert(__FILE__, __LINE__);		\
-		XAssertStatus = XASSERT_OCCURRED;	\
-		return;					\
-	}						\
-}
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
-* that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-*	 the assert occurs.
-*
-* @return
-*
-* Returns 0 unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID(expression)		   \
-{						   \
-	if (expression) {			   \
-		XAssertStatus = XASSERT_NONE;	   \
-	} else {				   \
-		XAssert(__FILE__, __LINE__);	   \
-		XAssertStatus = XASSERT_OCCURRED;  \
-		return 0;			   \
-	}					   \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID_ALWAYS()			   \
-{						   \
-	XAssert(__FILE__, __LINE__);		   \
-	XAssertStatus = XASSERT_OCCURRED;	   \
-	return;					   \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID_ALWAYS()		   \
-{						   \
-	XAssert(__FILE__, __LINE__);		   \
-	XAssertStatus = XASSERT_OCCURRED;	   \
-	return 0;				   \
-}
-
-#else
-
-#define XASSERT_VOID(expression)
-#define XASSERT_VOID_ALWAYS()
-#define XASSERT_NONVOID(expression)
-#define XASSERT_NONVOID_ALWAYS()
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void XAssertSetCallback(XAssertCallback Routine);
-void XNullHandler(void *NullParameter);
-
-#endif	/* end of protection macro */
diff --git a/board/xilinx/common/xbuf_descriptor.h b/board/xilinx/common/xbuf_descriptor.h
deleted file mode 100644
index fdd51d5..0000000
--- a/board/xilinx/common/xbuf_descriptor.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xbuf_descriptor.h
-*
-* DESCRIPTION:
-*
-* This file contains the interface for the XBufDescriptor component.
-* The XBufDescriptor component is a passive component that only maps over
-* a buffer descriptor data structure shared by the scatter gather DMA hardware
-* and software. The component's primary purpose is to provide encapsulation of
-* the buffer descriptor processing.  See the source file xbuf_descriptor.c for
-* details.
-*
-* NOTES:
-*
-* Most of the functions of this component are implemented as macros in order
-* to optimize the processing.  The names are not all uppercase such that they
-* can be switched between macros and functions easily.
-*
-******************************************************************************/
-
-#ifndef XBUF_DESCRIPTOR_H	/* prevent circular inclusions */
-#define XBUF_DESCRIPTOR_H	/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xdma_channel_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/* The following constants allow access to all fields of a buffer descriptor
- * and are necessary at this level of visibility to allow macros to access
- * and modify the fields of a buffer descriptor.  It is not expected that the
- * user of a buffer descriptor would need to use these constants.
- */
-
-#define XBD_DEVICE_STATUS_OFFSET    0
-#define XBD_CONTROL_OFFSET	    1
-#define XBD_SOURCE_OFFSET	    2
-#define XBD_DESTINATION_OFFSET	    3
-#define XBD_LENGTH_OFFSET	    4
-#define XBD_STATUS_OFFSET	    5
-#define XBD_NEXT_PTR_OFFSET	    6
-#define XBD_ID_OFFSET		    7
-#define XBD_FLAGS_OFFSET	    8
-#define XBD_RQSTED_LENGTH_OFFSET    9
-
-#define XBD_SIZE_IN_WORDS	    10
-
-/*
- * The following constants define the bits of the flags field of a buffer
- * descriptor
- */
-
-#define XBD_FLAGS_LOCKED_MASK	    1UL
-
-/**************************** Type Definitions *******************************/
-
-typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/* each of the following macros are named the same as functions rather than all
- * upper case in order to allow either the macros or the functions to be
- * used, see the source file xbuf_descriptor.c for documentation
- */
-
-#define XBufDescriptor_Initialize(InstancePtr)			\
-{								\
-    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0);   \
-    (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \
-    (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0);	    \
-    (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \
-}
-
-#define XBufDescriptor_GetControl(InstancePtr)	 \
-    (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET))
-
-#define XBufDescriptor_SetControl(InstancePtr, Control)	 \
-    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control)
-
-#define XBufDescriptor_IsLastControl(InstancePtr) \
-    (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \
-	       XDC_CONTROL_LAST_BD_MASK)
-
-#define XBufDescriptor_SetLast(InstancePtr) \
-    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK)
-
-#define XBufDescriptor_GetSrcAddress(InstancePtr) \
-    ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET)))
-
-#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \
-    (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source)
-
-#define XBufDescriptor_GetDestAddress(InstancePtr) \
-    ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET)))
-
-#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \
-    (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination)
-
-#define XBufDescriptor_GetLength(InstancePtr)				\
-    (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) -	\
-	      *((u32 *)InstancePtr + XBD_LENGTH_OFFSET))
-
-#define XBufDescriptor_SetLength(InstancePtr, Length)			    \
-{									    \
-    (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length));    \
-    (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
-}
-
-#define XBufDescriptor_GetStatus(InstancePtr)	 \
-    (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET))
-
-#define XBufDescriptor_SetStatus(InstancePtr, Status)	 \
-    (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status)
-
-#define XBufDescriptor_IsLastStatus(InstancePtr) \
-    (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \
-	       XDC_STATUS_LAST_BD_MASK)
-
-#define XBufDescriptor_GetDeviceStatus(InstancePtr) \
-    ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET)))
-
-#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \
-    (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status)
-
-#define XBufDescriptor_GetNextPtr(InstancePtr) \
-    (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET))
-
-#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \
-    (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr)
-
-#define XBufDescriptor_GetId(InstancePtr) \
-    (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET))
-
-#define XBufDescriptor_SetId(InstancePtr, Id) \
-    (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id)
-
-#define XBufDescriptor_GetFlags(InstancePtr) \
-    (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET))
-
-#define XBufDescriptor_SetFlags(InstancePtr, Flags) \
-    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags)
-
-#define XBufDescriptor_Lock(InstancePtr) \
-    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK)
-
-#define XBufDescriptor_Unlock(InstancePtr) \
-    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK)
-
-#define XBufDescriptor_IsLocked(InstancePtr) \
-    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/* The following prototypes are provided to allow each of the functions to
- * be implemented as a function rather than a macro, and to provide the
- * syntax to allow users to understand how to call the macros, they are
- * commented out to prevent linker errors
- *
-
-u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control);
-
-u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length);
-
-u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status);
-u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr,
-				    u32 Status);
-
-u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr,
-				  u32 SourceAddress);
-
-u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr,
-				   u32 DestinationAddress);
-
-XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr,
-			       XBufDescriptor* NextPtr);
-
-u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id);
-
-u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags);
-
-void XBufDescriptor_Lock(XBufDescriptor* InstancePtr);
-void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr);
-u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr);
-
-void XBufDescriptor_Copy(XBufDescriptor* InstancePtr,
-			 XBufDescriptor* DestinationPtr);
-
-*/
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c
deleted file mode 100644
index f816138..0000000
--- a/board/xilinx/common/xdma_channel.c
+++ /dev/null
@@ -1,738 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel.c
-*
-* DESCRIPTION:
-*
-* This file contains the DMA channel component. This component supports
-* a distributed DMA design in which each device can have it's own dedicated
-* DMA channel, as opposed to a centralized DMA design. This component
-* performs processing for DMA on all devices.
-*
-* See xdma_channel.h for more information about this component.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel.h"
-#include "xbasic_types.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Initialize
-*
-* DESCRIPTION:
-*
-* This function initializes a DMA channel.  This function must be called
-* prior to using a DMA channel.  Initialization of a channel includes setting
-* up the registers base address, and resetting the channel such that it's in a
-* known state.  Interrupts for the channel are disabled when the channel is
-* reset.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* BaseAddress contains the base address of the registers for the DMA channel.
-*
-* RETURN VALUE:
-*
-* XST_SUCCESS indicating initialization was successful.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
-{
-	/* assert to verify input arguments, don't assert base address */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-
-	/* setup the base address of the registers for the DMA channel such
-	 * that register accesses can be done
-	 */
-	InstancePtr->RegBaseAddress = BaseAddress;
-
-	/* initialize the scatter gather list such that it indicates it has not
-	 * been created yet and the DMA channel is ready to use (initialized)
-	 */
-	InstancePtr->GetPtr = NULL;
-	InstancePtr->PutPtr = NULL;
-	InstancePtr->CommitPtr = NULL;
-	InstancePtr->LastPtr = NULL;
-
-	InstancePtr->TotalDescriptorCount = 0;
-	InstancePtr->ActiveDescriptorCount = 0;
-	InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
-	/* initialize the version of the component
-	 */
-	XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
-
-	/* reset the DMA channel such that it's in a known state and ready
-	 * and indicate the initialization occured with no errors, note that
-	 * the is ready variable must be set before this call or reset will assert
-	 */
-	XDmaChannel_Reset(InstancePtr);
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_IsReady
-*
-* DESCRIPTION:
-*
-* This function determines if a DMA channel component has been successfully
-* initialized such that it's ready to use.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* TRUE if the DMA channel component is ready, FALSE otherwise.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_IsReady(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments used by the base component */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-
-	return InstancePtr->IsReady == XCOMPONENT_IS_READY;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetVersion
-*
-* DESCRIPTION:
-*
-* This function gets the software version for the specified DMA channel
-* component.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* A pointer to the software version of the specified DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XVersion *
-XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* return a pointer to the version of the DMA channel */
-
-	return &InstancePtr->Version;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SelfTest
-*
-* DESCRIPTION:
-*
-* This function performs a self test on the specified DMA channel.  This self
-* test is destructive as the DMA channel is reset and a register default is
-* verified.
-*
-* ARGUMENTS:
-*
-* InstancePtr is a pointer to the DMA channel to be operated on.
-*
-* RETURN VALUE:
-*
-* XST_SUCCESS is returned if the self test is successful, or one of the
-* following errors.
-*
-*	XST_DMA_RESET_REGISTER_ERROR		Indicates the control register value
-*										after a reset was not correct
-*
-* NOTES:
-*
-* This test does not performs a DMA transfer to test the channel because the
-* DMA hardware will not currently allow a non-local memory transfer to non-local
-* memory (memory copy), but only allows a non-local memory to or from the device
-* memory (typically a FIFO).
-*
-******************************************************************************/
-
-#define XDC_CONTROL_REG_RESET_MASK  0x98000000UL	/* control reg reset value */
-
-XStatus
-XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
-{
-	u32 ControlReg;
-
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* reset the DMA channel such that it's in a known state before the test
-	 * it resets to no interrupts enabled, the desired state for the test
-	 */
-	XDmaChannel_Reset(InstancePtr);
-
-	/* this should be the first test to help prevent a lock up with the polling
-	 * loop that occurs later in the test, check the reset value of the DMA
-	 * control register to make sure it's correct, return with an error if not
-	 */
-	ControlReg = XDmaChannel_GetControl(InstancePtr);
-	if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
-		return XST_DMA_RESET_REGISTER_ERROR;
-	}
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Reset
-*
-* DESCRIPTION:
-*
-* This function resets the DMA channel. This is a destructive operation such
-* that it should not be done while a channel is being used.  If the DMA channel
-* is transferring data into other blocks, such as a FIFO, it may be necessary
-* to reset other blocks.  This function does not modify the contents of a
-* scatter gather list for a DMA channel such that the user is responsible for
-* getting buffer descriptors from the list if necessary.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_Reset(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* reset the DMA channel such that it's in a known state, the reset
-	 * register is self clearing such that it only has to be set
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
-		  XDC_RESET_MASK);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetControl
-*
-* DESCRIPTION:
-*
-* This function gets the control register contents of the DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The control register contents of the DMA channel. One or more of the
-* following values may be contained the register.  Each of the values are
-* unique bit masks.
-*
-*	XDC_DMACR_SOURCE_INCR_MASK	Increment the source address
-*	XDC_DMACR_DEST_INCR_MASK	Increment the destination address
-*	XDC_DMACR_SOURCE_LOCAL_MASK Local source address
-*	XDC_DMACR_DEST_LOCAL_MASK	Local destination address
-*	XDC_DMACR_SG_ENABLE_MASK	Scatter gather enable
-*	XDC_DMACR_GEN_BD_INTR_MASK	Individual buffer descriptor interrupt
-*	XDC_DMACR_LAST_BD_MASK		Last buffer descriptor in a packet
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetControl(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* return the contents of the DMA control register */
-
-	return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetControl
-*
-* DESCRIPTION:
-*
-* This function sets the control register of the specified DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Control contains the value to be written to the control register of the DMA
-* channel. One or more of the following values may be contained the register.
-* Each of the values are unique bit masks such that they may be ORed together
-* to enable multiple bits or inverted and ANDed to disable multiple bits.
-*
-*	XDC_DMACR_SOURCE_INCR_MASK	Increment the source address
-*	XDC_DMACR_DEST_INCR_MASK	Increment the destination address
-*	XDC_DMACR_SOURCE_LOCAL_MASK Local source address
-*	XDC_DMACR_DEST_LOCAL_MASK	Local destination address
-*	XDC_DMACR_SG_ENABLE_MASK	Scatter gather enable
-*	XDC_DMACR_GEN_BD_INTR_MASK	Individual buffer descriptor interrupt
-*	XDC_DMACR_LAST_BD_MASK		Last buffer descriptor in a packet
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
-{
-	/* assert to verify input arguments except the control which can't be
-	 * asserted since all values are valid
-	 */
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* set the DMA control register to the specified value */
-
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetStatus
-*
-* DESCRIPTION:
-*
-* This function gets the status register contents of the DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The status register contents of the DMA channel. One or more of the
-* following values may be contained the register. Each of the values are
-* unique bit masks.
-*
-*	XDC_DMASR_BUSY_MASK			The DMA channel is busy
-*	XDC_DMASR_BUS_ERROR_MASK	A bus error occurred
-*	XDC_DMASR_BUS_TIMEOUT_MASK	A bus timeout occurred
-*	XDC_DMASR_LAST_BD_MASK		The last buffer descriptor of a packet
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* return the contents of the DMA status register */
-
-	return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetIntrStatus
-*
-* DESCRIPTION:
-*
-* This function sets the interrupt status register of the specified DMA channel.
-* Setting any bit of the interrupt status register will clear the bit to
-* indicate the interrupt processing has been completed. The definitions of each
-* bit in the register match the definition of the bits in the interrupt enable
-* register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Status contains the value to be written to the status register of the DMA
-* channel.  One or more of the following values may be contained the register.
-* Each of the values are unique bit masks such that they may be ORed together
-* to enable multiple bits or inverted and ANDed to disable multiple bits.
-*
-*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
-*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
-*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
-*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-*	XDC_IXR_BD_MASK				A buffer descriptor is done
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
-{
-	/* assert to verify input arguments except the status which can't be
-	 * asserted since all values are valid
-	 */
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* set the interrupt status register with the specified value such that
-	 * all bits which are set in the register are cleared effectively clearing
-	 * any active interrupts
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetIntrStatus
-*
-* DESCRIPTION:
-*
-* This function gets the interrupt status register of the specified DMA channel.
-* The interrupt status register indicates which interrupts are active
-* for the DMA channel.  If an interrupt is active, the status register must be
-* set (written) with the bit set for each interrupt which has been processed
-* in order to clear the interrupts.  The definitions of each bit in the register
-* match the definition of the bits in the interrupt enable register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The interrupt status register contents of the specified DMA channel.
-* One or more of the following values may be contained the register.
-* Each of the values are unique bit masks.
-*
-*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
-*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
-*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
-*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-*	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
-*	XDC_IXR_BD_MASK				A buffer descriptor is done
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* return the contents of the interrupt status register */
-
-	return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetIntrEnable
-*
-* DESCRIPTION:
-*
-* This function sets the interrupt enable register of the specified DMA
-* channel.  The interrupt enable register contains bits which enable
-* individual interrupts for the DMA channel.  The definitions of each bit
-* in the register match the definition of the bits in the interrupt status
-* register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Enable contains the interrupt enable register contents to be written
-* in the DMA channel. One or more of the following values may be contained
-* the register. Each of the values are unique bit masks such that they may be
-* ORed together to enable multiple bits or inverted and ANDed to disable
-* multiple bits.
-*
-*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
-*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
-*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
-*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-*	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
-*	XDC_IXR_BD_MASK				A buffer descriptor is done
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
-{
-	/* assert to verify input arguments except the enable which can't be
-	 * asserted since all values are valid
-	 */
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* set the interrupt enable register to the specified value */
-
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetIntrEnable
-*
-* DESCRIPTION:
-*
-* This function gets the interrupt enable of the DMA channel.  The
-* interrupt enable contains flags which enable individual interrupts for the
-* DMA channel. The definitions of each bit in the register match the definition
-* of the bits in the interrupt status register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The interrupt enable of the DMA channel.  One or more of the following values
-* may be contained the register. Each of the values are unique bit masks.
-*
-*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
-*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
-*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
-*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-*	XDC_IXR_BD_MASK				A buffer descriptor is done
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* return the contents of the interrupt enable register */
-
-	return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Transfer
-*
-* DESCRIPTION:
-*
-* This function starts the DMA channel transferring data from a memory source
-* to a memory destination. This function only starts the operation and returns
-* before the operation may be complete.  If the interrupt is enabled, an
-* interrupt will be generated when the operation is complete, otherwise it is
-* necessary to poll the channel status to determine when it's complete.  It is
-* the responsibility of the caller to determine when the operation is complete
-* by handling the generated interrupt or polling the status.  It is also the
-* responsibility of the caller to ensure that the DMA channel is not busy with
-* another transfer before calling this function.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* SourcePtr contains a pointer to the source memory where the data is to
-* be tranferred from and must be 32 bit aligned.
-*
-* DestinationPtr contains a pointer to the destination memory where the data
-* is to be transferred and must be 32 bit aligned.
-*
-* ByteCount contains the number of bytes to transfer during the DMA operation.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* The DMA h/w will not currently allow a non-local memory transfer to non-local
-* memory (memory copy), but only allows a non-local memory to or from the device
-* memory (typically a FIFO).
-*
-* It is the responsibility of the caller to ensure that the cache is
-* flushed and invalidated both before and after the DMA operation completes
-* if the memory pointed to is cached. The caller must also ensure that the
-* pointers contain a physical address rather than a virtual address
-* if address translation is being used.
-*
-******************************************************************************/
-void
-XDmaChannel_Transfer(XDmaChannel * InstancePtr,
-		     u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
-{
-	/* assert to verify input arguments and the alignment of any arguments
-	 * which have expected alignments
-	 */
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(SourcePtr != NULL);
-	XASSERT_VOID(((u32) SourcePtr & 3) == 0);
-	XASSERT_VOID(DestinationPtr != NULL);
-	XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
-	XASSERT_VOID(ByteCount != 0);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* setup the source and destination address registers for the transfer */
-
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
-		  (u32) SourcePtr);
-
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
-		  (u32) DestinationPtr);
-
-	/* start the DMA transfer to copy from the source buffer to the
-	 * destination buffer by writing the length to the length register
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
-}
diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h
deleted file mode 100644
index 4685982..0000000
--- a/board/xilinx/common/xdma_channel.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel.h
-*
-* DESCRIPTION:
-*
-* This file contains the DMA channel component implementation. This component
-* supports a distributed DMA design in which each device can have it's own
-* dedicated DMA channel, as opposed to a centralized DMA design.
-* A device which uses DMA typically contains two DMA channels, one for
-* sending data and the other for receiving data.
-*
-* This component is designed to be used as a basic building block for
-* designing a device driver. It provides registers accesses such that all
-* DMA processing can be maintained easier, but the device driver designer
-* must still understand all the details of the DMA channel.
-*
-* The DMA channel allows a CPU to minimize the CPU interaction required to move
-* data between a memory and a device.  The CPU requests the DMA channel to
-* perform a DMA operation and typically continues performing other processing
-* until the DMA operation completes.  DMA could be considered a primitive form
-* of multiprocessing such that caching and address translation can be an issue.
-*
-* Scatter Gather Operations
-*
-* The DMA channel may support scatter gather operations. A scatter gather
-* operation automates the DMA channel such that multiple buffers can be
-* sent or received with minimal software interaction with the hardware.  Buffer
-* descriptors, contained in the XBufDescriptor component, are used by the
-* scatter gather operations of the DMA channel to describe the buffers to be
-* processed.
-*
-* Scatter Gather List Operations
-*
-* A scatter gather list may be supported by each DMA channel.  The scatter
-* gather list allows buffer descriptors to be put into the list by a device
-* driver which requires scatter gather.  The hardware processes the buffer
-* descriptors which are contained in the list and modifies the buffer
-* descriptors to reflect the status of the DMA operations.  The device driver
-* is notified by interrupt that specific DMA events occur including scatter
-* gather events.  The device driver removes the completed buffer descriptors
-* from the scatter gather list to evaluate the status of each DMA operation.
-*
-* The scatter gather list is created and buffer descriptors are inserted into
-* the list.  Buffer descriptors are never removed from the list after it's
-* creation such that a put operation copies from a temporary buffer descriptor
-* to a buffer descriptor in the list.  Get operations don't copy from the list
-* to a temporary, but return a pointer to the buffer descriptor in the list.
-* A buffer descriptor in the list may be locked to prevent it from being
-* overwritten by a put operation.  This allows the device driver to get a
-* descriptor from a scatter gather list and prevent it from being overwritten
-* until the buffer associated with the buffer descriptor has been processed.
-*
-* Typical Scatter Gather Processing
-*
-* The following steps illustrate the typical processing to use the
-* scatter gather features of a DMA channel.
-*
-* 1. Create a scatter gather list for the DMA channel which puts empty buffer
-*    descriptors into the list.
-* 2. Create buffer descriptors which describe the buffers to be filled with
-*	 receive data or the buffers which contain data to be sent.
-* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
-*    gather operations are requested.
-* 4. Commit the buffer descriptors in the list such that they are ready to be
-*    used by the DMA channel hardware.
-* 5. Start the scatter gather operations of the DMA channel.
-* 6. Process any interrupts which occur as a result of the scatter gather
-*    operations or poll the DMA channel to determine the status.
-*
-* Interrupts
-*
-* Each DMA channel has the ability to generate an interrupt.  This component
-* does not perform processing for the interrupt as this processing is typically
-* tightly coupled with the device which is using the DMA channel.  It is the
-* responsibility of the caller of DMA functions to manage the interrupt
-* including connecting to the interrupt and enabling/disabling the interrupt.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the DMA channel.  This
-* component does not use critical sections and it does access registers using
-* read-modify-write operations.  Calls to DMA functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Address Translation
-*
-* All addresses of data structures which are passed to DMA functions must
-* be physical (real) addresses as opposed to logical (virtual) addresses.
-*
-* Caching
-*
-* The memory which is passed to the function which creates the scatter gather
-* list must not be cached such that buffer descriptors are non-cached.  This
-* is necessary because the buffer descriptors are kept in a ring buffer and
-* not directly accessible to the caller of DMA functions.
-*
-* The caller of DMA functions is responsible for ensuring that any data
-* buffers which are passed to the DMA channel are cache-line aligned if
-* necessary.
-*
-* The caller of DMA functions is responsible for ensuring that any data
-* buffers which are passed to the DMA channel have been flushed from the cache.
-*
-* The caller of DMA functions is responsible for ensuring that the cache is
-* invalidated prior to using any data buffers which are the result of a DMA
-* operation.
-*
-* Memory Alignment
-*
-* The addresses of data buffers which are passed to DMA functions must be
-* 32 bit word aligned since the DMA hardware performs 32 bit word transfers.
-*
-* Mutual Exclusion
-*
-* The functions of the DMA channel are not thread safe such that the caller
-* of all DMA functions is responsible for ensuring mutual exclusion for a
-* DMA channel.  Mutual exclusion across multiple DMA channels is not
-* necessary.
-*
-* NOTES:
-*
-* Many of the provided functions which are register accessors don't provide
-* a lot of error detection. The caller is expected to understand the impact
-* of a function call based upon the current state of the DMA channel.  This
-* is done to minimize the overhead in this component.
-*
-******************************************************************************/
-
-#ifndef XDMA_CHANNEL_H		/* prevent circular inclusions */
-#define XDMA_CHANNEL_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel_i.h"	/* constants shared with buffer descriptor */
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-#include "xbuf_descriptor.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants provide access to the bit fields of the DMA control
- * register (DMACR)
- */
-#define XDC_DMACR_SOURCE_INCR_MASK	0x80000000UL	/* increment source address */
-#define XDC_DMACR_DEST_INCR_MASK	0x40000000UL	/* increment dest address */
-#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL	/* local source address */
-#define XDC_DMACR_DEST_LOCAL_MASK	0x10000000UL	/* local dest address */
-#define XDC_DMACR_SG_DISABLE_MASK	0x08000000UL	/* scatter gather disable */
-#define XDC_DMACR_GEN_BD_INTR_MASK	0x04000000UL	/* descriptor interrupt */
-#define XDC_DMACR_LAST_BD_MASK		XDC_CONTROL_LAST_BD_MASK	/* last buffer */
-															 /*     descriptor  */
-
-/* the following constants provide access to the bit fields of the DMA status
- * register (DMASR)
- */
-#define XDC_DMASR_BUSY_MASK			0x80000000UL	/* channel is busy */
-#define XDC_DMASR_BUS_ERROR_MASK	0x40000000UL	/* bus error occurred */
-#define XDC_DMASR_BUS_TIMEOUT_MASK	0x20000000UL	/* bus timeout occurred */
-#define XDC_DMASR_LAST_BD_MASK		XDC_STATUS_LAST_BD_MASK	/* last buffer */
-														    /* descriptor  */
-#define XDC_DMASR_SG_BUSY_MASK		0x08000000UL	/* scatter gather is busy */
-
-/* the following constants provide access to the bit fields of the interrupt
- * status register (ISR) and the interrupt enable register (IER), bit masks
- * match for both registers such that they are named IXR
- */
-#define XDC_IXR_DMA_DONE_MASK		0x1UL	/* dma operation done */
-#define XDC_IXR_DMA_ERROR_MASK	    0x2UL	/* dma operation error */
-#define XDC_IXR_PKT_DONE_MASK	    0x4UL	/* packet done */
-#define XDC_IXR_PKT_THRESHOLD_MASK	0x8UL	/* packet count threshold */
-#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL	/* packet wait bound reached */
-#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL	/* scatter gather disable
-						   acknowledge occurred */
-#define XDC_IXR_SG_END_MASK			0x40UL	/* last buffer descriptor
-							   disabled scatter gather */
-#define XDC_IXR_BD_MASK				0x80UL	/* buffer descriptor done */
-
-/**************************** Type Definitions *******************************/
-
-/*
- * the following structure contains data which is on a per instance basis
- * for the XDmaChannel component
- */
-typedef struct XDmaChannelTag {
-	XVersion Version;	/* version of the driver */
-	u32 RegBaseAddress;	/* base address of registers */
-	u32 IsReady;		/* device is initialized and ready */
-
-	XBufDescriptor *PutPtr;	/* keep track of where to put into list */
-	XBufDescriptor *GetPtr;	/* keep track of where to get from list */
-	XBufDescriptor *CommitPtr;	/* keep track of where to commit in list */
-	XBufDescriptor *LastPtr;	/* keep track of the last put in the list */
-	u32 TotalDescriptorCount;	/* total # of descriptors in the list */
-	u32 ActiveDescriptorCount;	/* # of descriptors pointing to buffers
-					   * in the buffer descriptor list */
-} XDmaChannel;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress);
-u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr);
-XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr);
-void XDmaChannel_Reset(XDmaChannel * InstancePtr);
-
-/* Control functions */
-
-u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr);
-void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control);
-
-/* Status functions */
-
-u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr);
-void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status);
-u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr);
-void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable);
-u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr);
-
-/* DMA without scatter gather functions */
-
-void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
-			  u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount);
-
-/* Scatter gather functions */
-
-XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr,
-			   XBufDescriptor ** BufDescriptorPtr);
-XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
-				 u32 * MemoryPtr, u32 ByteCount);
-u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr);
-
-XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
-				  XBufDescriptor * BufDescriptorPtr);
-XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
-				  XBufDescriptor ** BufDescriptorPtr);
-
-/* Packet functions for interrupt collescing */
-
-u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr);
-void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold);
-u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr);
-void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound);
-u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr);
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel_i.h b/board/xilinx/common/xdma_channel_i.h
deleted file mode 100644
index e9f343b..0000000
--- a/board/xilinx/common/xdma_channel_i.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel_i.h
-*
-* DESCRIPTION:
-*
-* This file contains data which is shared internal data for the DMA channel
-* component. It is also shared with the buffer descriptor component which is
-* very tightly coupled with the DMA channel component.
-*
-* NOTES:
-*
-* The last buffer descriptor constants must be located here to prevent a
-* circular dependency between the DMA channel component and the buffer
-* descriptor component.
-*
-******************************************************************************/
-
-#ifndef XDMA_CHANNEL_I_H	/* prevent circular inclusions */
-#define XDMA_CHANNEL_I_H	/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XDC_DMA_CHANNEL_V1_00_A		"1.00a"
-
-/* the following constant provides access to the bit fields of the DMA control
- * register (DMACR) which must be shared between the DMA channel component
- * and the buffer descriptor component
- */
-#define XDC_CONTROL_LAST_BD_MASK	0x02000000UL	/* last buffer descriptor */
-
-/* the following constant provides access to the bit fields of the DMA status
- * register (DMASR) which must be shared between the DMA channel component
- * and the buffer descriptor component
- */
-#define XDC_STATUS_LAST_BD_MASK		0x10000000UL	/* last buffer descriptor */
-
-/* the following constants provide access to each of the registers of a DMA
- * channel
- */
-#define XDC_RST_REG_OFFSET	0	/* reset register */
-#define XDC_MI_REG_OFFSET	0	/* module information register */
-#define XDC_DMAC_REG_OFFSET	4	/* DMA control register */
-#define XDC_SA_REG_OFFSET	8	/* source address register */
-#define XDC_DA_REG_OFFSET	12	/* destination address register */
-#define XDC_LEN_REG_OFFSET	16	/* length register */
-#define XDC_DMAS_REG_OFFSET	20	/* DMA status register */
-#define XDC_BDA_REG_OFFSET	24	/* buffer descriptor address register */
-#define XDC_SWCR_REG_OFFSET 28	/* software control register */
-#define XDC_UPC_REG_OFFSET	32	/* unserviced packet count register */
-#define	XDC_PCT_REG_OFFSET	36	/* packet count threshold register */
-#define XDC_PWB_REG_OFFSET	40	/* packet wait bound register */
-#define XDC_IS_REG_OFFSET	44	/* interrupt status register */
-#define XDC_IE_REG_OFFSET	48	/* interrupt enable register */
-
-/* the following constant is written to the reset register to reset the
- * DMA channel
- */
-#define XDC_RESET_MASK				0x0000000AUL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel_sg.c b/board/xilinx/common/xdma_channel_sg.c
deleted file mode 100644
index a8e9462..0000000
--- a/board/xilinx/common/xdma_channel_sg.c
+++ /dev/null
@@ -1,1317 +0,0 @@
-/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel_sg.c
-*
-* DESCRIPTION:
-*
-* This file contains the implementation of the XDmaChannel component which is
-* related to scatter gather operations.
-*
-* Scatter Gather Operations
-*
-* The DMA channel may support scatter gather operations. A scatter gather
-* operation automates the DMA channel such that multiple buffers can be
-* sent or received with minimal software interaction with the hardware.	 Buffer
-* descriptors, contained in the XBufDescriptor component, are used by the
-* scatter gather operations of the DMA channel to describe the buffers to be
-* processed.
-*
-* Scatter Gather List Operations
-*
-* A scatter gather list may be supported by each DMA channel.  The scatter
-* gather list allows buffer descriptors to be put into the list by a device
-* driver which requires scatter gather.	 The hardware processes the buffer
-* descriptors which are contained in the list and modifies the buffer
-* descriptors to reflect the status of the DMA operations.  The device driver
-* is notified by interrupt that specific DMA events occur including scatter
-* gather events.  The device driver removes the completed buffer descriptors
-* from the scatter gather list to evaluate the status of each DMA operation.
-*
-* The scatter gather list is created and buffer descriptors are inserted into
-* the list.  Buffer descriptors are never removed from the list after it's
-* creation such that a put operation copies from a temporary buffer descriptor
-* to a buffer descriptor in the list.  Get operations don't copy from the list
-* to a temporary, but return a pointer to the buffer descriptor in the list.
-* A buffer descriptor in the list may be locked to prevent it from being
-* overwritten by a put operation.  This allows the device driver to get a
-* descriptor from a scatter gather list and prevent it from being overwritten
-* until the buffer associated with the buffer descriptor has been processed.
-*
-* The get and put functions only operate on the list and are asynchronous from
-* the hardware which may be using the list of descriptors.  This is important
-* because there are no checks in the get and put functions to ensure that the
-* hardware has processed the descriptors.  This must be handled by the driver
-* using the DMA scatter gather channel through the use of the other functions.
-* When a scatter gather operation is started, the start function does ensure
-* that the descriptor to start has not already been processed by the hardware
-* and is not the first of a series of descriptors that have not been committed
-* yet.
-*
-* Descriptors are put into the list but not marked as ready to use by the
-* hardware until a commit operation is done.  This allows multiple descriptors
-* which may contain a single packet of information for a protocol to be
-* guaranteed not to cause any underflow conditions during transmission. The
-* hardware design only allows descriptors to cause it to stop after a descriptor
-* has been processed rather than before it is processed.  A series of
-* descriptors are put into the list followed by a commit operation, or each
-* descriptor may be commited.  A commit operation is performed by changing a
-* single descriptor, the first of the series of puts, to indicate that the
-* hardware may now use all descriptors after it.  The last descriptor in the
-* list is always set to cause the hardware to stop after it is processed.
-*
-* Typical Scatter Gather Processing
-*
-* The following steps illustrate the typical processing to use the
-* scatter gather features of a DMA channel.
-*
-* 1. Create a scatter gather list for the DMA channel which puts empty buffer
-*    descriptors into the list.
-* 2. Create buffer descriptors which describe the buffers to be filled with
-*    receive data or the buffers which contain data to be sent.
-* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
-*    gather operations are requested.
-* 4. Commit the buffer descriptors in the list such that they are ready to be
-*    used by the DMA channel hardware.
-* 5. Start the scatter gather operations of the DMA channel.
-* 6. Process any interrupts which occur as a result of the scatter gather
-*    operations or poll the DMA channel to determine the status.  This may
-*    be accomplished by getting the packet count for the channel and then
-*    getting the appropriate number of descriptors from the list for that
-*    number of packets.
-*
-* Minimizing Interrupts
-*
-* The Scatter Gather operating mode is designed to reduce the amount of CPU
-* throughput necessary to manage the hardware for devices. A key to the CPU
-* throughput is the number and rate of interrupts that the CPU must service.
-* Devices with higher data rates can cause larger numbers of interrupts and
-* higher frequency interrupts. Ideally the number of interrupts can be reduced
-* by only generating an interrupt when a specific amount of data has been
-* received from the interface. This design suffers from a lack of interrupts
-* when the amount of data received is less than the specified amount of data
-* to generate an interrupt. In order to help minimize the number of interrupts
-* which the CPU must service, an algorithm referred to as "interrupt coalescing"
-* is utilized.
-*
-* Interrupt Coalescing
-*
-* The principle of interrupt coalescing is to wait before generating an
-* interrupt until a certain number of packets have been received or sent. An
-* interrupt is also generated if a smaller number of packets have been received
-* followed by a certain period of time with no packet reception. This is a
-* trade-off of latency for bandwidth and is accomplished using several
-* mechanisms of the hardware including a counter for packets received or
-* transmitted and a packet timer. These two hardware mechanisms work in
-* combination to allow a reduction in the number of interrupts processed by the
-* CPU for packet reception.
-*
-* Unserviced Packet Count
-*
-* The purpose of the packet counter is to count the number of packets received
-* or transmitted and provide an interrupt when a specific number of packets
-* have been processed by the hardware. An interrupt is generated whenever the
-* counter is greater than or equal to the Packet Count Threshold. This counter
-* contains an accurate count of the number of packets that the hardware has
-* processed, either received or transmitted, and the software has not serviced.
-*
-* The packet counter allows the number of interrupts to be reduced by waiting
-* to generate an interrupt until enough packets are received. For packet
-* reception, packet counts of less than the number to generate an interrupt
-* would not be serviced without the addition of a packet timer. This counter is
-* continuously updated by the hardware, not latched to the value at the time
-* the interrupt occurred.
-*
-* The packet counter can be used within the interrupt service routine for the
-* device to reduce the number of interrupts. The interrupt service routine
-* loops while performing processing for each packet which has been received or
-* transmitted and decrements the counter by a specified value. At the same time,
-* the hardware is possibly continuing to receive or transmit more packets such
-* that the software may choose, based upon the value in the packet counter, to
-* remain in the interrupt service routine rather than exiting and immediately
-* returning. This feature should be used with caution as reducing the number of
-* interrupts is beneficial, but unbounded interrupt processing is not desirable.
-*
-* Since the hardware may be incrementing the packet counter simultaneously
-* with the software decrementing the counter, there is a need for atomic
-* operations. The hardware ensures that the operation is atomic such that
-* simultaneous accesses are properly handled.
-*
-* Packet Wait Bound
-*
-* The purpose of the packet wait bound is to augment the unserviced packet
-* count. Whenever there is no pending interrupt for the channel and the
-* unserviced packet count is non-zero, a timer starts counting timeout at the
-* value contained the the packet wait bound register.  If the timeout is
-* reached, an interrupt is generated such that the software may service the
-* data which was buffered.
-*
-* NOTES:
-*
-* Special Test Conditions:
-*
-* The scatter gather list processing must be thoroughly tested if changes are
-* made.	 Testing should include putting and committing single descriptors and
-* putting multiple descriptors followed by a single commit.  There are some
-* conditions in the code which handle the exception conditions.
-*
-* The Put Pointer points to the next location in the descriptor list to copy
-* in a new descriptor. The Get Pointer points to the next location in the
-* list to get a descriptor from.  The Get Pointer only allows software to
-* have a traverse the list after the hardware has finished processing some
-* number of descriptors.  The Commit Pointer points to the descriptor in the
-* list which is to be committed.  It is also used to determine that no
-* descriptor is waiting to be commited (NULL).	The Last Pointer points to
-* the last descriptor that was put into the list.  It typically points
-* to the previous descriptor to the one pointed to by the Put Pointer.
-* Comparisons are done between these pointers to determine when the following
-* special conditions exist.
-
-* Single Put And Commit
-*
-* The buffer descriptor is ready to be used by the hardware so it is important
-* for the descriptor to not appear to be waiting to be committed.  The commit
-* pointer is reset when a commit is done indicating there are no descriptors
-* waiting to be committed.  In all cases but this one, the descriptor is
-* changed to cause the hardware to go to the next descriptor after processing
-* this one.  But in this case, this is the last descriptor in the list such
-* that it must not be changed.
-*
-* 3 Or More Puts And Commit
-*
-* A series of 3 or more puts followed by a single commit is different in that
-* only the 1st descriptor put into the list is changed when the commit is done.
-* This requires each put starting on the 3rd to change the previous descriptor
-* so that it allows the hardware to continue to the next descriptor in the list.
-*
-* The 1st Put Following A Commit
-*
-* The commit caused the commit pointer to be NULL indicating that there are no
-* descriptors waiting to be committed.	It is necessary for the next put to set
-* the commit pointer so that a commit must follow the put for the hardware to
-* use the descriptor.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- ------------------------------------------------------
-* 1.00a rpm  02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
-*		      from SetPktThreshold.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel.h"
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xbuf_descriptor.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL	/* scatter gather enable */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/* the following macro copies selected fields of a buffer descriptor to another
- * buffer descriptor, this was provided by the buffer descriptor component but
- * was moved here since it is only used internally to this component and since
- * it does not copy all fields
- */
-#define CopyBufferDescriptor(InstancePtr, DestinationPtr)	   \
-{								   \
-    *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) =	       \
-	*((u32 *)InstancePtr + XBD_CONTROL_OFFSET);	       \
-    *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) =	       \
-	*((u32 *)InstancePtr + XBD_SOURCE_OFFSET);	       \
-    *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) =	       \
-	*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET);	       \
-    *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) =	       \
-	*((u32 *)InstancePtr + XBD_LENGTH_OFFSET);	       \
-    *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) =	       \
-	*((u32 *)InstancePtr + XBD_STATUS_OFFSET);	       \
-    *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) =      \
-	*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET);      \
-    *((u32 *)DestinationPtr + XBD_ID_OFFSET) =		       \
-	*((u32 *)InstancePtr + XBD_ID_OFFSET);		       \
-    *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) =	       \
-	*((u32 *)InstancePtr + XBD_FLAGS_OFFSET);	       \
-    *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) =      \
-	*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET);      \
-}
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SgStart
-*
-* DESCRIPTION:
-*
-* This function starts a scatter gather operation for a scatter gather
-* DMA channel.	The first buffer descriptor in the buffer descriptor list
-* will be started with the scatter gather operation.  A scatter gather list
-* should have previously been created for the DMA channel and buffer
-* descriptors put into the scatter gather list such that there are scatter
-* operations ready to be performed.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if scatter gather was started successfully
-* for the DMA channel.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started
-* because the scatter gather list of the DMA channel does not contain any
-* buffer descriptors that are ready to be processed by the hardware.
-*
-* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started
-* because the scatter gather was not stopped, but was already started.
-*
-* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of
-* scatter gather list which was to be started is not committed to the list.
-* This status is more likely if this function is being called from an ISR
-* and non-ISR processing is putting descriptors into the list.
-*
-* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the
-* scatter gather list which was to be started had already been used by the
-* hardware for a DMA transfer that has been completed.
-*
-* NOTES:
-*
-* It is the responsibility of the caller to get all the buffer descriptors
-* after performing a stop operation and before performing a start operation.
-* If buffer descriptors are not retrieved between stop and start operations,
-* buffer descriptors may be processed by the hardware more than once.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SgStart(XDmaChannel * InstancePtr)
-{
-	u32 Register;
-	XBufDescriptor *LastDescriptorPtr;
-
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if a scatter gather list has not been created yet, return a status */
-
-	if (InstancePtr->TotalDescriptorCount == 0) {
-		return XST_DMA_SG_NO_LIST;
-	}
-
-	/* if the scatter gather list exists but is empty then return a status */
-
-	if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
-		return XST_DMA_SG_LIST_EMPTY;
-	}
-
-	/* if scatter gather is busy for the DMA channel, return a status because
-	 * restarting it could lose data
-	 */
-
-	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
-	if (Register & XDC_DMASR_SG_BUSY_MASK) {
-		return XST_DMA_SG_IS_STARTED;
-	}
-
-	/* get the address of the last buffer descriptor which the DMA hardware
-	 * finished processing
-	 */
-	LastDescriptorPtr =
-	    (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
-					XDC_BDA_REG_OFFSET);
-
-	/* setup the first buffer descriptor that will be sent when the scatter
-	 * gather channel is enabled, this is only necessary one time since
-	 * the BDA register of the channel maintains the last buffer descriptor
-	 * processed
-	 */
-	if (LastDescriptorPtr == NULL) {
-		XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET,
-			  (u32) InstancePtr->GetPtr);
-	} else {
-		XBufDescriptor *NextDescriptorPtr;
-
-		/* get the next descriptor to be started, if the status indicates it
-		 * hasn't already been used by the h/w, then it's OK to start it,
-		 * s/w sets the status of each descriptor to busy and then h/w clears
-		 * the busy when it is complete
-		 */
-		NextDescriptorPtr =
-		    XBufDescriptor_GetNextPtr(LastDescriptorPtr);
-
-		if ((XBufDescriptor_GetStatus(NextDescriptorPtr) &
-		     XDC_DMASR_BUSY_MASK) == 0) {
-			return XST_DMA_SG_NO_DATA;
-		}
-		/* don't start the DMA SG channel if the descriptor to be processed
-		 * by h/w is to be committed by the s/w, this function can be called
-		 * such that it interrupts a thread that was putting into the list
-		 */
-		if (NextDescriptorPtr == InstancePtr->CommitPtr) {
-			return XST_DMA_SG_BD_NOT_COMMITTED;
-		}
-	}
-
-	/* start the scatter gather operation by clearing the stop bit in the
-	 * control register and setting the enable bit in the s/w control register,
-	 * both of these are necessary to cause it to start, right now the order of
-	 * these statements is important, the software control register should be
-	 * set 1st.  The other order can cause the CPU to have a loss of sync
-	 * because it cannot read/write the register while the DMA operation is
-	 * running
-	 */
-
-	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
-
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
-		  Register | XDC_SWCR_SG_ENABLE_MASK);
-
-	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
-
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET,
-		  Register & ~XDC_DMACR_SG_DISABLE_MASK);
-
-	/* indicate the DMA channel scatter gather operation was started
-	 * successfully
-	 */
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SgStop
-*
-* DESCRIPTION:
-*
-* This function stops a scatter gather operation for a scatter gather
-* DMA channel. This function starts the process of stopping a scatter
-* gather operation that is in progress and waits for the stop to be completed.
-* Since it waits for the operation to stopped before returning, this function
-* could take an amount of time relative to the size of the DMA scatter gather
-* operation which is in progress.  The scatter gather list of the DMA channel
-* is not modified by this function such that starting the scatter gather
-* channel after stopping it will cause it to resume.  This operation is
-* considered to be a graceful stop in that the scatter gather operation
-* completes the current buffer descriptor before stopping.
-*
-* If the interrupt is enabled, an interrupt will be generated when the
-* operation is stopped and the caller is responsible for handling the
-* interrupt.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufDescriptorPtr is also a return value which contains a pointer to the
-* buffer descriptor which the scatter gather operation completed when it
-* was stopped.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if scatter gather was stopped successfully
-* for the DMA channel.
-*
-* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped
-* because the scatter gather is not started, but was already stopped.
-*
-* BufDescriptorPtr contains a pointer to the buffer descriptor which was
-* completed when the operation was stopped.
-*
-* NOTES:
-*
-* This function implements a loop which polls the hardware for an infinite
-* amount of time. If the hardware is not operating correctly, this function
-* may never return.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SgStop(XDmaChannel * InstancePtr,
-		   XBufDescriptor ** BufDescriptorPtr)
-{
-	u32 Register;
-
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(BufDescriptorPtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* get the contents of the software control register, if scatter gather is not
-	 * enabled (started), then return a status because the disable acknowledge
-	 * would not be generated
-	 */
-	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
-
-	if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) {
-		return XST_DMA_SG_IS_STOPPED;
-	}
-
-	/* Ensure the interrupt status for the scatter gather is cleared such
-	 * that this function will wait til the disable has occurred, writing
-	 * a 1 to only that bit in the register will clear only it
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
-		  XDC_IXR_SG_DISABLE_ACK_MASK);
-
-	/* disable scatter gather by writing to the software control register
-	 * without modifying any other bits of the register
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
-		  Register & ~XDC_SWCR_SG_ENABLE_MASK);
-
-	/* scatter gather does not disable immediately, but after the current
-	 * buffer descriptor is complete, so wait for the DMA channel to indicate
-	 * the disable is complete
-	 */
-	do {
-		Register =
-		    XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
-	} while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0);
-
-	/* Ensure the interrupt status for the scatter gather disable is cleared,
-	 * writing a 1 to only that bit in the register will clear only it
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
-		  XDC_IXR_SG_DISABLE_ACK_MASK);
-
-	/* set the specified buffer descriptor pointer to point to the buffer
-	 * descriptor that the scatter gather DMA channel was processing
-	 */
-	*BufDescriptorPtr =
-	    (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
-					XDC_BDA_REG_OFFSET);
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_CreateSgList
-*
-* DESCRIPTION:
-*
-* This function creates a scatter gather list in the DMA channel.  A scatter
-* gather list consists of a list of buffer descriptors that are available to
-* be used for scatter gather operations.  Buffer descriptors are put into the
-* list to request a scatter gather operation to be performed.
-*
-* A number of buffer descriptors are created from the specified memory and put
-* into a buffer descriptor list as empty buffer descriptors. This function must
-* be called before non-empty buffer descriptors may be put into the DMA channel
-* to request scatter gather operations.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* MemoryPtr contains a pointer to the memory which is to be used for buffer
-* descriptors and must not be cached.
-*
-* ByteCount contains the number of bytes for the specified memory to be used
-* for buffer descriptors.
-*
-* RETURN VALUE:
-*
-* A status contains XST_SUCCESS if the scatter gather list was successfully
-* created.
-*
-* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list
-* was not created because the list has already been created.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
-			 u32 * MemoryPtr, u32 ByteCount)
-{
-	XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr;
-	XBufDescriptor *PreviousDescriptorPtr = NULL;
-	XBufDescriptor *StartOfListPtr = BufferDescriptorPtr;
-	u32 UsedByteCount;
-
-	/* assert to verify valid input arguments, alignment for those
-	 * arguments that have alignment restrictions, and at least enough
-	 * memory for one buffer descriptor
-	 */
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(MemoryPtr != NULL);
-	XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0);
-	XASSERT_NONVOID(ByteCount != 0);
-	XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor));
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if the scatter gather list has already been created, then return
-	 * with a status
-	 */
-	if (InstancePtr->TotalDescriptorCount != 0) {
-		return XST_DMA_SG_LIST_EXISTS;
-	}
-
-	/* loop thru the specified memory block and create as many buffer
-	 * descriptors as possible putting each into the list which is
-	 * implemented as a ring buffer, make sure not to use any memory which
-	 * is not large enough for a complete buffer descriptor
-	 */
-	UsedByteCount = 0;
-	while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) {
-		/* setup a pointer to the next buffer descriptor in the memory and
-		 * update # of used bytes to know when all of memory is used
-		 */
-		BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr +
-							  UsedByteCount);
-
-		/* initialize the new buffer descriptor such that it doesn't contain
-		 * garbage which could be used by the DMA hardware
-		 */
-		XBufDescriptor_Initialize(BufferDescriptorPtr);
-
-		/* if this is not the first buffer descriptor to be created,
-		 * then link it to the last created buffer descriptor
-		 */
-		if (PreviousDescriptorPtr != NULL) {
-			XBufDescriptor_SetNextPtr(PreviousDescriptorPtr,
-						  BufferDescriptorPtr);
-		}
-
-		/* always keep a pointer to the last created buffer descriptor such
-		 * that they can be linked together in the ring buffer
-		 */
-		PreviousDescriptorPtr = BufferDescriptorPtr;
-
-		/* keep a count of the number of descriptors in the list to allow
-		 * error processing to be performed
-		 */
-		InstancePtr->TotalDescriptorCount++;
-
-		UsedByteCount += sizeof (XBufDescriptor);
-	}
-
-	/* connect the last buffer descriptor created and inserted in the list
-	 * to the first such that a ring buffer is created
-	 */
-	XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr);
-
-	/* initialize the ring buffer to indicate that there are no
-	 * buffer descriptors in the list which point to valid data buffers
-	 */
-	InstancePtr->PutPtr = BufferDescriptorPtr;
-	InstancePtr->GetPtr = BufferDescriptorPtr;
-	InstancePtr->CommitPtr = NULL;
-	InstancePtr->LastPtr = BufferDescriptorPtr;
-	InstancePtr->ActiveDescriptorCount = 0;
-
-	/* indicate the scatter gather list was successfully created */
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_IsSgListEmpty
-*
-* DESCRIPTION:
-*
-* This function determines if the scatter gather list of a DMA channel is
-* empty with regard to buffer descriptors which are pointing to buffers to be
-* used for scatter gather operations.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A value of TRUE if the scatter gather list is empty, otherwise a value of
-* FALSE.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr)
-{
-	/* assert to verify valid input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if the number of descriptors which are being used in the list is zero
-	 * then the list is empty
-	 */
-	return (InstancePtr->ActiveDescriptorCount == 0);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_PutDescriptor
-*
-* DESCRIPTION:
-*
-* This function puts a buffer descriptor into the DMA channel scatter
-* gather list. A DMA channel maintains a list of buffer descriptors which are
-* to be processed.  This function puts the specified buffer descriptor
-* at the next location in the list.  Note that since the list is already intact,
-* the information in the parameter is copied into the list (rather than modify
-* list pointers on the fly).
-*
-* After buffer descriptors are put into the list, they must also be committed
-* by calling another function.	This allows multiple buffer descriptors which
-* span a single packet to be put into the list while preventing the hardware
-* from starting the first buffer descriptor of the packet.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into
-* the next available location of the scatter gather list.
-*
-* RETURN VALUE:
-*
-* A status which indicates XST_SUCCESS if the buffer descriptor was
-* successfully put into the scatter gather list.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not
-* put into the list because the list was full.
-*
-* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not
-* put into the list because the buffer descriptor in the list which is to
-* be overwritten was locked.  A locked buffer descriptor indicates the higher
-* layered software is still using the buffer descriptor.
-*
-* NOTES:
-*
-* It is necessary to create a scatter gather list for a DMA channel before
-* putting buffer descriptors into it.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
-			  XBufDescriptor * BufferDescriptorPtr)
-{
-	u32 Control;
-
-	/* assert to verify valid input arguments and alignment for those
-	 * arguments that have alignment restrictions
-	 */
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(BufferDescriptorPtr != NULL);
-	XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if a scatter gather list has not been created yet, return a status */
-
-	if (InstancePtr->TotalDescriptorCount == 0) {
-		return XST_DMA_SG_NO_LIST;
-	}
-
-	/* if the list is full because all descriptors are pointing to valid
-	 * buffers, then indicate an error, this code assumes no list or an
-	 * empty list is detected above
-	 */
-	if (InstancePtr->ActiveDescriptorCount ==
-	    InstancePtr->TotalDescriptorCount) {
-		return XST_DMA_SG_LIST_FULL;
-	}
-
-	/* if the buffer descriptor in the list which is to be overwritten is
-	 * locked, then don't overwrite it and return a status
-	 */
-	if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) {
-		return XST_DMA_SG_BD_LOCKED;
-	}
-
-	/* set the scatter gather stop bit in the control word of the descriptor
-	 * to cause the h/w to stop after it processes this descriptor since it
-	 * will be the last in the list
-	 */
-	Control = XBufDescriptor_GetControl(BufferDescriptorPtr);
-	XBufDescriptor_SetControl(BufferDescriptorPtr,
-				  Control | XDC_DMACR_SG_DISABLE_MASK);
-
-	/* set both statuses in the descriptor so we tell if they are updated with
-	 * the status of the transfer, the hardware should change the busy in the
-	 * DMA status to be false when it completes
-	 */
-	XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK);
-	XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0);
-
-	/* copy the descriptor into the next position in the list so it's ready to
-	 * be used by the h/w, this assumes the descriptor in the list prior to this
-	 * one still has the stop bit in the control word set such that the h/w
-	 * use this one yet
-	 */
-	CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr);
-
-	/* only the last in the list and the one to be committed have scatter gather
-	 * disabled in the control word, a commit requires only one descriptor
-	 * to be changed, when # of descriptors to commit > 2 all others except the
-	 * 1st and last have scatter gather enabled
-	 */
-	if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) &&
-	    (InstancePtr->CommitPtr != NULL)) {
-		Control = XBufDescriptor_GetControl(InstancePtr->LastPtr);
-		XBufDescriptor_SetControl(InstancePtr->LastPtr,
-					  Control & ~XDC_DMACR_SG_DISABLE_MASK);
-	}
-
-	/* update the list data based upon putting a descriptor into the list,
-	 * these operations must be last
-	 */
-	InstancePtr->ActiveDescriptorCount++;
-
-	/* only update the commit pointer if it is not already active, this allows
-	 * it to be deactivated after every commit such that a single descriptor
-	 * which is committed does not appear to be waiting to be committed
-	 */
-	if (InstancePtr->CommitPtr == NULL) {
-		InstancePtr->CommitPtr = InstancePtr->LastPtr;
-	}
-
-	/* these updates MUST BE LAST after the commit pointer update in order for
-	 * the commit pointer to track the correct descriptor to be committed
-	 */
-	InstancePtr->LastPtr = InstancePtr->PutPtr;
-	InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr);
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_CommitPuts
-*
-* DESCRIPTION:
-*
-* This function commits the buffer descriptors which have been put into the
-* scatter list for the DMA channel since the last commit operation was
-* performed.  This enables the calling functions to put several buffer
-* descriptors into the list (e.g.,a packet's worth) before allowing the scatter
-* gather operations to start.  This prevents the DMA channel hardware from
-* starting to use the buffer descriptors in the list before they are ready
-* to be used (multiple buffer descriptors for a single packet).
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if the buffer descriptors of the list were
-* successfully committed.
-*
-* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors
-* were not committed because there was nothing to commit in the list.  All the
-* buffer descriptors which are in the list are commited.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_CommitPuts(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if the buffer descriptor to be committed is already committed or
-	 * the list is empty (none have been put in), then indicate an error
-	 */
-	if ((InstancePtr->CommitPtr == NULL) ||
-	    XDmaChannel_IsSgListEmpty(InstancePtr)) {
-		return XST_DMA_SG_NOTHING_TO_COMMIT;
-	}
-
-	/* last descriptor in the list must have scatter gather disabled so the end
-	 * of the list is hit by h/w, if descriptor to commit is not last in list,
-	 * commit descriptors by enabling scatter gather in the descriptor
-	 */
-	if (InstancePtr->CommitPtr != InstancePtr->LastPtr) {
-		u32 Control;
-
-		Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr);
-		XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control &
-					  ~XDC_DMACR_SG_DISABLE_MASK);
-	}
-	/* Update the commit pointer to indicate that there is nothing to be
-	 * committed, this state is used by start processing to know that the
-	 * buffer descriptor to start is not waiting to be committed
-	 */
-	InstancePtr->CommitPtr = NULL;
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetDescriptor
-*
-* DESCRIPTION:
-*
-* This function gets a buffer descriptor from the scatter gather list of the
-* DMA channel. The buffer descriptor is retrieved from the scatter gather list
-* and the scatter gather list is updated to not include the retrieved buffer
-* descriptor.  This is typically done after a scatter gather operation
-* completes indicating that a data buffer has been successfully sent or data
-* has been received into the data buffer. The purpose of this function is to
-* allow the device using the scatter gather operation to get the results of the
-* operation.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which
-* was retrieved from the list.	The buffer descriptor is not really removed
-* from the list, but it is changed to a state such that the hardware will not
-* use it again until it is put into the scatter gather list of the DMA channel.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from
-* the scatter gather list of the DMA channel.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was
-* retrieved from the list because there are no buffer descriptors to be
-* processed in the list.
-*
-* BufDescriptorPtr is updated to point to the buffer descriptor which was
-* retrieved from the list if the status indicates success.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
-			  XBufDescriptor ** BufDescriptorPtr)
-{
-	u32 Control;
-
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(BufDescriptorPtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if a scatter gather list has not been created yet, return a status */
-
-	if (InstancePtr->TotalDescriptorCount == 0) {
-		return XST_DMA_SG_NO_LIST;
-	}
-
-	/* if the buffer descriptor list is empty, then indicate an error */
-
-	if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
-		return XST_DMA_SG_LIST_EMPTY;
-	}
-
-	/* retrieve the next buffer descriptor which is ready to be processed from
-	 * the buffer descriptor list for the DMA channel, set the control word
-	 * such that hardware will stop after the descriptor has been processed
-	 */
-	Control = XBufDescriptor_GetControl(InstancePtr->GetPtr);
-	XBufDescriptor_SetControl(InstancePtr->GetPtr,
-				  Control | XDC_DMACR_SG_DISABLE_MASK);
-
-	/* set the input argument, which is also an output, to point to the
-	 * buffer descriptor which is to be retrieved from the list
-	 */
-	*BufDescriptorPtr = InstancePtr->GetPtr;
-
-	/* update the pointer of the DMA channel to reflect the buffer descriptor
-	 * was retrieved from the list by setting it to the next buffer descriptor
-	 * in the list and indicate one less descriptor in the list now
-	 */
-	InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr);
-	InstancePtr->ActiveDescriptorCount--;
-
-	return XST_SUCCESS;
-}
-
-/*********************** Interrupt Collescing Functions **********************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktCount
-*
-* DESCRIPTION:
-*
-* This function returns the value of the unserviced packet count register of
-* the DMA channel.  This count represents the number of packets that have been
-* sent or received by the hardware, but not processed by software.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The unserviced packet counter register contents for the DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetPktCount(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* get the unserviced packet count from the register and return it */
-
-	return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_DecrementPktCount
-*
-* DESCRIPTION:
-*
-* This function decrements the value of the unserviced packet count register.
-* This informs the hardware that the software has processed a packet.  The
-* unserviced packet count register may only be decremented by one in the
-* hardware.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr)
-{
-	u32 Register;
-
-	/* assert to verify input arguments */
-
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* if the unserviced packet count register can be decremented (rather
-	 * than rolling over) decrement it by writing a 1 to the register,
-	 * this is the only valid write to the register as it serves as an
-	 * acknowledge that a packet was handled by the software
-	 */
-	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
-	if (Register > 0) {
-		XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET,
-			  1UL);
-	}
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetPktThreshold
-*
-* DESCRIPTION:
-*
-* This function sets the value of the packet count threshold register of the
-* DMA channel.	It reflects the number of packets that must be sent or
-* received before generating an interrupt.  This value helps implement
-* a concept called "interrupt coalescing", which is used to reduce the number
-* of interrupts from devices with high data rates.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* Threshold is the value that is written to the threshold register of the
-* DMA channel.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if the packet count threshold was
-* successfully set.
-*
-* NOTES:
-*
-* The packet threshold could be set to larger than the number of descriptors
-* allocated to the DMA channel. In this case, the wait bound will take over
-* and always indicate data arrival. There was a check in this function that
-* returned an error if the treshold was larger than the number of descriptors,
-* but that was removed because users would then have to set the threshold
-* only after they set descriptor space, which is an order dependency that
-* caused confustion.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold)
-{
-	/* assert to verify input arguments, don't assert the threshold since
-	 * it's range is unknown
-	 */
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* set the packet count threshold in the register such that an interrupt
-	 * may be generated, if enabled, when the packet count threshold is
-	 * reached or exceeded
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET,
-		  (u32) Threshold);
-
-	/* indicate the packet count threshold was successfully set */
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktThreshold
-*
-* DESCRIPTION:
-*
-* This function gets the value of the packet count threshold register of the
-* DMA channel.	This value reflects the number of packets that must be sent or
-* received before generating an interrupt.  This value helps implement a concept
-* called "interrupt coalescing", which is used to reduce the number of
-* interrupts from devices with high data rates.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The packet threshold register contents for the DMA channel and is a value in
-* the range 0 - 1023.  A value of 0 indicates the packet wait bound timer is
-* disabled.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u8
-XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* get the packet count threshold from the register and return it,
-	 * since only 8 bits are used, cast it to return only those bits */
-
-	return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetPktWaitBound
-*
-* DESCRIPTION:
-*
-* This function sets the value of the packet wait bound register of the
-* DMA channel.	This value reflects the timer value used to trigger an
-* interrupt when not enough packets have been received to reach the packet
-* count threshold.
-*
-* The timer is in millisecond units with +/- 33% accuracy.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* WaitBound is the value, in milliseconds, to be stored in the wait bound
-* register of the DMA channel and is a value in the range 0  - 1023.  A value
-* of 0 disables the packet wait bound timer.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(WaitBound < 1024);
-	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* set the packet wait bound in the register such that interrupt may be
-	 * generated, if enabled, when packets have not been handled for a specific
-	 * amount of time
-	 */
-	XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktWaitBound
-*
-* DESCRIPTION:
-*
-* This function gets the value of the packet wait bound register of the
-* DMA channel.	This value contains the timer value used to trigger an
-* interrupt when not enough packets have been received to reach the packet
-* count threshold.
-*
-* The timer is in millisecond units with +/- 33% accuracy.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The packet wait bound register contents for the DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* get the packet wait bound from the register and return it */
-
-	return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET);
-}
diff --git a/board/xilinx/common/xio.h b/board/xilinx/common/xio.h
deleted file mode 100644
index 5bb09c8..0000000
--- a/board/xilinx/common/xio.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * xio.h
- *
- * Defines XIo functions for Xilinx OCP in terms of Linux primitives
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2002 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef XIO_H
-#define XIO_H
-
-#include "xbasic_types.h"
-#include <asm/io.h>
-
-typedef u32 XIo_Address;
-
-extern inline u8
-XIo_In8(XIo_Address InAddress)
-{
-	return (u8) in_8((volatile unsigned char *) InAddress);
-}
-extern inline u16
-XIo_In16(XIo_Address InAddress)
-{
-	return (u16) in_be16((volatile unsigned short *) InAddress);
-}
-extern inline u32
-XIo_In32(XIo_Address InAddress)
-{
-	return (u32) in_be32((volatile unsigned *) InAddress);
-}
-extern inline void
-XIo_Out8(XIo_Address OutAddress, u8 Value)
-{
-	out_8((volatile unsigned char *) OutAddress, Value);
-}
-extern inline void
-XIo_Out16(XIo_Address OutAddress, u16 Value)
-{
-	out_be16((volatile unsigned short *) OutAddress, Value);
-}
-extern inline void
-XIo_Out32(XIo_Address OutAddress, u32 Value)
-{
-	out_be32((volatile unsigned *) OutAddress, Value);
-}
-
-#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
-#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
-#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
-#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
-
-#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
-#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
-#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
-#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
-
-#endif				/* XIO_H */
diff --git a/board/xilinx/common/xipif_v1_23_b.c b/board/xilinx/common/xipif_v1_23_b.c
deleted file mode 100644
index c7311ab..0000000
--- a/board/xilinx/common/xipif_v1_23_b.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
-/******************************************************************************
-*
-*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
-*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-*       FOR A PARTICULAR PURPOSE.
-*
-*       (c) Copyright 2002 Xilinx Inc.
-*       All rights reserved.
-*
-******************************************************************************/
-/******************************************************************************
-*
-* FILENAME:
-*
-* xipif.c
-*
-* DESCRIPTION:
-*
-* This file contains the implementation of the XIpIf component. The
-* XIpIf component encapsulates the IPIF, which is the standard interface
-* that IP must adhere to when connecting to a bus.  The purpose of this
-* component is to encapsulate the IPIF processing such that maintainability
-* is increased.  This component does not provide a lot of abstraction from
-* from the details of the IPIF as it is considered a building block for
-* device drivers.  A device driver designer must be familiar with the
-* details of the IPIF hardware to use this component.
-*
-* The IPIF hardware provides a building block for all hardware devices such
-* that each device does not need to reimplement these building blocks. The
-* IPIF contains other building blocks, such as FIFOs and DMA channels, which
-* are also common to many devices.  These blocks are implemented as separate
-* hardware blocks and instantiated within the IPIF.  The primary hardware of
-* the IPIF which is implemented by this software component is the interrupt
-* architecture.  Since there are many blocks of a device which may generate
-* interrupts, all the interrupt processing is contained in the common part
-* of the device, the IPIF.  This interrupt processing is for the device level
-* only and does not include any processing for the interrupt controller.
-*
-* A device is a mechanism such as an Ethernet MAC.  The device is made
-* up of several parts which include an IPIF and the IP.  The IPIF contains most
-* of the device infrastructure which is common to all devices, such as
-* interrupt processing, DMA channels, and FIFOs.  The infrastructure may also
-* be referred to as IPIF internal blocks since they are part of the IPIF and
-* are separate blocks that can be selected based upon the needs of the device.
-* The IP of the device is the logic that is unique to the device and interfaces
-* to the IPIF of the device.
-*
-* In general, there are two levels of registers within the IPIF.  The first
-* level, referred to as the device level, contains registers which are for the
-* entire device.  The second level, referred to as the IP level, contains
-* registers which are specific to the IP of the device.  The two levels of
-* registers are designed to be hierarchical such that the device level is
-* is a more general register set above the more specific registers of the IP.
-* The IP level of registers provides functionality which is typically common
-* across all devices and allows IP designers to focus on the unique aspects
-* of the IP.
-*
-* The interrupt registers of the IPIF are parameterizable such that the only
-* the number of bits necessary for the device are implemented. The functions
-* of this component do not attempt to validate that the passed in arguments are
-* valid based upon the number of implemented bits.  This is necessary to
-* maintain the level of performance required for the common components.  Bits
-* of the registers are assigned starting at the least significant bit of the
-* registers.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the IPIF.  This component
-* does not use critical sections and it does access registers using
-* read-modify-write operations.  Calls to IPIF functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Mutual Exclusion
-*
-* The functions of the IPIF are not thread safe such that the caller of all
-* functions is responsible for ensuring mutual exclusion for an IPIF.  Mutual
-* exclusion across multiple IPIF components is not necessary.
-*
-* NOTES:
-*
-* None.
-*
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.23b jhl  02/27/01 Repartioned to reduce size
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xipif_v1_23_b.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constant is used to generate bit masks for register testing
- * in the self test functions, it defines the starting bit mask that is to be
- * shifted from the LSB to MSB in creating a register test mask
- */
-#define XIIF_V123B_FIRST_BIT_MASK     1UL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XIpIf_SelfTest
-*
-* DESCRIPTION:
-*
-* This function performs a self test on the specified IPIF component.  Many
-* of the registers in the IPIF are tested to ensure proper operation.  This
-* function is destructive because the IPIF is reset at the start of the test
-* and at the end of the test to ensure predictable results.  The IPIF reset
-* also resets the entire device that uses the IPIF.  This function exits with
-* all interrupts for the device disabled.
-*
-* ARGUMENTS:
-*
-* InstancePtr points to the XIpIf to operate on.
-*
-* DeviceRegistersWidth contains the number of bits in the device interrupt
-* registers. The hardware is parameterizable such that only the number of bits
-* necessary to support a device are implemented.  This value must be between 0
-* and 32 with 0 indicating there are no device interrupt registers used.
-*
-* IpRegistersWidth contains the number of bits in the IP interrupt registers
-* of the device.  The hardware is parameterizable such that only the number of
-* bits necessary to support a device are implemented.  This value must be
-* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
-*
-* RETURN VALUE:
-*
-* A value of XST_SUCCESS indicates the test was successful with no errors.
-* Any one of the following error values may also be returned.
-*
-*   XST_IPIF_RESET_REGISTER_ERROR       The value of a register at reset was
-*                                       not valid
-*   XST_IPIF_IP_STATUS_ERROR            A write to the IP interrupt status
-*                                       register did not read back correctly
-*   XST_IPIF_IP_ACK_ERROR               One or more bits in the IP interrupt
-*                                       status register did not reset when acked
-*   XST_IPIF_IP_ENABLE_ERROR            The IP interrupt enable register
-*                                       did not read back correctly based upon
-*                                       what was written to it
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/* the following constant defines the maximum number of bits which may be
- * used in the registers at the device and IP levels, this is based upon the
- * number of bits available in the registers
- */
-#define XIIF_V123B_MAX_REG_BIT_COUNT 32
-
-XStatus
-XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
-{
-	XStatus Status;
-
-	/* assert to verify arguments are valid */
-
-	XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
-
-	/* reset the IPIF such that it's in a known state before the test
-	 * and interrupts are globally disabled
-	 */
-	XIIF_V123B_RESET(RegBaseAddress);
-
-	/* perform the self test on the IP interrupt registers, if
-	 * it is not successful exit with the status
-	 */
-	Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
-	if (Status != XST_SUCCESS) {
-		return Status;
-	}
-
-	/* reset the IPIF such that it's in a known state before exiting test */
-
-	XIIF_V123B_RESET(RegBaseAddress);
-
-	/* reaching this point means there were no errors, return success */
-
-	return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* IpIntrSelfTest
-*
-* DESCRIPTION:
-*
-* Perform a self test on the IP interrupt registers of the IPIF. This
-* function modifies registers of the IPIF such that they are not guaranteed
-* to be in the same state when it returns.  Any bits in the IP interrupt
-* status register which are set are assumed to be set by default after a reset
-* and are not tested in the test.
-*
-* ARGUMENTS:
-*
-* InstancePtr points to the XIpIf to operate on.
-*
-* IpRegistersWidth contains the number of bits in the IP interrupt registers
-* of the device.  The hardware is parameterizable such that only the number of
-* bits necessary to support a device are implemented.  This value must be
-* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if the test was successful.  Otherwise, one
-* of the following values is returned.
-*
-*   XST_IPIF_RESET_REGISTER_ERROR       The value of a register at reset was
-*                                       not valid
-*   XST_IPIF_IP_STATUS_ERROR            A write to the IP interrupt status
-*                                       register did not read back correctly
-*   XST_IPIF_IP_ACK_ERROR               One or more bits in the IP status
-*                                       register did not reset when acked
-*   XST_IPIF_IP_ENABLE_ERROR            The IP interrupt enable register
-*                                       did not read back correctly based upon
-*                                       what was written to it
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-static XStatus
-IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
-{
-	/* ensure that the IP interrupt interrupt enable register is  zero
-	 * as it should be at reset, the interrupt status is dependent upon the
-	 * IP such that it's reset value is not known
-	 */
-	if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
-		return XST_IPIF_RESET_REGISTER_ERROR;
-	}
-
-	/* if there are any used IP interrupts, then test all of the interrupt
-	 * bits in all testable registers
-	 */
-	if (IpRegistersWidth > 0) {
-		u32 BitCount;
-		u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
-		u32 Mask = XIIF_V123B_FIRST_BIT_MASK;	/* bits assigned MSB to LSB */
-		u32 InterruptStatus;
-
-		/* generate the register masks to be used for IP register tests, the
-		 * number of bits supported by the hardware is parameterizable such
-		 * that only that number of bits are implemented in the registers, the
-		 * bits are allocated starting at the MSB of the registers
-		 */
-		for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
-			Mask = Mask << 1;
-			IpInterruptMask |= Mask;
-		}
-
-		/* get the current IP interrupt status register contents, any bits
-		 * already set must default to 1 at reset in the device and these
-		 * bits can't be tested in the following test, remove these bits from
-		 * the mask that was generated for the test
-		 */
-		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
-		IpInterruptMask &= ~InterruptStatus;
-
-		/* set the bits in the device status register and verify them by reading
-		 * the register again, all bits of the register are latched
-		 */
-		XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
-		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
-		if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
-		{
-			return XST_IPIF_IP_STATUS_ERROR;
-		}
-
-		/* test to ensure that the bits set in the IP interrupt status register
-		 * can be cleared by acknowledging them in the IP interrupt status
-		 * register then read it again and verify it was cleared
-		 */
-		XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
-		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
-		if ((InterruptStatus & IpInterruptMask) != 0) {
-			return XST_IPIF_IP_ACK_ERROR;
-		}
-
-		/* set the IP interrupt enable set register and then read the IP
-		 * interrupt enable register and verify the interrupts were enabled
-		 */
-		XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
-		if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
-			return XST_IPIF_IP_ENABLE_ERROR;
-		}
-
-		/* clear the IP interrupt enable register and then read the
-		 * IP interrupt enable register and verify the interrupts were disabled
-		 */
-		XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
-		if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
-			return XST_IPIF_IP_ENABLE_ERROR;
-		}
-	}
-	return XST_SUCCESS;
-}
diff --git a/board/xilinx/common/xipif_v1_23_b.h b/board/xilinx/common/xipif_v1_23_b.h
deleted file mode 100644
index 3ce1fff..0000000
--- a/board/xilinx/common/xipif_v1_23_b.h
+++ /dev/null
@@ -1,746 +0,0 @@
-/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
-/******************************************************************************
-*
-*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
-*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-*	FOR A PARTICULAR PURPOSE.
-*
-*	(c) Copyright 2002 Xilinx Inc.
-*	All rights reserved.
-*
-******************************************************************************/
-/******************************************************************************
-*
-* FILENAME:
-*
-* xipif.h
-*
-* DESCRIPTION:
-*
-* The XIpIf component encapsulates the IPIF, which is the standard interface
-* that IP must adhere to when connecting to a bus.  The purpose of this
-* component is to encapsulate the IPIF processing such that maintainability
-* is increased.	 This component does not provide a lot of abstraction from
-* from the details of the IPIF as it is considered a building block for
-* device drivers.  A device driver designer must be familiar with the
-* details of the IPIF hardware to use this component.
-*
-* The IPIF hardware provides a building block for all hardware devices such
-* that each device does not need to reimplement these building blocks. The
-* IPIF contains other building blocks, such as FIFOs and DMA channels, which
-* are also common to many devices.  These blocks are implemented as separate
-* hardware blocks and instantiated within the IPIF.  The primary hardware of
-* the IPIF which is implemented by this software component is the interrupt
-* architecture.	 Since there are many blocks of a device which may generate
-* interrupts, all the interrupt processing is contained in the common part
-* of the device, the IPIF.  This interrupt processing is for the device level
-* only and does not include any processing for the interrupt controller.
-*
-* A device is a mechanism such as an Ethernet MAC.  The device is made
-* up of several parts which include an IPIF and the IP.	 The IPIF contains most
-* of the device infrastructure which is common to all devices, such as
-* interrupt processing, DMA channels, and FIFOs.  The infrastructure may also
-* be referred to as IPIF internal blocks since they are part of the IPIF and
-* are separate blocks that can be selected based upon the needs of the device.
-* The IP of the device is the logic that is unique to the device and interfaces
-* to the IPIF of the device.
-*
-* In general, there are two levels of registers within the IPIF.  The first
-* level, referred to as the device level, contains registers which are for the
-* entire device.  The second level, referred to as the IP level, contains
-* registers which are specific to the IP of the device.	 The two levels of
-* registers are designed to be hierarchical such that the device level is
-* is a more general register set above the more specific registers of the IP.
-* The IP level of registers provides functionality which is typically common
-* across all devices and allows IP designers to focus on the unique aspects
-* of the IP.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the IPIF.  This component
-* does not use critical sections and it does access registers using
-* read-modify-write operations.	 Calls to IPIF functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Mutual Exclusion
-*
-* The functions of the IPIF are not thread safe such that the caller of all
-* functions is responsible for ensuring mutual exclusion for an IPIF.  Mutual
-* exclusion across multiple IPIF components is not necessary.
-*
-* NOTES:
-*
-* None.
-*
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.23b jhl  02/27/01 Repartioned to minimize size
-*
-******************************************************************************/
-
-#ifndef XIPIF_H			/* prevent circular inclusions */
-#define XIPIF_H			/* by using protection macros */
-
-/***************************** Include Files *********************************/
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants define the register offsets for the registers of the
- * IPIF, there are some holes in the memory map for reserved addresses to allow
- * other registers to be added and still match the memory map of the interrupt
- * controller registers
- */
-#define XIIF_V123B_DISR_OFFSET	   0UL	/* device interrupt status register */
-#define XIIF_V123B_DIPR_OFFSET	   4UL	/* device interrupt pending register */
-#define XIIF_V123B_DIER_OFFSET	   8UL	/* device interrupt enable register */
-#define XIIF_V123B_DIIR_OFFSET	   24UL /* device interrupt ID register */
-#define XIIF_V123B_DGIER_OFFSET	   28UL /* device global interrupt enable reg */
-#define XIIF_V123B_IISR_OFFSET	   32UL /* IP interrupt status register */
-#define XIIF_V123B_IIER_OFFSET	   40UL /* IP interrupt enable register */
-#define XIIF_V123B_RESETR_OFFSET   64UL /* reset register */
-
-#define XIIF_V123B_RESET_MASK		  0xAUL
-
-/* the following constant is used for the device global interrupt enable
- * register, to enable all interrupts for the device, this is the only bit
- * in the register
- */
-#define XIIF_V123B_GINTR_ENABLE_MASK	  0x80000000UL
-
-/* the following constants contain the masks to identify each internal IPIF
- * condition in the device registers of the IPIF, interrupts are assigned
- * in the register from LSB to the MSB
- */
-#define XIIF_V123B_ERROR_MASK		  1UL	/* LSB of the register */
-
-/* The following constants contain interrupt IDs which identify each internal
- * IPIF condition, this value must correlate with the mask constant for the
- * error
- */
-#define XIIF_V123B_ERROR_INTERRUPT_ID	  0	/* interrupt bit #, (LSB = 0) */
-#define XIIF_V123B_NO_INTERRUPT_ID	  128	/* no interrupts are pending */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_RESET
-*
-* DESCRIPTION:
-*
-* Reset the IPIF component and hardware.  This is a destructive operation that
-* could cause the loss of data since resetting the IPIF of a device also
-* resets the device using the IPIF and any blocks, such as FIFOs or DMA
-* channels, within the IPIF.  All registers of the IPIF will contain their
-* reset value when this function returns.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/* the following constant is used in the reset register to cause the IPIF to
- * reset
- */
-#define XIIF_V123B_RESET(RegBaseAddress) \
-    XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_DISR
-*
-* DESCRIPTION:
-*
-* This function sets the device interrupt status register to the value.
-* This register indicates the status of interrupt sources for a device
-* which contains the IPIF.  The status is independent of whether interrupts
-* are enabled and could be used for polling a device at a higher level rather
-* than a more detailed level.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF.  With the exception of some internal IPIF
-* conditions, the contents of this register are not latched but indicate
-* the live status of the interrupt sources within the device.  Writing any of
-* the non-latched bits of the register will have no effect on the register.
-*
-* For the latched bits of this register only, setting a bit which is zero
-* within this register causes an interrupt to generated.  The device global
-* interrupt enable register and the device interrupt enable register must be set
-* appropriately to allow an interrupt to be passed out of the device. The
-* interrupt is cleared by writing to this register with the bits to be
-* cleared set to a one and all others to zero.	This register implements a
-* toggle on write functionality meaning any bits which are set in the value
-* written cause the bits in the register to change to the opposite state.
-*
-* This function writes the specified value to the register such that
-* some bits may be set and others cleared.  It is the caller's responsibility
-* to get the value of the register prior to setting the value to prevent a
-* destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Status contains the value to be written to the interrupt status register of
-* the device.  The only bits which can be written are the latched bits which
-* contain the internal IPIF conditions.	 The following values may be used to
-* set the status register or clear an interrupt condition.
-*
-*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
-    XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DISR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt status register contents.
-* This register indicates the status of interrupt sources for a device
-* which contains the IPIF.  The status is independent of whether interrupts
-* are enabled and could be used for polling a device at a higher level.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF.  With the exception of some internal IPIF
-* conditions, the contents of this register are not latched but indicate
-* the live status of the interrupt sources within the device.
-*
-* For only the latched bits of this register, the interrupt may be cleared by
-* writing to these bits in the status register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* A status which contains the value read from the interrupt status register of
-* the device. The bit definitions are specific to the device with
-* the exception of the latched internal IPIF condition bits. The following
-* values may be used to detect internal IPIF conditions in the status.
-*
-*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DISR(RegBaseAddress) \
-    XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_DIER
-*
-* DESCRIPTION:
-*
-* This function sets the device interrupt enable register contents.
-* This register controls which interrupt sources of the device are allowed to
-* generate an interrupt.  The device global interrupt enable register must also
-* be set appropriately for an interrupt to be passed out of the device.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF.  Setting a bit in this register enables that
-* interrupt source to generate an interrupt.  Clearing a bit in this register
-* disables interrupt generation for that interrupt source.
-*
-* This function writes only the specified value to the register such that
-* some interrupts source may be enabled and others disabled.  It is the
-* caller's responsibility to get the value of the interrupt enable register
-* prior to setting the value to prevent an destructive behavior.
-*
-* An interrupt source may not be enabled to generate an interrupt, but can
-* still be polled in the interrupt status register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Enable contains the value to be written to the interrupt enable register
-* of the device.  The bit definitions are specific to the device with
-* the exception of the internal IPIF conditions. The following
-* values may be used to enable the internal IPIF conditions interrupts.
-*
-*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
-*					  u32 Enable)
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
-    XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIER
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt enable register contents.
-* This register controls which interrupt sources of the device
-* are allowed to generate an interrupt.	 The device global interrupt enable
-* register and the device interrupt enable register must also be set
-* appropriately for an interrupt to be passed out of the device.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF.  Setting a bit in this register enables that
-* interrupt source to generate an interrupt if the global enable is set
-* appropriately.  Clearing a bit in this register disables interrupt generation
-* for that interrupt source regardless of the global interrupt enable.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The value read from the interrupt enable register of the device.  The bit
-* definitions are specific to the device with the exception of the internal
-* IPIF conditions. The following values may be used to determine from the
-* value if the internal IPIF conditions interrupts are enabled.
-*
-*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIER(RegBaseAddress) \
-    XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIPR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt pending register contents.
-* This register indicates the pending interrupt sources, those that are waiting
-* to be serviced by the software, for a device which contains the IPIF.
-* An interrupt must be enabled in the interrupt enable register of the IPIF to
-* be pending.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* the device which contains the IPIF.  With the exception of some internal IPIF
-* conditions, the contents of this register are not latched since the condition
-* is latched in the IP interrupt status register, by an internal block of the
-* IPIF such as a FIFO or DMA channel, or by the IP of the device.  This register
-* is read only and is not latched, but it is necessary to acknowledge (clear)
-* the interrupt condition by performing the appropriate processing for the IP
-* or block within the IPIF.
-*
-* This register can be thought of as the contents of the interrupt status
-* register ANDed with the contents of the interrupt enable register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The value read from the interrupt pending register of the device.  The bit
-* definitions are specific to the device with the exception of the latched
-* internal IPIF condition bits. The following values may be used to detect
-* internal IPIF conditions in the value.
-*
-*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
-    XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIIR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt ID for the highest priority interrupt
-* which is pending from the interrupt ID register. This function provides
-* priority resolution such that faster interrupt processing is possible.
-* Without priority resolution, it is necessary for the software to read the
-* interrupt pending register and then check each interrupt source to determine
-* if an interrupt is pending.  Priority resolution becomes more important as the
-* number of interrupt sources becomes larger.
-*
-* Interrupt priorities are based upon the bit position of the interrupt in the
-* interrupt pending register with bit 0 being the highest priority. The
-* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
-* highest priority. The interrupt ID register is live rather than latched such
-* that multiple calls to this function may not yield the same results.	A
-* special value, outside of the interrupt priority range of 0 - 31, is
-* contained in the register which indicates that no interrupt is pending.  This
-* may be useful for allowing software to continue processing interrupts in a
-* loop until there are no longer any interrupts pending.
-*
-* The interrupt ID is designed to allow a function pointer table to be used
-* in the software such that the interrupt ID is used as an index into that
-* table.  The function pointer table could contain an instance pointer, such
-* as to DMA channel, and a function pointer to the function which handles
-* that interrupt.  This design requires the interrupt processing of the device
-* driver to be partitioned into smaller more granular pieces based upon
-* hardware used by the device, such as DMA channels and FIFOs.
-*
-* It is not mandatory that this function be used by the device driver software.
-* It may choose to read the pending register and resolve the pending interrupt
-* priorities on it's own.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
-* which is pending.  A value of XIIF_NO_INTERRUPT_ID indicates that there is
-* no interrupt pending. The following values may be used to identify the
-* interrupt ID for the internal IPIF interrupts.
-*
-*   XIIF_V123B_ERROR_INTERRUPT_ID     Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
-    XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_GLOBAL_INTR_DISABLE
-*
-* DESCRIPTION:
-*
-* This function disables all interrupts for the device by writing to the global
-* interrupt enable register.  This register provides the ability to disable
-* interrupts without any modifications to the interrupt enable register such
-* that it is minimal effort to restore the interrupts to the previous enabled
-* state.  The corresponding function, XIpIf_GlobalIntrEnable, is provided to
-* restore the interrupts to the previous enabled state.	 This function is
-* designed to be used in critical sections of device drivers such that it is
-* not necessary to disable other device interrupts.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
-    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_GINTR_ENABLE
-*
-* DESCRIPTION:
-*
-* This function writes to the global interrupt enable register to enable
-* interrupts from the device.  This register provides the ability to enable
-* interrupts without any modifications to the interrupt enable register such
-* that it is minimal effort to restore the interrupts to the previous enabled
-* state.  This function does not enable individual interrupts as the interrupt
-* enable register must be set appropriately.  This function is designed to be
-* used in critical sections of device drivers such that it is not necessary to
-* disable other device interrupts.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress)		  \
-    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
-	       XIIF_V123B_GINTR_ENABLE_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_IS_GINTR_ENABLED
-*
-* DESCRIPTION:
-*
-* This function determines if interrupts are enabled at the global level by
-* reading the gloabl interrupt register. This register provides the ability to
-* disable interrupts without any modifications to the interrupt enable register
-* such that it is minimal effort to restore the interrupts to the previous
-* enabled state.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress)		\
-    (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) ==	\
-	      XIIF_V123B_GINTR_ENABLE_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_IISR
-*
-* DESCRIPTION:
-*
-* This function sets the IP interrupt status register to the specified value.
-* This register indicates the status of interrupt sources for the IP of the
-* device.  The IP is defined as the part of the device that connects to the
-* IPIF.	 The status is independent of whether interrupts are enabled such that
-* the status register may also be polled when interrupts are not enabled.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP.  All bits of this register are latched. Setting a bit which is zero
-* within this register causes an interrupt to be generated.  The device global
-* interrupt enable register and the device interrupt enable register must be set
-* appropriately to allow an interrupt to be passed out of the device. The
-* interrupt is cleared by writing to this register with the bits to be
-* cleared set to a one and all others to zero.	This register implements a
-* toggle on write functionality meaning any bits which are set in the value
-* written cause the bits in the register to change to the opposite state.
-*
-* This function writes only the specified value to the register such that
-* some status bits may be set and others cleared.  It is the caller's
-* responsibility to get the value of the register prior to setting the value
-* to prevent an destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Status contains the value to be written to the IP interrupt status
-* register.  The bit definitions are specific to the device IP.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
-    XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_IISR
-*
-* DESCRIPTION:
-*
-* This function gets the contents of the IP interrupt status register.
-* This register indicates the status of interrupt sources for the IP of the
-* device.  The IP is defined as the part of the device that connects to the
-* IPIF. The status is independent of whether interrupts are enabled such
-* that the status register may also be polled when interrupts are not enabled.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device.  All bits of this register are latched.  Writing a 1 to a bit within
-* this register causes an interrupt to be generated if enabled in the interrupt
-* enable register and the global interrupt enable is set.  Since the status is
-* latched, each status bit must be acknowledged in order for the bit in the
-* status register to be updated.  Each bit can be acknowledged by writing a
-* 0 to the bit in the status register.
-
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* A status which contains the value read from the IP interrupt status register.
-* The bit definitions are specific to the device IP.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_IISR(RegBaseAddress) \
-    XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_IIER
-*
-* DESCRIPTION:
-*
-* This function sets the IP interrupt enable register contents.	 This register
-* controls which interrupt sources of the IP are allowed to generate an
-* interrupt.  The global interrupt enable register and the device interrupt
-* enable register must also be set appropriately for an interrupt to be
-* passed out of the device containing the IPIF and the IP.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP.  Setting a bit in this register enables the interrupt source to generate
-* an interrupt.	 Clearing a bit in this register disables interrupt generation
-* for that interrupt source.
-*
-* This function writes only the specified value to the register such that
-* some interrupt sources may be enabled and others disabled.  It is the
-* caller's responsibility to get the value of the interrupt enable register
-* prior to setting the value to prevent an destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Enable contains the value to be written to the IP interrupt enable register.
-* The bit definitions are specific to the device IP.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
-    XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_IIER
-*
-* DESCRIPTION:
-*
-*
-* This function gets the IP interrupt enable register contents.	 This register
-* controls which interrupt sources of the IP are allowed to generate an
-* interrupt.  The global interrupt enable register and the device interrupt
-* enable register must also be set appropriately for an interrupt to be
-* passed out of the device containing the IPIF and the IP.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP.  Setting a bit in this register enables the interrupt source to generate
-* an interrupt.	 Clearing a bit in this register disables interrupt generation
-* for that interrupt source.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The contents read from the IP interrupt enable register.  The bit definitions
-* are specific to the device IP.
-*
-* NOTES:
-*
-* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
-*
-******************************************************************************/
-#define XIIF_V123B_READ_IIER(RegBaseAddress) \
-    XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization Functions
- */
-XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.c b/board/xilinx/common/xpacket_fifo_v1_00_b.c
deleted file mode 100644
index ae2d6d4..0000000
--- a/board/xilinx/common/xpacket_fifo_v1_00_b.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/*
-*
-* @file xpacket_fifo_v1_00_b.c
-*
-* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h
-* for more information about the component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02  First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xstatus.h"
-#include "xpacket_fifo_v1_00_b.h"
-
-/************************** Constant Definitions *****************************/
-
-/* width of a FIFO word */
-
-#define XPF_FIFO_WIDTH_BYTE_COUNT       4UL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************* Variable Definitions ******************************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/*
-*
-* This function initializes a packet FIFO.  Initialization resets the
-* FIFO such that it's empty and ready to use.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param RegBaseAddress contains the base address of the registers for
-*        the packet FIFO.
-* @param DataBaseAddress contains the base address of the data for
-*        the packet FIFO.
-*
-* @return
-*
-* Always returns XST_SUCCESS.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
-			    u32 RegBaseAddress, u32 DataBaseAddress)
-{
-	/* assert to verify input argument are valid */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-
-	/* initialize the component variables to the specified state */
-
-	InstancePtr->RegBaseAddress = RegBaseAddress;
-	InstancePtr->DataBaseAddress = DataBaseAddress;
-	InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
-	/* reset the FIFO such that it's empty and ready to use and indicate the
-	 * initialization was successful, note that the is ready variable must be
-	 * set prior to calling the reset function to prevent an assert
-	 */
-	XPF_V100B_RESET(InstancePtr);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* This function performs a self-test on the specified packet FIFO.  The self
-* test resets the FIFO and reads a register to determine if it is the correct
-* reset value.  This test is destructive in that any data in the FIFO will
-* be lost.
-*
-* @param InstancePtr is a pointer to the packet FIFO to be operated on.
-*
-* @param FifoType specifies the type of FIFO, read or write, for the self test.
-*        The FIFO type is specified by the values XPF_READ_FIFO_TYPE or
-*        XPF_WRITE_FIFO_TYPE.
-*
-* @return
-*
-* XST_SUCCESS is returned if the selftest is successful, or
-* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the
-* occupancy/vacancy count register after a reset does not match the
-* specified reset value.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType)
-{
-	u32 Register;
-
-	/* assert to verify valid input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) ||
-			(FifoType == XPF_WRITE_FIFO_TYPE));
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* reset the fifo and then check to make sure the occupancy/vacancy
-	 * register contents are correct for a reset condition
-	 */
-	XPF_V100B_RESET(InstancePtr);
-
-	Register = XIo_In32(InstancePtr->RegBaseAddress +
-			    XPF_COUNT_STATUS_REG_OFFSET);
-
-	/* check the value of the register to ensure that it's correct for the
-	 * specified FIFO type since both FIFO types reset to empty, but a bit
-	 * in the register changes definition based upon FIFO type
-	 */
-
-	if (FifoType == XPF_READ_FIFO_TYPE) {
-		/* check the regiser value for a read FIFO which should be empty */
-
-		if (Register != XPF_EMPTY_FULL_MASK) {
-			return XST_PFIFO_BAD_REG_VALUE;
-		}
-	} else {
-		/* check the register value for a write FIFO which should not be full
-		 * on reset
-		 */
-		if ((Register & XPF_EMPTY_FULL_MASK) != 0) {
-			return XST_PFIFO_BAD_REG_VALUE;
-		}
-	}
-
-	/* the test was successful */
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is
-* currently 32 bits wide such that an input buffer which is a series of bytes
-* is filled from the FIFO a word at a time. If the requested byte count is not
-* a multiple of 32 bit words, it is necessary for this function to format the
-* remaining 32 bit word from the FIFO into a series of bytes in the buffer.
-* There may be up to 3 extra bytes which must be extracted from the last word
-* of the FIFO and put into the buffer.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param BufferPtr points to the memory buffer to write the data into. This
-*        buffer must be 32 bit aligned or an alignment exception could be
-*        generated. Since this buffer is a byte buffer, the data is assumed to
-*        be endian independent.
-* @param ByteCount contains the number of bytes to read from the FIFO. This
-*        number of bytes must be present in the FIFO or an error will be
-*        returned.
-*
-* @return
-*
-* XST_SUCCESS indicates the operation was successful.  If the number of
-* bytes specified by the byte count is not present in the FIFO
-* XST_PFIFO_LACK_OF_DATA is returned.
-*
-* If the function was successful, the specified buffer is modified to contain
-* the bytes which were removed from the FIFO.
-*
-* @note
-*
-* Note that the exact number of bytes which are present in the FIFO is
-* not known by this function.  It can only check for a number of 32 bit
-* words such that if the byte count specified is incorrect, but is still
-* possible based on the number of words in the FIFO, up to 3 garbage bytes
-* may be present at the end of the buffer.
-* <br><br>
-* This function assumes that if the device consuming data from the FIFO is
-* a byte device, the order of the bytes to be consumed is from the most
-* significant byte to the least significant byte of a 32 bit word removed
-* from the FIFO.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
-		      u8 * BufferPtr, u32 ByteCount)
-{
-	u32 FifoCount;
-	u32 WordCount;
-	u32 ExtraByteCount;
-	u32 *WordBuffer = (u32 *) BufferPtr;
-
-	/* assert to verify valid input arguments including 32 bit alignment of
-	 * the buffer pointer
-	 */
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(BufferPtr != NULL);
-	XASSERT_NONVOID(((u32) BufferPtr &
-			 (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
-	XASSERT_NONVOID(ByteCount != 0);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* get the count of how many 32 bit words are in the FIFO, if there aren't
-	 * enought words to satisfy the request, return an error
-	 */
-
-	FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
-			     XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
-	if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) {
-		return XST_PFIFO_LACK_OF_DATA;
-	}
-
-	/* calculate the number of words to read from the FIFO before the word
-	 * containing the extra bytes, and calculate the number of extra bytes
-	 * the extra bytes are defined as those at the end of the buffer when
-	 * the buffer does not end on a 32 bit boundary
-	 */
-	WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
-	ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
-
-	/* Read the 32 bit words from the FIFO for all the buffer except the
-	 * last word which contains the extra bytes, the following code assumes
-	 * that the buffer is 32 bit aligned, otherwise an alignment exception could
-	 * be generated
-	 */
-	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
-		WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress);
-	}
-
-	/* if there are extra bytes to handle, read the last word from the FIFO
-	 * and insert the extra bytes into the buffer
-	 */
-	if (ExtraByteCount > 0) {
-		u32 LastWord;
-		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
-		/* get the last word from the FIFO for the extra bytes */
-
-		LastWord = XIo_In32(InstancePtr->DataBaseAddress);
-
-		/* one extra byte in the last word, put the byte into the next location
-		 * of the buffer, bytes in a word of the FIFO are ordered from most
-		 * significant byte to least
-		 */
-		if (ExtraByteCount == 1) {
-			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
-		}
-
-		/* two extra bytes in the last word, put each byte into the next two
-		 * locations of the buffer
-		 */
-		else if (ExtraByteCount == 2) {
-			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
-			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
-		}
-		/* three extra bytes in the last word, put each byte into the next three
-		 * locations of the buffer
-		 */
-		else if (ExtraByteCount == 3) {
-			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
-			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
-			ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
-		}
-	}
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide
-* such that an input buffer which is a series of bytes must be written into the
-* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is
-* necessary for this function to format the remaining bytes into a single 32
-* bit word to be inserted into the FIFO. This is necessary to avoid any
-* accesses past the end of the buffer.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param BufferPtr points to the memory buffer that data is to be read from
-*        and written into the FIFO. Since this buffer is a byte buffer, the data
-*        is assumed to be endian independent. This buffer must be 32 bit aligned
-*        or an alignment exception could be generated.
-* @param ByteCount contains the number of bytes to read from the buffer and to
-*        write to the FIFO.
-*
-* @return
-*
-* XST_SUCCESS is returned if the operation succeeded.  If there is not enough
-* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is
-* returned.
-*
-* @note
-*
-* This function assumes that if the device inserting data into the FIFO is
-* a byte device, the order of the bytes in each 32 bit word is from the most
-* significant byte to the least significant byte.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
-		       u8 * BufferPtr, u32 ByteCount)
-{
-	u32 FifoCount;
-	u32 WordCount;
-	u32 ExtraByteCount;
-	u32 *WordBuffer = (u32 *) BufferPtr;
-
-	/* assert to verify valid input arguments including 32 bit alignment of
-	 * the buffer pointer
-	 */
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(BufferPtr != NULL);
-	XASSERT_NONVOID(((u32) BufferPtr &
-			 (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
-	XASSERT_NONVOID(ByteCount != 0);
-	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
-	/* get the count of how many words may be inserted into the FIFO */
-
-	FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
-			     XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
-	/* Calculate the number of 32 bit words required to insert the specified
-	 * number of bytes in the FIFO and determine the number of extra bytes
-	 * if the buffer length is not a multiple of 32 bit words
-	 */
-
-	WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
-	ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
-
-	/* take into account the extra bytes in the total word count */
-
-	if (ExtraByteCount > 0) {
-		WordCount++;
-	}
-
-	/* if there's not enough room in the FIFO to hold the specified
-	 * number of bytes, then indicate an error,
-	 */
-	if (FifoCount < WordCount) {
-		return XST_PFIFO_NO_ROOM;
-	}
-
-	/* readjust the word count to not take into account the extra bytes */
-
-	if (ExtraByteCount > 0) {
-		WordCount--;
-	}
-
-	/* Write all the bytes of the buffer which can be written as 32 bit
-	 * words into the FIFO, waiting to handle the extra bytes seperately
-	 */
-	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
-		XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]);
-	}
-
-	/* if there are extra bytes to handle, extract them from the buffer
-	 * and create a 32 bit word and write it to the FIFO
-	 */
-	if (ExtraByteCount > 0) {
-		u32 LastWord = 0;
-		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
-		/* one extra byte in the buffer, put the byte into the last word
-		 * to be inserted into the FIFO, perform this processing inline rather
-		 * than in a loop to help performance
-		 */
-		if (ExtraByteCount == 1) {
-			LastWord = ExtraBytesBuffer[0] << 24;
-		}
-
-		/* two extra bytes in the buffer, put each byte into the last word
-		 * to be inserted into the FIFO
-		 */
-		else if (ExtraByteCount == 2) {
-			LastWord = ExtraBytesBuffer[0] << 24 |
-			    ExtraBytesBuffer[1] << 16;
-		}
-
-		/* three extra bytes in the buffer, put each byte into the last word
-		 * to be inserted into the FIFO
-		 */
-		else if (ExtraByteCount == 3) {
-			LastWord = ExtraBytesBuffer[0] << 24 |
-			    ExtraBytesBuffer[1] << 16 |
-			    ExtraBytesBuffer[2] << 8;
-		}
-
-		/* write the last 32 bit word to the FIFO and return with no errors */
-
-		XIo_Out32(InstancePtr->DataBaseAddress, LastWord);
-	}
-
-	return XST_SUCCESS;
-}
diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.h b/board/xilinx/common/xpacket_fifo_v1_00_b.h
deleted file mode 100644
index 1cda0e8..0000000
--- a/board/xilinx/common/xpacket_fifo_v1_00_b.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/*
-*
-* @file xpacket_fifo_v1_00_b.h
-*
-* This component is a common component because it's primary purpose is to
-* prevent code duplication in drivers. A driver which must handle a packet
-* FIFO uses this component rather than directly manipulating a packet FIFO.
-*
-* A FIFO is a device which has dual port memory such that one user may be
-* inserting data into the FIFO while another is consuming data from the FIFO.
-* A packet FIFO is designed for use with packet protocols such as Ethernet and
-* ATM.  It is typically only used with devices when DMA and/or Scatter Gather
-* is used.  It differs from a nonpacket FIFO in that it does not provide any
-* interrupts for thresholds of the FIFO such that it is less useful without
-* DMA.
-*
-* @note
-*
-* This component has the capability to generate an interrupt when an error
-* condition occurs.  It is the user's responsibility to provide the interrupt
-* processing to handle the interrupt. This component provides the ability to
-* determine if that interrupt is active, a deadlock condition, and the ability
-* to reset the FIFO to clear the condition. In this condition, the device which
-* is using the FIFO should also be reset to prevent other problems. This error
-* condition could occur as a normal part of operation if the size of the FIFO
-* is not setup correctly.  See the hardware IP specification for more details.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02  First release
-* </pre>
-*
-*****************************************************************************/
-#ifndef XPACKET_FIFO_H		/* prevent circular inclusions */
-#define XPACKET_FIFO_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * These constants specify the FIFO type and are mutually exclusive
- */
-#define XPF_READ_FIFO_TYPE      0	/* a read FIFO */
-#define XPF_WRITE_FIFO_TYPE     1	/* a write FIFO */
-
-/*
- * These constants define the offsets to each of the registers from the
- * register base address, each of the constants are a number of bytes
- */
-#define XPF_RESET_REG_OFFSET            0UL
-#define XPF_MODULE_INFO_REG_OFFSET      0UL
-#define XPF_COUNT_STATUS_REG_OFFSET     4UL
-
-/*
- * This constant is used with the Reset Register
- */
-#define XPF_RESET_FIFO_MASK             0x0000000A
-
-/*
- * These constants are used with the Occupancy/Vacancy Count Register. This
- * register also contains FIFO status
- */
-#define XPF_COUNT_MASK                  0x0000FFFF
-#define XPF_DEADLOCK_MASK               0x20000000
-#define XPF_ALMOST_EMPTY_FULL_MASK      0x40000000
-#define XPF_EMPTY_FULL_MASK             0x80000000
-
-/**************************** Type Definitions *******************************/
-
-/*
- * The XPacketFifo driver instance data. The driver is required to allocate a
- * variable of this type for every packet FIFO in the device.
- */
-typedef struct {
-	u32 RegBaseAddress;	/* Base address of registers */
-	u32 IsReady;		/* Device is initialized and ready */
-	u32 DataBaseAddress;	/* Base address of data for FIFOs */
-} XPacketFifoV100b;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/*
-*
-* Reset the specified packet FIFO.  Resetting a FIFO will cause any data
-* contained in the FIFO to be lost.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_RESET(InstancePtr) \
-    XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK);
-
-/*****************************************************************************/
-/*
-*
-* Get the occupancy count for a read packet FIFO and the vacancy count for a
-* write packet FIFO. These counts indicate the number of 32-bit words
-* contained (occupancy) in the FIFO or the number of 32-bit words available
-* to write (vacancy) in the FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* The occupancy or vacancy count for the specified packet FIFO.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_GET_COUNT(InstancePtr) \
-    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
-    XPF_COUNT_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is almost empty. Almost empty is
-* defined for a read FIFO when there is only one data word in the FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is almost empty, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \
-    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
-    XPF_ALMOST_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is almost full. Almost full is
-* defined for a write FIFO when there is only one available data word in the
-* FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is almost full, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \
-    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
-    XPF_ALMOST_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is empty. This applies only to a
-* read FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is empty, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_EMPTY(InstancePtr) \
-    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
-    XPF_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is full. This applies only to a
-* write FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is full, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_FULL(InstancePtr) \
-    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
-    XPF_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is deadlocked.  This condition occurs
-* when the FIFO is full and empty at the same time and is caused by a packet
-* being written to the FIFO which exceeds the total data capacity of the FIFO.
-* It occurs because of the mark/restore features of the packet FIFO which allow
-* retransmission of a packet. The software should reset the FIFO and any devices
-* using the FIFO when this condition occurs.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is deadlocked, FALSE otherwise.
-*
-* @note
-*
-* This component has the capability to generate an interrupt when an error
-* condition occurs.  It is the user's responsibility to provide the interrupt
-* processing to handle the interrupt. This function provides the ability to
-* determine if a deadlock condition, and the ability to reset the FIFO to
-* clear the condition.
-*
-* In this condition, the device which is using the FIFO should also be reset
-* to prevent other problems. This error condition could occur as a normal part
-* of operation if the size of the FIFO is not setup correctly.
-*
-* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \
-    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
-    XPF_DEADLOCK_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/* Standard functions */
-
-XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
-				    u32 RegBaseAddress, u32 DataBaseAddress);
-XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType);
-
-/* Data functions */
-
-XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
-			      u8 * ReadBufferPtr, u32 ByteCount);
-XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
-			       u8 * WriteBufferPtr, u32 ByteCount);
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xstatus.h b/board/xilinx/common/xstatus.h
deleted file mode 100644
index ffda4d7..0000000
--- a/board/xilinx/common/xstatus.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* This file contains Xilinx software status codes.  Status codes have their
-* own data type called XStatus.  These codes are used throughout the Xilinx
-* device drivers.
-*
-******************************************************************************/
-
-#ifndef XSTATUS_H		/* prevent circular inclusions */
-#define XSTATUS_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-
-#define XST_SUCCESS                     0L
-#define XST_FAILURE                     1L
-#define XST_DEVICE_NOT_FOUND            2L
-#define XST_DEVICE_BLOCK_NOT_FOUND      3L
-#define XST_INVALID_VERSION             4L
-#define XST_DEVICE_IS_STARTED           5L
-#define XST_DEVICE_IS_STOPPED           6L
-#define XST_FIFO_ERROR                  7L	/* an error occurred during an
-						   operation with a FIFO such as
-						   an underrun or overrun, this
-						   error requires the device to
-						   be reset */
-#define XST_RESET_ERROR                 8L	/* an error occurred which requires
-						   the device to be reset */
-#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
-						   typically requires the device
-						   using the DMA to be reset */
-#define XST_NOT_POLLED                  10L	/* the device is not configured for
-						   polled mode operation */
-#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
-						   the specified data into */
-#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
-						   to hold the expected data */
-#define XST_NO_DATA                     13L	/* there was no data available */
-#define XST_REGISTER_ERROR              14L	/* a register did not contain the
-						   expected value */
-#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
-						   into the function */
-#define XST_NOT_SGDMA                   16L	/* the device is not configured for
-						   scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
-#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
-						 * registered */
-#define XST_NO_FEATURE                  19L	/* device is not configured with
-						 * the requested feature */
-#define XST_NOT_INTERRUPT               20L	/* device is not configured for
-						 * interrupt mode operation */
-#define XST_DEVICE_BUSY                 21L	/* device is busy */
-#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
-						 * have maxed out */
-#define XST_IS_STARTED                  23L	/* used when part of device is
-						 * already started i.e.
-						 * sub channel */
-#define XST_IS_STOPPED                  24L	/* used when part of device is
-						 * already stopped i.e.
-						 * sub channel */
-
-/***************** Utility Component statuses 401 - 500  *********************/
-
-#define XST_MEMTEST_FAILED              401L	/* memory test failed */
-
-/***************** Common Components statuses 501 - 1000 *********************/
-
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
-#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
-#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
-						   was invalid after reset */
-
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
-						   failed */
-#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
-						   was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
-						   no buffer descriptors ready
-						   to be processed */
-#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
-#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
-						   the scatter gather list are
-						   being used */
-#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
-						   descriptor which is to be
-						   copied over in the scatter
-						   list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
-						   put into the scatter gather
-						   list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
-						   specified was larger than the
-						   total # of buffer descriptors
-						   in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
-						   already been created */
-#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
-						   been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
-						   being started was not committed
-						   to the list */
-#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
-						   has already been used by the
-						   hardware so it can't be reused
-						 */
-
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
-						   was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
-						   reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
-						   register did not reset when
-						   acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
-						   register was not updated when
-						   other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
-						   status register did not read
-						   back correctly */
-#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
-						   did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
-						   not updated correctly when other
-						   registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
-						   register did not indicate the
-						   expected value */
-#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
-						   did not indicate the expected
-						   value */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
-						 * to hold the minimum number of
-						 * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
-#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Adapter is out of buffers */
-#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid adapter init string */
-#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
-						 * collision on polled send */
-
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR         1051L
-#define XST_UART_START_ERROR        1052L
-#define XST_UART_CONFIG_ERROR       1053L
-#define XST_UART_TEST_FAIL          1054L
-#define XST_UART_BAUD_ERROR         1055L
-#define XST_UART_BAUD_RANGE         1056L
-
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
-#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
-#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
-					     /* general call address        */
-#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
-					     /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
-					     /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
-					     /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
-					     /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
-					     /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
-					     /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
-					     /* didn't return written value */
-#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
-
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
-						   controller hit the max value
-						   which requires the statistics
-						   to be cleared */
-
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming */
-#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
-#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
-						   error. Use XFlash_DeviceControl
-						   to retrieve device specific codes */
-#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state */
-#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state */
-#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
-						   driver */
-#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
-						   aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
-						   addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
-						   write/erase function with
-						   XFL_NON_BLOCKING_WRITE/ERASE
-						   option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
-
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
-#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
-#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
-						 * selected */
-#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only */
-#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
-
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
-						 * one master assigned to two or more
-						 * priorities, or one master not
-						 * assigned to any priority
-						 */
-#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
-						 * priority levels without first
-						 * suspending the use of priority
-						 * levels
-						 */
-#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
-						 * bus parking was not enabled
-						 */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
-						 * priority mode to allow the
-						 * priorities to be changed
-						 */
-
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
-#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
-
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
-
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED      1251L
-
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST    1276L
-
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST   1301L
-
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST   1326L
-
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
-
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS     1361L
-
-/**************************** Type Definitions *******************************/
-
-/**
- * The status typedef.
- */
-typedef u32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xversion.c b/board/xilinx/common/xversion.c
deleted file mode 100644
index c8a6915..0000000
--- a/board/xilinx/common/xversion.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* This file contains the implementation of the XVersion component. This
-* component represents a version ID.  It is encapsulated within a component
-* so that it's type and implementation can change without affecting users of
-* it.
-*
-* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
-* X is the major revision, YY is the minor revision, and Z is the
-* compatability revision.
-*
-* Packed versions are also utilized for the configuration ROM such that
-* memory is minimized. A packed version consumes only 16 bits and is
-* formatted as follows.
-*
-* <pre>
-* Revision                  Range       Bit Positions
-*
-* Major Revision            0 - 9       Bits 15 - 12
-* Minor Revision            0 - 99      Bits 11 - 5
-* Compatability Revision    a - z       Bits 4 - 0
-</pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants define the masks and shift values to allow the
- * revisions to be packed and unpacked, a packed version is packed into a 16
- * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
- * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
- * revision
- */
-#define XVE_MAJOR_SHIFT_VALUE       12
-#define XVE_MINOR_ONLY_MASK         0x0FE0
-#define XVE_MINOR_SHIFT_VALUE       5
-#define XVE_COMP_ONLY_MASK          0x001F
-
-/* the following constants define the specific characters of a version string
- * for each character of the revision, a version string is in the following
- * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
- * revision (00 - 99), and Z is the compatability revision (a - z)
- */
-#define XVE_MAJOR_CHAR      0	/* major revision 0 - 9 */
-#define XVE_MINOR_TENS_CHAR 2	/* minor revision tens 0 - 9 */
-#define XVE_MINOR_ONES_CHAR 3	/* minor revision ones 0 - 9 */
-#define XVE_COMP_CHAR       4	/* compatability revision a - z */
-#define XVE_END_STRING_CHAR 5
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static u32 IsVersionStringValid(s8 * StringPtr);
-
-/*****************************************************************************
-*
-* Unpacks a packed version into the specified version. Versions are packed
-* into the configuration ROM to reduce the amount storage. A packed version
-* is a binary format as oppossed to a non-packed version which is implemented
-* as a string.
-*
-* @param    InstancePtr points to the version to unpack the packed version into.
-* @param    PackedVersion contains the packed version to unpack.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion)
-{
-	/* not implemented yet since CROM related */
-}
-
-/*****************************************************************************
-*
-* Packs a version into the specified packed version. Versions are packed into
-* the configuration ROM to reduce the amount storage.
-*
-* @param    InstancePtr points to the version to pack.
-* @param    PackedVersionPtr points to the packed version which will receive
-*           the new packed version.
-*
-* @return
-*
-* A status, XST_SUCCESS, indicating the packing was accomplished
-* successfully, or an error, XST_INVALID_VERSION, indicating the specified
-* input version was not valid such that the pack did not occur
-* <br><br>
-* The packed version pointed to by PackedVersionPtr is modified with the new
-* packed version if the status indicates success.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr)
-{
-	/* not implemented yet since CROM related */
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************
-*
-* Determines if two versions are equal.
-*
-* @param    InstancePtr points to the first version to be compared.
-* @param    VersionPtr points to a second version to be compared.
-*
-* @return
-*
-* TRUE if the versions are equal, FALSE otherwise.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-u32
-XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr)
-{
-	u8 *Version1 = (u8 *) InstancePtr;
-	u8 *Version2 = (u8 *) VersionPtr;
-	int Index;
-
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(VersionPtr != NULL);
-
-	/* check each byte of the versions to see if they are the same,
-	 * return at any point a byte differs between them
-	 */
-	for (Index = 0; Index < sizeof (XVersion); Index++) {
-		if (Version1[Index] != Version2[Index]) {
-			return FALSE;
-		}
-	}
-
-	/* No byte was found to be different between the versions, so indicate
-	 * the versions are equal
-	 */
-	return TRUE;
-}
-
-/*****************************************************************************
-*
-* Converts a version to a null terminated string.
-*
-* @param    InstancePtr points to the version to convert.
-* @param    StringPtr points to the string which will be the result of the
-*           conversion. This does not need to point to a null terminated
-*           string as an input, but must point to storage which is an adequate
-*           amount to hold the result string.
-*
-* @return
-*
-* The null terminated string is inserted at the location pointed to by
-* StringPtr if the status indicates success.
-*
-* @note
-*
-* It is necessary for the caller to have already allocated the storage to
-* contain the string.  The amount of memory necessary for the string is
-* specified in the version header file.
-*
-******************************************************************************/
-void
-XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(StringPtr != NULL);
-
-	/* since version is implemented as a string, just copy the specified
-	 * input into the specified output
-	 */
-	XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
-}
-
-/*****************************************************************************
-*
-* Initializes a version from a null terminated string. Since the string may not
-* be a format which is compatible with the version, an error could occur.
-*
-* @param    InstancePtr points to the version which is to be initialized.
-* @param    StringPtr points to a null terminated string which will be
-*           converted to a version.  The format of the string must match the
-*           version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
-*           Z = a - z.
-*
-* @return
-*
-* A status, XST_SUCCESS, indicating the conversion was accomplished
-* successfully, or XST_INVALID_VERSION indicating the version string format
-* was not valid.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr)
-{
-	/* assert to verify input arguments */
-
-	XASSERT_NONVOID(InstancePtr != NULL);
-	XASSERT_NONVOID(StringPtr != NULL);
-
-	/* if the version string specified is not valid, return an error */
-
-	if (!IsVersionStringValid(StringPtr)) {
-		return XST_INVALID_VERSION;
-	}
-
-	/* copy the specified string into the specified version and indicate the
-	 * conversion was successful
-	 */
-	XVersion_Copy((XVersion *) StringPtr, InstancePtr);
-
-	return XST_SUCCESS;
-}
-
-/*****************************************************************************
-*
-* Copies the contents of a version to another version.
-*
-* @param    InstancePtr points to the version which is the source of data for
-*           the copy operation.
-* @param    VersionPtr points to another version which is the destination of
-*           the copy operation.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr)
-{
-	u8 *Source = (u8 *) InstancePtr;
-	u8 *Destination = (u8 *) VersionPtr;
-	int Index;
-
-	/* assert to verify input arguments */
-
-	XASSERT_VOID(InstancePtr != NULL);
-	XASSERT_VOID(VersionPtr != NULL);
-
-	/* copy each byte of the source version to the destination version */
-
-	for (Index = 0; Index < sizeof (XVersion); Index++) {
-		Destination[Index] = Source[Index];
-	}
-}
-
-/*****************************************************************************
-*
-* Determines if the specified version is valid.
-*
-* @param    StringPtr points to the string to be validated.
-*
-* @return
-*
-* TRUE if the version string is a valid format, FALSE otherwise.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static u32
-IsVersionStringValid(s8 * StringPtr)
-{
-	/* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
-	 * YY = 00 - 99, and Z = a - z, then indicate it's not valid
-	 */
-	if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
-	    (StringPtr[XVE_MAJOR_CHAR] > '9') ||
-	    (StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
-	    (StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
-	    (StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
-	    (StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
-	    (StringPtr[XVE_COMP_CHAR] < 'a') ||
-	    (StringPtr[XVE_COMP_CHAR] > 'z')) {
-		return FALSE;
-	}
-
-	return TRUE;
-}
diff --git a/board/xilinx/common/xversion.h b/board/xilinx/common/xversion.h
deleted file mode 100644
index 17f9da7..0000000
--- a/board/xilinx/common/xversion.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* This file contains the interface for the XVersion component. This
-* component represents a version ID.  It is encapsulated within a component
-* so that it's type and implementation can change without affecting users of
-* it.
-*
-* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
-* X is the major revision, YY is the minor revision, and Z is the
-* compatability revision.
-*
-* Packed versions are also utilized for the configuration ROM such that
-* memory is minimized. A packed version consumes only 16 bits and is
-* formatted as follows.
-*
-* <pre>
-* Revision                  Range       Bit Positions
-*
-* Major Revision            0 - 9       Bits 15 - 12
-* Minor Revision            0 - 99      Bits 11 - 5
-* Compatability Revision    a - z       Bits 4 - 0
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XVERSION_H		/* prevent circular inclusions */
-#define XVERSION_H		/* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-typedef s8 XVersion[6];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion);
-
-XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion);
-
-u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr);
-
-void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr);
-
-XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr);
-
-void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr);
-
-#endif				/* end of protection macro */
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index b75e62c..70f94c1 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -53,29 +53,9 @@ int gpio_init (void)
 	return 0;
 }
 
-#ifdef CONFIG_SYS_FSL_2
-void fsl_isr2 (void *arg) {
-	volatile int num;
-	*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) =
-	    ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)));
-	GET (num, 2);
-	NGET (num, 2);
-	puts("*");
-}
-
-int fsl_init2 (void) {
-	puts("fsl_init2\n");
-	install_interrupt_handler (FSL_INTR_2, fsl_isr2, NULL);
-	return 0;
-}
-#endif
-
 void board_init(void)
 {
 	gpio_init();
-#ifdef CONFIG_SYS_FSL_2
-	fsl_init2();
-#endif
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/xilinx/xilinx_iic/xiic_l.c b/board/xilinx/xilinx_iic/xiic_l.c
deleted file mode 100644
index 6b78163..0000000
--- a/board/xilinx/xilinx_iic/xiic_l.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
-/******************************************************************************
-*
-*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
-*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-*	FOR A PARTICULAR PURPOSE.
-*
-*	(c) Copyright 2002 Xilinx Inc.
-*	All rights reserved.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiic_l.c
-*
-* This file contains low-level driver functions that can be used to access the
-* device.  The user should refer to the hardware device specification for more
-* details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- --- -------  -----------------------------------------------
-* 1.01b jhl 5/13/02  First release
-* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
-*		     interrupt status mask was not being done in the loop such
-*		     that a read would sometimes fail on the last byte because
-*		     the transmit error which should have been ignored was
-*		     being used.  This would leave an extra byte in the FIFO
-*		     and the bus throttled such that the next operation would
-*		     also fail.	 Also updated the receive function to not
-*		     disable the device after the last byte until after the
-*		     bus transitions to not busy which is more consistent
-*		     with the expected behavior.
-* 1.01c ecm 12/05/02 new rev
-* </pre>
-*
-****************************************************************************/
-
-/***************************** Include Files *******************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xipif_v1_23_b.h"
-#include "xiic_l.h"
-
-/************************** Constant Definitions ***************************/
-
-/**************************** Type Definitions *****************************/
-
-
-/***************** Macros (Inline Functions) Definitions *******************/
-
-
-/******************************************************************************
-*
-* This macro clears the specified interrupt in the IPIF interrupt status
-* register.  It is non-destructive in that the register is read and only the
-* interrupt specified is cleared.  Clearing an interrupt acknowledges it.
-*
-* @param    BaseAddress contains the IPIF registers base address.
-*
-* @param    InterruptMask contains the interrupts to be disabled
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XIic_mClearIisr(u32 BaseAddress,
-*				  u32 InterruptMask);
-*
-******************************************************************************/
-#define XIic_mClearIisr(BaseAddress, InterruptMask)		    \
-    XIIF_V123B_WRITE_IISR((BaseAddress),			    \
-	XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
-
-/******************************************************************************
-*
-* This macro sends the address for a 7 bit address during both read and write
-* operations. It takes care of the details to format the address correctly.
-* This macro is designed to be called internally to the drivers.
-*
-* @param    SlaveAddress contains the address of the slave to send to.
-*
-* @param    Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
-*
-******************************************************************************/
-#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation)	    \
-{									    \
-    u8 LocalAddr = (u8)(SlaveAddress << 1);			    \
-    LocalAddr = (LocalAddr & 0xFE) | (Operation);			    \
-    XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr);		    \
-}
-
-/************************** Function Prototypes ****************************/
-
-static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr,
-			  unsigned ByteCount);
-static unsigned SendData (u32 BaseAddress, u8 * BufferPtr,
-			  unsigned ByteCount);
-
-/************************** Variable Definitions **************************/
-
-
-/****************************************************************************/
-/**
-* Receive data as a master on the IIC bus.  This function receives the data
-* using polled I/O and blocks until the data has been received.	 It only
-* supports 7 bit addressing and non-repeated start modes of operation.	The
-* user is responsible for ensuring the bus is not busy if multiple masters
-* are present on the bus.
-*
-* @param    BaseAddress contains the base address of the IIC device.
-* @param    Address contains the 7 bit IIC address of the device to send the
-*	    specified data to.
-* @param    BufferPtr points to the data to be sent.
-* @param    ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes received.
-*
-* @note
-*
-* None
-*
-******************************************************************************/
-unsigned XIic_Recv (u32 BaseAddress, u8 Address,
-		    u8 * BufferPtr, unsigned ByteCount)
-{
-	u8 CntlReg;
-	unsigned RemainingByteCount;
-
-	/* Tx error is enabled incase the address (7 or 10) has no device to answer
-	 * with Ack. When only one byte of data, must set NO ACK before address goes
-	 * out therefore Tx error must not be enabled as it will go off immediately
-	 * and the Rx full interrupt will be checked.  If full, then the one byte
-	 * was received and the Tx error will be disabled without sending an error
-	 * callback msg.
-	 */
-	XIic_mClearIisr (BaseAddress,
-			 XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
-			 XIIC_INTR_ARB_LOST_MASK);
-
-	/* Set receive FIFO occupancy depth for 1 byte (zero based)
-	 */
-	XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0);
-
-	/* 7 bit slave address, send the address for a read operation
-	 * and set the state to indicate the address has been sent
-	 */
-	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION);
-
-	/* MSMS gets set after putting data in FIFO. Start the master receive
-	 * operation by setting CR Bits MSMS to Master, if the buffer is only one
-	 * byte, then it should not be acknowledged to indicate the end of data
-	 */
-	CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
-	if (ByteCount == 1) {
-		CntlReg |= XIIC_CR_NO_ACK_MASK;
-	}
-
-	/* Write out the control register to start receiving data and call the
-	 * function to receive each byte into the buffer
-	 */
-	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
-
-	/* Clear the latched interrupt status for the bus not busy bit which must
-	 * be done while the bus is busy
-	 */
-	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
-
-	/* Try to receive the data from the IIC bus */
-
-	RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount);
-	/*
-	 * The receive is complete, disable the IIC device and return the number of
-	 * bytes that was received
-	 */
-	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
-
-	/* Return the number of bytes that was received */
-
-	return ByteCount - RemainingByteCount;
-}
-
-/******************************************************************************
-*
-* Receive the specified data from the device that has been previously addressed
-* on the IIC bus.  This function assumes that the 7 bit address has been sent
-* and it should wait for the transmit of the address to complete.
-*
-* @param    BaseAddress contains the base address of the IIC device.
-* @param    BufferPtr points to the buffer to hold the data that is received.
-* @param    ByteCount is the number of bytes to be received.
-*
-* @return
-*
-* The number of bytes remaining to be received.
-*
-* @note
-*
-* This function does not take advantage of the receive FIFO because it is
-* designed for minimal code space and complexity.  It contains loops that
-* that could cause the function not to return if the hardware is not working.
-*
-* This function assumes that the calling function will disable the IIC device
-* after this function returns.
-*
-******************************************************************************/
-static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
-{
-	u8 CntlReg;
-	u32 IntrStatusMask;
-	u32 IntrStatus;
-
-	/* Attempt to receive the specified number of bytes on the IIC bus */
-
-	while (ByteCount > 0) {
-		/* Setup the mask to use for checking errors because when receiving one
-		 * byte OR the last byte of a multibyte message an error naturally
-		 * occurs when the no ack is done to tell the slave the last byte
-		 */
-		if (ByteCount == 1) {
-			IntrStatusMask =
-				XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
-		} else {
-			IntrStatusMask =
-				XIIC_INTR_ARB_LOST_MASK |
-				XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
-		}
-
-		/* Wait for the previous transmit and the 1st receive to complete
-		 * by checking the interrupt status register of the IPIF
-		 */
-		while (1) {
-			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
-			if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
-				break;
-			}
-			/* Check the transmit error after the receive full because when
-			 * sending only one byte transmit error will occur because of the
-			 * no ack to indicate the end of the data
-			 */
-			if (IntrStatus & IntrStatusMask) {
-				return ByteCount;
-			}
-		}
-
-		CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);
-
-		/* Special conditions exist for the last two bytes so check for them
-		 * Note that the control register must be setup for these conditions
-		 * before the data byte which was already received is read from the
-		 * receive FIFO (while the bus is throttled
-		 */
-		if (ByteCount == 1) {
-			/* For the last data byte, it has already been read and no ack
-			 * has been done, so clear MSMS while leaving the device enabled
-			 * so it can get off the IIC bus appropriately with a stop.
-			 */
-			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
-				  XIIC_CR_ENABLE_DEVICE_MASK);
-		}
-
-		/* Before the last byte is received, set NOACK to tell the slave IIC
-		 * device that it is the end, this must be done before reading the byte
-		 * from the FIFO
-		 */
-		if (ByteCount == 2) {
-			/* Write control reg with NO ACK allowing last byte to
-			 * have the No ack set to indicate to slave last byte read.
-			 */
-			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
-				  CntlReg | XIIC_CR_NO_ACK_MASK);
-		}
-
-		/* Read in data from the FIFO and unthrottle the bus such that the
-		 * next byte is read from the IIC bus
-		 */
-		*BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);
-
-		/* Clear the latched interrupt status so that it will be updated with
-		 * the new state when it changes, this must be done after the receive
-		 * register is read
-		 */
-		XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |
-				 XIIC_INTR_TX_ERROR_MASK |
-				 XIIC_INTR_ARB_LOST_MASK);
-		ByteCount--;
-	}
-
-	/* Wait for the bus to transition to not busy before returning, the IIC
-	 * device cannot be disabled until this occurs.	 It should transition as
-	 * the MSMS bit of the control register was cleared before the last byte
-	 * was read from the FIFO.
-	 */
-	while (1) {
-		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
-			break;
-		}
-	}
-
-	return ByteCount;
-}
-
-/****************************************************************************/
-/**
-* Send data as a master on the IIC bus.	 This function sends the data
-* using polled I/O and blocks until the data has been sent.  It only supports
-* 7 bit addressing and non-repeated start modes of operation.  The user is
-* responsible for ensuring the bus is not busy if multiple masters are present
-* on the bus.
-*
-* @param    BaseAddress contains the base address of the IIC device.
-* @param    Address contains the 7 bit IIC address of the device to send the
-*	    specified data to.
-* @param    BufferPtr points to the data to be sent.
-* @param    ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes sent.
-*
-* @note
-*
-* None
-*
-******************************************************************************/
-unsigned XIic_Send (u32 BaseAddress, u8 Address,
-		    u8 * BufferPtr, unsigned ByteCount)
-{
-	unsigned RemainingByteCount;
-
-	/* Put the address into the FIFO to be sent and indicate that the operation
-	 * to be performed on the bus is a write operation
-	 */
-	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);
-
-	/* Clear the latched interrupt status so that it will be updated with the
-	 * new state when it changes, this must be done after the address is put
-	 * in the FIFO
-	 */
-	XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
-			 XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
-
-	/* MSMS must be set after putting data into transmit FIFO, indicate the
-	 * direction is transmit, this device is master and enable the IIC device
-	 */
-	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
-		  XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
-		  XIIC_CR_ENABLE_DEVICE_MASK);
-
-	/* Clear the latched interrupt
-	 * status for the bus not busy bit which must be done while the bus is busy
-	 */
-	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
-
-	/* Send the specified data to the device on the IIC bus specified by the
-	 * the address
-	 */
-	RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);
-
-	/*
-	 * The send is complete, disable the IIC device and return the number of
-	 * bytes that was sent
-	 */
-	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
-
-	return ByteCount - RemainingByteCount;
-}
-
-/******************************************************************************
-*
-* Send the specified buffer to the device that has been previously addressed
-* on the IIC bus.  This function assumes that the 7 bit address has been sent
-* and it should wait for the transmit of the address to complete.
-*
-* @param    BaseAddress contains the base address of the IIC device.
-* @param    BufferPtr points to the data to be sent.
-* @param    ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes remaining to be sent.
-*
-* @note
-*
-* This function does not take advantage of the transmit FIFO because it is
-* designed for minimal code space and complexity.  It contains loops that
-* that could cause the function not to return if the hardware is not working.
-*
-******************************************************************************/
-static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
-{
-	u32 IntrStatus;
-
-	/* Send the specified number of bytes in the specified buffer by polling
-	 * the device registers and blocking until complete
-	 */
-	while (ByteCount > 0) {
-		/* Wait for the transmit to be empty before sending any more data
-		 * by polling the interrupt status register
-		 */
-		while (1) {
-			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
-
-			if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
-					  XIIC_INTR_ARB_LOST_MASK |
-					  XIIC_INTR_BNB_MASK)) {
-				return ByteCount;
-			}
-
-			if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
-				break;
-			}
-		}
-		/* If there is more than one byte to send then put the next byte to send
-		 * into the transmit FIFO
-		 */
-		if (ByteCount > 1) {
-			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
-				  *BufferPtr++);
-		} else {
-			/* Set the stop condition before sending the last byte of data so that
-			 * the stop condition will be generated immediately following the data
-			 * This is done by clearing the MSMS bit in the control register.
-			 */
-			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
-				  XIIC_CR_ENABLE_DEVICE_MASK |
-				  XIIC_CR_DIR_IS_TX_MASK);
-
-			/* Put the last byte to send in the transmit FIFO */
-
-			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
-				  *BufferPtr++);
-		}
-
-		/* Clear the latched interrupt status register and this must be done after
-		 * the transmit FIFO has been written to or it won't clear
-		 */
-		XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
-
-		/* Update the byte count to reflect the byte sent and clear the latched
-		 * interrupt status so it will be updated for the new state
-		 */
-		ByteCount--;
-	}
-
-	/* Wait for the bus to transition to not busy before returning, the IIC
-	 * device cannot be disabled until this occurs.
-	 * Note that this is different from a receive operation because the stop
-	 * condition causes the bus to go not busy.
-	 */
-	while (1) {
-		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
-			break;
-		}
-	}
-
-	return ByteCount;
-}
diff --git a/board/xilinx/xilinx_iic/xiic_l.h b/board/xilinx/xilinx_iic/xiic_l.h
deleted file mode 100644
index a2c4c49..0000000
--- a/board/xilinx/xilinx_iic/xiic_l.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
-/*****************************************************************************
-*
-*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
-*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-*	FOR A PARTICULAR PURPOSE.
-*
-*	(c) Copyright 2002 Xilinx Inc.
-*	All rights reserved.
-*
-*****************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xiic_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device.  High-level driver functions
-* are defined in xiic.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  05/07/02 First release
-* 1.01c ecm  12/05/02 new rev
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XIIC_L_H /* prevent circular inclusions */
-#define XIIC_L_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions ****************************/
-
-#define XIIC_MSB_OFFSET		       3
-
-#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
-
-/*
- * Register offsets in bytes from RegisterBase. Three is added to the
- * base offset to access LSB (IBM style) of the word
- */
-#define XIIC_CR_REG_OFFSET   0x00+XIIC_REG_OFFSET   /* Control Register	  */
-#define XIIC_SR_REG_OFFSET   0x04+XIIC_REG_OFFSET   /* Status Register	  */
-#define XIIC_DTR_REG_OFFSET  0x08+XIIC_REG_OFFSET   /* Data Tx Register	  */
-#define XIIC_DRR_REG_OFFSET  0x0C+XIIC_REG_OFFSET   /* Data Rx Register	  */
-#define XIIC_ADR_REG_OFFSET  0x10+XIIC_REG_OFFSET   /* Address Register	  */
-#define XIIC_TFO_REG_OFFSET  0x14+XIIC_REG_OFFSET   /* Tx FIFO Occupancy  */
-#define XIIC_RFO_REG_OFFSET  0x18+XIIC_REG_OFFSET   /* Rx FIFO Occupancy  */
-#define XIIC_TBA_REG_OFFSET  0x1C+XIIC_REG_OFFSET   /* 10 Bit Address reg */
-#define XIIC_RFD_REG_OFFSET  0x20+XIIC_REG_OFFSET   /* Rx FIFO Depth reg  */
-
-/* Control Register masks */
-
-#define XIIC_CR_ENABLE_DEVICE_MASK	  0x01	/* Device enable = 1	  */
-#define XIIC_CR_TX_FIFO_RESET_MASK	  0x02	/* Transmit FIFO reset=1  */
-#define XIIC_CR_MSMS_MASK		  0x04	/* Master starts Txing=1  */
-#define XIIC_CR_DIR_IS_TX_MASK		  0x08	/* Dir of tx. Txing=1	  */
-#define XIIC_CR_NO_ACK_MASK		  0x10	/* Tx Ack. NO ack = 1	  */
-#define XIIC_CR_REPEATED_START_MASK	  0x20	/* Repeated start = 1	  */
-#define XIIC_CR_GENERAL_CALL_MASK	  0x40	/* Gen Call enabled = 1	  */
-
-/* Status Register masks */
-
-#define XIIC_SR_GEN_CALL_MASK		  0x01	/* 1=a mstr issued a GC	  */
-#define XIIC_SR_ADDR_AS_SLAVE_MASK	  0x02	/* 1=when addr as slave	  */
-#define XIIC_SR_BUS_BUSY_MASK		  0x04	/* 1 = bus is busy	  */
-#define XIIC_SR_MSTR_RDING_SLAVE_MASK	  0x08	/* 1=Dir: mstr <-- slave  */
-#define XIIC_SR_TX_FIFO_FULL_MASK	  0x10	/* 1 = Tx FIFO full	  */
-#define XIIC_SR_RX_FIFO_FULL_MASK	  0x20	/* 1 = Rx FIFO full	  */
-#define XIIC_SR_RX_FIFO_EMPTY_MASK	  0x40	/* 1 = Rx FIFO empty	  */
-
-/* IPIF Interrupt Status Register masks	   Interrupt occurs when...	  */
-
-#define XIIC_INTR_ARB_LOST_MASK		  0x01	/* 1 = arbitration lost	  */
-#define XIIC_INTR_TX_ERROR_MASK		  0x02	/* 1=Tx error/msg complete*/
-#define XIIC_INTR_TX_EMPTY_MASK		  0x04	/* 1 = Tx FIFO/reg empty  */
-#define XIIC_INTR_RX_FULL_MASK		  0x08	/* 1=Rx FIFO/reg=OCY level*/
-#define XIIC_INTR_BNB_MASK		  0x10	/* 1 = Bus not busy	  */
-#define XIIC_INTR_AAS_MASK		  0x20	/* 1 = when addr as slave */
-#define XIIC_INTR_NAAS_MASK		  0x40	/* 1 = not addr as slave  */
-#define XIIC_INTR_TX_HALF_MASK		  0x80	/* 1 = TX FIFO half empty */
-
-/* IPIF Device Interrupt Register masks */
-
-#define XIIC_IPIF_IIC_MASK	    0x00000004UL    /* 1=inter enabled */
-#define XIIC_IPIF_ERROR_MASK	    0x00000001UL    /* 1=inter enabled */
-#define XIIC_IPIF_INTER_ENABLE_MASK  (XIIC_IPIF_IIC_MASK |  \
-				      XIIC_IPIF_ERROR_MASK)
-
-#define XIIC_TX_ADDR_SENT	      0x00
-#define XIIC_TX_ADDR_MSTR_RECV_MASK   0x02
-
-/* The following constants specify the depth of the FIFOs */
-
-#define IIC_RX_FIFO_DEPTH	  16   /* Rx fifo capacity		 */
-#define IIC_TX_FIFO_DEPTH	  16   /* Tx fifo capacity		 */
-
-/* The following constants specify groups of interrupts that are typically
- * enabled or disables at the same time
- */
-#define XIIC_TX_INTERRUPTS					    \
-	    (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK |    \
-	     XIIC_INTR_TX_HALF_MASK)
-
-#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
-
-/* The following constants are used with the following macros to specify the
- * operation, a read or write operation.
- */
-#define XIIC_READ_OPERATION  1
-#define XIIC_WRITE_OPERATION 0
-
-/* The following constants are used with the transmit FIFO fill function to
- * specify the role which the IIC device is acting as, a master or a slave.
- */
-#define XIIC_MASTER_ROLE     1
-#define XIIC_SLAVE_ROLE	     0
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-unsigned XIic_Recv(u32 BaseAddress, u8 Address,
-		   u8 *BufferPtr, unsigned ByteCount);
-
-unsigned XIic_Send(u32 BaseAddress, u8 Address,
-		   u8 *BufferPtr, unsigned ByteCount);
-
-#endif		  /* end of protection macro */
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index ef4faa1..43c552d 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -22,9 +22,6 @@
 #
 
 include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
 
 LIB	= $(obj)lib$(BOARD).o