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authorYe Li <ye.li@nxp.com>2016-03-04 10:10:44 +0800
committerfang hui <hui.fang@nxp.com>2016-11-09 08:25:50 +0800
commit8d4edd5d83b872947b04bd81658c76181a19bf00 (patch)
treef7b67cb0ef810dd192cee3adfb33e7e59f9b485d /board
parent8ba75502ce87368327873c7274cca0f699cea8bb (diff)
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MLK-12492-1 mx6: fix type style problems introduced by patch MLK-12483
Some type style problems found by review-commits for previous patch MLK-12483, fix them in this patch and re-check. Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c17
-rw-r--r--board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c12
2 files changed, 12 insertions, 17 deletions
diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
index 765d5cc..c2de966 100644
--- a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
+++ b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
@@ -351,9 +351,8 @@ static void setup_eimnor(void)
int board_flash_wp_on(void)
{
- if (check_module_fused(MX6_MODULE_EIM)) {
+ if (check_module_fused(MX6_MODULE_EIM))
return 1; /* Skip flash init */
- }
return 0;
}
@@ -514,7 +513,7 @@ int mmc_map_to_kernel_blk(int dev_no)
{
if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
dev_no = 1;
-
+
return dev_no;
}
@@ -553,7 +552,7 @@ int board_mmc_init(bd_t *bis)
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
- case 0:
+ case 0:
#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
imx_iomux_v3_setup_multiple_pads(
usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
@@ -756,10 +755,9 @@ static int setup_fec(int fec_id)
int ret;
if (0 == fec_id) {
- if (check_module_fused(MX6_MODULE_ENET1)) {
+ if (check_module_fused(MX6_MODULE_ENET1))
return -1;
- }
-
+
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17]
@@ -771,10 +769,9 @@ static int setup_fec(int fec_id)
return ret;
} else {
- if (check_module_fused(MX6_MODULE_ENET2)) {
+ if (check_module_fused(MX6_MODULE_ENET2))
return -1;
- }
-
+
/* clk from phy, set gpr1[14], clear gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 01f5699..c09e2ae 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -498,7 +498,7 @@ int mmc_map_to_kernel_blk(int dev_no)
{
if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
dev_no = 1;
-
+
return dev_no;
}
@@ -755,18 +755,16 @@ static int setup_fec(int fec_id)
int ret;
if (0 == fec_id) {
- if (check_module_fused(MX6_MODULE_ENET1)) {
+ if (check_module_fused(MX6_MODULE_ENET1))
return -1;
- }
-
+
/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
} else {
- if (check_module_fused(MX6_MODULE_ENET2)) {
+ if (check_module_fused(MX6_MODULE_ENET2))
return -1;
- }
-
+
/* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);