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| author | Murali Karicheri <m-karicheri2@ti.com> | 2014-09-10 15:54:59 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-09-17 21:06:56 -0400 |
| commit | 6c343825dd8852843ee7426c579cb55520ad2fc8 (patch) | |
| tree | eadbd6bb5af57cc360c6a23bd9708e1bb86573f8 /board | |
| parent | c292adae170fa8c27dca75963bdb0a9afc640e57 (diff) | |
| download | u-boot-imx-6c343825dd8852843ee7426c579cb55520ad2fc8.zip u-boot-imx-6c343825dd8852843ee7426c579cb55520ad2fc8.tar.gz u-boot-imx-6c343825dd8852843ee7426c579cb55520ad2fc8.tar.bz2 | |
ARM: keystone: ddr3: workaround for ddr3a/3b memory issue
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/ks2_evm/ddr3_k2hk.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index 21a5a0a..6070a99 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -81,4 +81,8 @@ void ddr3_init(void) while (1) ; } + + /* Apply the workaround for PG 1.0 and 1.1 Silicons */ + if (cpu_revision() <= 1) + ddr3_err_reset_workaround(); } |