Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  drivers/rtc: add Marvell Integrated RTC
  Armada100: Add Board Support for Marvell GuruPlug-Display
  Armada100: MFP macro naming correction
  arm: auto gen asm-offsets.h for mb86r0x
  spear: fix build errors for spear3xx/spear600 platforms
  cosmetic: arm: lib/board.c: Coding Style cleanup
  ARM: versatile: fix board support
  SMDKV310: Enable device tree support
  SMDKV310: MMC_SPL: Fix building when using "make O="
  arm: a320: enable tagged list support
  arm: a320: fix multiline comment style
  ARMv7: u8500_href: Add missing header to fix compiler warning
  Removed unused define, CONFIG_ARMV7.
  avr32: add grasshopper (ICnova AP7000) board
  AT91/SPI: fix atmel_dataflash_spi.c to allow building without warnings
  MAKEALL: remove AT91 boards that are in boards.cfg
  AT91: Makes AT91SAM9263-EK build correctly against u-boot-atmel/master
  AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master
  AT91: Board fix for AT91SAM9261-EK
  AT91: SoC fix at91sam9261_matrix.h
  AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master
  AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
  AT91: change common at91sam9261 files to compile with new scheme
  AT91: fix mistake in at91sam9260_devices.c(spi1_hw_init)
  a/a/c/arm920t/at91/reset.c: drop obsolete CONFIG_AT91RM9200_USART
  README: fix arm920t/at91 path
  net/eth.c: drop obsolete at91rm9200 support
  README.at91-soc: remove AT91(RM9200) joining notice
  a/a/c/arm920t/cpu.c: remove CONFIG_AT91_LEGACY warning
  MAKEALL: remove obsolete at91rm9200 soc
  ARM: remove obsolete at91rm9200
  omap4: clock init support for omap4460
  omap4: support TPS programming
  omap: reuse omap3 gpio support in omap4
  omap4: sdram init changes for omap4460
  omap4: add omap4460 revision detection
  mkimage: Add OMAP boot image support
  omap: add MMC and FAT support to SPL
  omap: add basic SPL support
  armv7: start.S: fixes and enhancements for SPL
  omap4: automatic sdram detection
  omap4: calculate EMIF register values
  omap4: add sdram init support
  omap4: add clock support
  omap4: add OMAP4430 revision check
  omap4: cleanup pin mux data
  omap4: utility function to identify the context of hw init
  DA8xx: fix LPSC constants
  DA8xx: switch an enum to defines for consistency
  DA8xx: add MMC/SD controller addresses
  DaVinci EMAC: declare function for all DA8xx CPUs
  DA8xx: add generic GPIO driver
  DaVinci: rename gpio_defs.h to gpio.h
  omap3evm: eth: Include functions only when necessary
  omap3evm: Update ethernet reset sequence for Rev.G board
  omap3evm: eth: split function setup_net_chip
  omap3: Include array definition only when it is used
  omap730p2: fix build breaks
  omap2420h4: fix build breaks
  omap1610inn: fix build breaks
  omap1510inn: fix build breaks
  omap5912osk: fix build breaks
  omap1610h2: fix build breaks

28 files changed, 569 insertions, 367 deletions

diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
new file mode 100644
index 0000000..2d8bba0
--- /dev/null
+++ b/board/Marvell/gplugd/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2011
+# eInfochips Ltd. <www.einfochips.com>
+# Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+#
+# Based on Aspenite:
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)lib$(BOARD).o
+
+COBJS	:= gplugd.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
new file mode 100644
index 0000000..dc7d89d
--- /dev/null
+++ b/board/Marvell/gplugd/gplugd.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* I2C */
+		MFP105_CI2C_SDA,
+		MFP106_CI2C_SCL,
+
+		/* Enable Console on UART3 */
+		MFPO8_UART3_TXD,
+		MFPO9_UART3_RXD,
+		MFP_EOC		/*End of configuration*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	return 0;
+}
diff --git a/board/armltd/versatile/config.mk b/board/armltd/versatile/config.mk
deleted file mode 100644
index 8b57af1..0000000
--- a/board/armltd/versatile/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# image should be loaded at 0x01000000
-#
-
-CONFIG_SYS_TEXT_BASE = 0x01000000
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
index 6e836dd..ee8cb5e 100644
--- a/board/armltd/versatile/versatile.c
+++ b/board/armltd/versatile/versatile.c
@@ -51,7 +51,7 @@ void show_boot_progress(int progress)
  * Miscellaneous platform dependent initialisations
  */
 
-int board_init (void)
+int board_early_init_f (void)
 {
 	/*
 	 * set clock frequency:
@@ -62,6 +62,11 @@ int board_init (void)
 	  ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 	   (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
 
+	return 0;
+}
+
+int board_init (void)
+{
 	/* arch number of Versatile Board */
 	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
 
@@ -88,6 +93,9 @@ int misc_init_r (void)
 ******************************/
 int dram_init (void)
 {
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index de5cfae..b6c7d9e 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91sam9261_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -31,7 +32,6 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
@@ -49,44 +49,48 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_CMD_NAND
 static void at91sam9261ek_nand_hw_init(void)
 {
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
 #ifdef CONFIG_AT91SAM9G10EK
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+		&smc->cs[3].cycle);
 #else
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
 #endif
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		       AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		       AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		       &smc->cs[3].mode);
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -102,35 +106,37 @@ static void at91sam9261ek_nand_hw_init(void)
 #ifdef CONFIG_DRIVER_DM9000
 static void at91sam9261ek_dm9000_hw_init(void)
 {
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
 	/* Configure SMC CS2 for DM9000 */
 #ifdef CONFIG_AT91SAM9G10EK
-	at91_sys_write(AT91_SMC_SETUP(2),
-		       AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(2),
-		       AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) |
-		       AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8));
-	at91_sys_write(AT91_SMC_CYCLE(2),
-		       AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20));
-	at91_sys_write(AT91_SMC_MODE(2),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
-		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
-		       AT91_SMC_TDF_(1));
+	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+		&smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		       AT91_SMC_MODE_TDF_CYCLE(1),
+		       &smc->cs[2].mode);
 #else
-	at91_sys_write(AT91_SMC_SETUP(2),
-		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(2),
-		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
-		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
-	at91_sys_write(AT91_SMC_CYCLE(2),
-		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
-	at91_sys_write(AT91_SMC_MODE(2),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
-		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
-		       AT91_SMC_TDF_(1));
+	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		       AT91_SMC_MODE_TDF_CYCLE(1),
+		       &smc->cs[2].mode);
 #endif
 
 	/* Configure Reset signal as output */
@@ -156,7 +162,7 @@ vidinfo_t panel_info = {
 	vl_vsync_len:	1,
 	vl_upper_margin:1,
 	vl_lower_margin:0,
-	mmio:		AT91SAM9261_LCDC_BASE,
+	mmio:		ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
@@ -171,6 +177,8 @@ void lcd_disable(void)
 
 static void at91sam9261ek_lcd_hw_init(void)
 {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
 	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
 	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
 	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
@@ -194,12 +202,11 @@ static void at91sam9261ek_lcd_hw_init(void)
 	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
 	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
 
-	at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+	writel(AT91_PMC_HCK1, &pmc->scer);
 
-#ifdef CONFIG_AT91SAM9G10EK
-	gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE;
-#else
-	gd->fb_base = AT91SAM9261_SRAM_BASE;
+	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
+#ifdef CONFIG_AT91SAM9261EK
+	gd->fb_base = ATMEL_BASE_SRAM;
 #endif
 }
 
@@ -217,7 +224,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
@@ -246,9 +253,9 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 #endif
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_serial_hw_init();
+	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9261ek_nand_hw_init();
 #endif
@@ -273,8 +280,9 @@ int board_eth_init(bd_t *bis)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
 	return 0;
 }
 
diff --git a/board/atmel/at91sam9261ek/config.mk b/board/atmel/at91sam9261ek/config.mk
deleted file mode 100644
index e554a45..0000000
--- a/board/atmel/at91sam9261ek/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c
index 5d1c5f2..0c2f522 100644
--- a/board/atmel/at91sam9261ek/led.c
+++ b/board/atmel/at91sam9261ek/led.c
@@ -26,12 +26,15 @@
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
+	writel(ATMEL_ID_PIOA, &pmc->pcer);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 91efc07..4d2937d 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -32,7 +32,8 @@
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
@@ -52,9 +53,9 @@ DECLARE_GLOBAL_DATA_PTR;
 static void at91sam9263ek_nand_hw_init(void)
 {
 	unsigned long csa;
-	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
-	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+	at91_pmc_t    *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	/* Enable CS3 */
 	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
@@ -83,14 +84,14 @@ static void at91sam9263ek_nand_hw_init(void)
 		       AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-	writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
+	writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
 		&pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
@@ -98,11 +99,11 @@ static void at91sam9263ek_nand_hw_init(void)
 static void at91sam9263ek_macb_hw_init(void)
 {
 	unsigned long 	erstl;
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIO_BASE;
-	at91_rstc_t	*rstc	= (at91_rstc_t *) AT91_RSTC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
+	at91_rstc_t	*rstc	= (at91_rstc_t *) ATMEL_BASE_RSTC;
 	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -153,7 +154,7 @@ vidinfo_t panel_info = {
 	vl_vsync_len:	1,
 	vl_upper_margin:1,
 	vl_lower_margin:0,
-	mmio:		AT91SAM9263_LCDC_BASE,
+	mmio:		ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
@@ -168,7 +169,7 @@ void lcd_disable(void)
 
 static void at91sam9263ek_lcd_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
 	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
@@ -193,8 +194,8 @@ static void at91sam9263ek_lcd_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
 	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
 
-	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
-	gd->fb_base = AT91SAM9263_SRAM0_BASE;
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	gd->fb_base = ATMEL_BASE_SRAM0;
 }
 
 #ifdef CONFIG_LCD_INFO
@@ -218,7 +219,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
@@ -244,6 +245,18 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOCDE),
+		&pmc->pcer);
+
+	return 0;
+}
+
 int board_init(void)
 {
 	/* Enable Ctrlc */
@@ -252,9 +265,9 @@ int board_init(void)
 	/* arch number of AT91SAM9263EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_serial_hw_init();
+	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9263ek_nand_hw_init();
 #endif
@@ -276,8 +289,9 @@ int board_init(void)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
 	return 0;
 }
 
@@ -291,7 +305,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
+	rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
 #endif
 	return rc;
 }
diff --git a/board/atmel/at91sam9263ek/config.mk b/board/atmel/at91sam9263ek/config.mk
deleted file mode 100644
index e554a45..0000000
--- a/board/atmel/at91sam9263ek/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c
index fa1f05b..c44455e 100644
--- a/board/atmel/at91sam9263ek/led.c
+++ b/board/atmel/at91sam9263ek/led.c
@@ -23,25 +23,24 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/io.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91sam9263.h>
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
+	writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE,
 		&pmc->pcer);
 
-	at91_set_pio_output(CONFIG_RED_LED, 1);
-	at91_set_pio_output(CONFIG_GREEN_LED, 1);
-	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
 
-	at91_set_pio_value(CONFIG_RED_LED, 0);
-	at91_set_pio_value(CONFIG_GREEN_LED, 1);
-	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
 }
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index e374917..e559084 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91sam9rl_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -31,7 +32,7 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
 #include <lcd.h>
 #include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_CMD_NAND
 static void at91sam9rlek_nand_hw_init(void)
 {
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+	writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -102,7 +107,7 @@ vidinfo_t panel_info = {
 	vl_vsync_len:	1,
 	vl_upper_margin:1,
 	vl_lower_margin:0,
-	mmio:		AT91SAM9RL_LCDC_BASE,
+	mmio:		ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
@@ -116,6 +121,8 @@ void lcd_disable(void)
 }
 static void at91sam9rlek_lcd_hw_init(void)
 {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
 	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
 	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
 	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
@@ -138,9 +145,7 @@ static void at91sam9rlek_lcd_hw_init(void)
 	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
 	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
-
-	gd->fb_base = 0;
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 }
 
 #ifdef CONFIG_LCD_INFO
@@ -157,7 +162,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
@@ -173,6 +178,17 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
+		&pmc->pcer);
+
+	return 0;
+}
 
 int board_init(void)
 {
@@ -182,9 +198,9 @@ int board_init(void)
 	/* arch number of AT91SAM9RLEK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_serial_hw_init();
+	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9rlek_nand_hw_init();
 #endif
@@ -199,7 +215,8 @@ int board_init(void)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
diff --git a/board/atmel/at91sam9rlek/config.mk b/board/atmel/at91sam9rlek/config.mk
deleted file mode 100644
index e554a45..0000000
--- a/board/atmel/at91sam9rlek/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c
index 9634cc0..987e8c0 100644
--- a/board/atmel/at91sam9rlek/led.c
+++ b/board/atmel/at91sam9rlek/led.c
@@ -26,12 +26,14 @@
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+	writel(ATMEL_ID_PIOD, &pmc->pcer);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c
index 0ee0d11..0ad5678 100644
--- a/board/davinci/dm355leopard/dm355leopard.c
+++ b/board/davinci/dm355leopard/dm355leopard.c
@@ -20,7 +20,7 @@
 #include <nand.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/gpio_defs.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/nand_defs.h>
 #include <asm/arch/davinci_misc.h>
 #include <net.h>
diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c
index 5fb7611..ac54106 100644
--- a/board/davinci/dm365evm/dm365evm.c
+++ b/board/davinci/dm365evm/dm365evm.c
@@ -22,7 +22,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/nand_defs.h>
-#include <asm/arch/gpio_defs.h>
+#include <asm/arch/gpio.h>
 #include <netdev.h>
 #include <asm/arch/davinci_misc.h>
 #ifdef CONFIG_DAVINCI_MMC
diff --git a/board/ti/panda/config.mk b/board/in-circuit/grasshopper/Makefile
index 33901a7..a6c36c7 100644
--- a/board/ti/panda/config.mk
+++ b/board/in-circuit/grasshopper/Makefile
@@ -1,9 +1,9 @@
 #
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
+# Copyright (C) 2011
+# Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -15,17 +15,31 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
 
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+include $(TOPDIR)/config.mk
+
+LIB     := $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+
+SRCS    := $(COBJS-y:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS-y))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c
new file mode 100644
index 0000000..475a759
--- /dev/null
+++ b/board/in-circuit/grasshopper/grasshopper.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+				| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+				| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	/* Dual MT48LC16M16A2-7E (or equal) */
+	.data_bits		= SDRAM_DATA_32BIT,
+	.row_bits		= 13,
+	.col_bits		= 9,
+	.bank_bits		= 2,
+	.cas			= 2,
+	.twr			= 2,
+	.trc			= 7,
+	.trp			= 2,
+	.trcd			= 2,
+	.tras			= 4,
+	.txsr			= 7,
+	/* 7.81 us */
+	.refresh_period		= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart0(PORTMUX_DRIVE_MIN);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = uncached(EBI_SDRAM_BASE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x00;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+	return 0;
+}
+#endif
+/* vim: set noet ts=8: */
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index 0562222..0812c20 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -46,9 +46,7 @@ int dram_init(void)
 	struct xloader_table_1_2 *table_1_2;
 	struct chip_data *chip = &chip_data;
 
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1,
-					       PHYS_SDRAM_1_MAXSIZE);
+	gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
 
 	if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) {
 		table_1_1 = &xloader_tb->table.table_1_1;
@@ -66,6 +64,12 @@ int dram_init(void)
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
 int misc_init_r(void)
 {
 #if defined(CONFIG_CMD_NET)
diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c
index 525633e..9283fab 100644
--- a/board/st-ericsson/u8500/u8500_href.c
+++ b/board/st-ericsson/u8500/u8500_href.c
@@ -27,6 +27,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #ifdef CONFIG_MMC
+#include "prcmu-fw.h"
 #include "../../../drivers/mmc/arm_pl180_mmci.h"
 #endif
 
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index aaf3033..30c1c57 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -33,10 +33,14 @@
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
 #include <i2c.h>
 #include <asm/mach-types.h>
 #include "evm.h"
 
+#define OMAP3EVM_GPIO_ETH_RST_GEN1		64
+#define OMAP3EVM_GPIO_ETH_RST_GEN2		7
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static u32 omap3_evm_version;
@@ -130,6 +134,9 @@ int misc_init_r(void)
 #endif
 	omap3_evm_get_revision();
 
+#if defined(CONFIG_CMD_NET)
+	reset_net_chip();
+#endif
 	dieid_num_r();
 
 	return 0;
@@ -146,6 +153,7 @@ void set_muxconf_regs(void)
 	MUX_EVM();
 }
 
+#ifdef CONFIG_CMD_NET
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
@@ -153,7 +161,6 @@ void set_muxconf_regs(void)
  */
 static void setup_net_chip(void)
 {
-	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
@@ -172,16 +179,37 @@ static void setup_net_chip(void)
 	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 		&ctrl_base->gpmc_nadv_ale);
+}
 
-	/* Make GPIO 64 as output pin */
-	writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
-
-	/* Now send a pulse on the GPIO pin */
-	writel(GPIO0, &gpio3_base->setdataout);
+/**
+ * Reset the ethernet chip.
+ */
+static void reset_net_chip(void)
+{
+	int ret;
+	int rst_gpio;
+
+	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
+		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
+	} else {
+		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
+	}
+
+	ret = omap_request_gpio(rst_gpio);
+	if (ret < 0) {
+		printf("Unable to get GPIO %d\n", rst_gpio);
+		return ;
+	}
+
+	/* Configure as output */
+	omap_set_gpio_direction(rst_gpio, 0);
+
+	/* Send a pulse on the GPIO pin */
+	omap_set_gpio_dataout(rst_gpio, 1);
 	udelay(1);
-	writel(GPIO0, &gpio3_base->cleardataout);
+	omap_set_gpio_dataout(rst_gpio, 0);
 	udelay(1);
-	writel(GPIO0, &gpio3_base->setdataout);
+	omap_set_gpio_dataout(rst_gpio, 1);
 }
 
 int board_eth_init(bd_t *bis)
@@ -192,3 +220,4 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+#endif /* CONFIG_CMD_NET */
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
index b721ad6..623cf1b 100644
--- a/board/ti/evm/evm.h
+++ b/board/ti/evm/evm.h
@@ -49,6 +49,7 @@ u32 get_omap3_evm_rev(void);
 
 #if defined(CONFIG_CMD_NET)
 static void setup_net_chip(void);
+static void reset_net_chip(void);
 #endif
 
 /*
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index 2186403..09f88ee 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= panda.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 78e1910..9afed80 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/sdp4430/sdp.h b/board/ti/panda/panda_mux_data.h
index bf41067..16cc0ad 100644
--- a/board/ti/sdp4430/sdp.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _SDP_H_
-#define _SDP_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -207,11 +173,11 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
@@ -252,13 +216,15 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index f1ee544..12f2743 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= sdp.o cmd_bat.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/sdp4430/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index b13c4c5..a5ea682 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/panda/panda.h b/board/ti/sdp4430/sdp4430_mux_data.h
index e3d090e..16cc0ad 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_H_
-#define _PANDA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -53,7 +43,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -64,14 +54,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -189,12 +155,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -205,13 +171,13 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,29 +202,29 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */