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authorroy zang <tie-fei.zang@freescale.com>2006-12-04 17:56:59 +0800
committerZang Tiefei <roy@bus.ap.freescale.net>2006-12-04 17:56:59 +0800
commit9d27b3a0685ff99fc477983f315c04d49f657a8a (patch)
tree409a70e937d5f826df7929d11cb08a7cd207f5cd /board
parent4dbcd69e3e2776ea334590d5768e3692c5fae5c1 (diff)
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Slight code clean up.
Add comments, delete duplicate define and remove spaces. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/mpc7448hpc2/tsi108_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c
index fdb5365..e3b09cf 100644
--- a/board/mpc7448hpc2/tsi108_init.c
+++ b/board/mpc7448hpc2/tsi108_init.c
@@ -147,7 +147,7 @@ int board_early_init_f (void)
gd->mem_clk = 0;
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
- i = (i >> 20) & 0x07; /* value of SW4[4:7] */
+ i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
switch (i) {
case 0: /* external clock */
printf ("Using external clock\n");
@@ -229,7 +229,7 @@ int board_early_init_r (void)
__asm__ __volatile__ ("sync");
- /* Base addresses for Cs0, CS1, CS2, CS3 */
+ /* Base addresses for CS0, CS1, CS2, CS3 */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);