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authorTom Warren <twarren@nvidia.com>2013-03-06 16:16:22 -0700
committerTom Warren <twarren@nvidia.com>2013-03-14 11:06:43 -0700
commit8ca79b2ff467bda3bc1cfe7fe566f0c1189881dc (patch)
tree7cc9230b3f5f27c89df60bcb20c41c24bcbbb160 /board
parent8b7776b9f95d542d0e81357c4f8aa32f7bf466e5 (diff)
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Tegra30: Cardhu: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'board')
-rw-r--r--board/nvidia/cardhu/cardhu.c6
-rw-r--r--board/nvidia/cardhu/pinmux-config-cardhu.h21
2 files changed, 24 insertions, 3 deletions
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index df4cb6b..08e9b7b 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2012
+ * (C) Copyright 2010-2013
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-cardhu.h"
/*
@@ -36,4 +37,7 @@ void pinmux_init(void)
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
}
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
index 8428bba..51d2b94 100644
--- a/board/nvidia/cardhu/pinmux-config-cardhu.h
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -53,6 +53,18 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PGRP_LPMD_##_lpmd, \
+ .schmt = PGRP_SCHMT_##_schmt, \
+ .hsm = PGRP_HSM_##_hsm, \
+ }
+
static struct pingroup_config tegra3_pinmux_common[] = {
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
@@ -326,4 +338,9 @@ static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
};
-#endif /* _PINMUX_CONFIG_CARDHU_H_ */
+static struct padctrl_config cardhu_padctrl[] = {
+ /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */