ARM: remove broken "edb93xx" boards

Remove edb9301, edb9302, edb9302a, edb9307, edb9307a, edb9312,
edb9315 and edb9315a boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>

9 files changed, 0 insertions, 685 deletions

diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
deleted file mode 100644
index dcaed06..0000000
--- a/board/edb93xx/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
deleted file mode 100644
index fab59ef..0000000
--- a/board/edb93xx/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
-
-ifdef CONFIG_EDB9301
-CONFIG_SYS_TEXT_BASE = 0x05700000
-endif
-
-ifdef CONFIG_EDB9302
-CONFIG_SYS_TEXT_BASE = 0x05700000
-endif
-
-ifdef CONFIG_EDB9302A
-CONFIG_SYS_TEXT_BASE = 0xc5700000
-endif
-
-ifdef CONFIG_EDB9307
-CONFIG_SYS_TEXT_BASE = 0x01f00000
-endif
-
-ifdef CONFIG_EDB9307A
-CONFIG_SYS_TEXT_BASE = 0xc1f00000
-endif
-
-ifdef CONFIG_EDB9312
-CONFIG_SYS_TEXT_BASE = 0x01f00000
-endif
-
-ifdef CONFIG_EDB9315
-CONFIG_SYS_TEXT_BASE = 0x01f00000
-endif
-
-ifdef CONFIG_EDB9315A
-CONFIG_SYS_TEXT_BASE = 0xc1f00000
-endif
diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h
deleted file mode 100644
index 185283d..0000000
--- a/board/edb93xx/early_udelay.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-/* delay execution before timers are initialized */
-static inline void early_udelay(uint32_t usecs)
-{
-	/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
-	register uint32_t loops = usecs * (1000 / 20);
-
-	__asm__ volatile ("1:\n"
-			"subs %0, %1, #1\n"
-			"bne 1b":"=r" (loops):"0" (loops));
-}
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
deleted file mode 100644
index dde30ff..0000000
--- a/board/edb93xx/edb93xx.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * (C) Copyright 2002 2003
- * Network Audio Technologies, Inc. <www.netaudiotech.com>
- * Adam Bezanson <bezanson@netaudiotech.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MAX_BANK_SIZE	0x04000000 /* 64 MB */
-
-static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
-	PHYS_SDRAM_1,
-#ifdef PHYS_SDRAM_2
-	PHYS_SDRAM_2,
-#endif
-#ifdef PHYS_SDRAM_3
-	PHYS_SDRAM_3,
-#endif
-#ifdef PHYS_SDRAM_4
-	PHYS_SDRAM_4
-#endif
-};
-
-int board_init(void)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	icache_enable();
-
-#ifdef USE_920T_MMU
-	dcache_enable();
-#endif
-
-	/*
-	 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
-	 * 14.7456/2 MHz
-	 */
-	uint32_t value = readl(&syscon->pwrcnt);
-	value |= SYSCON_PWRCNT_UART_BAUD;
-	writel(value, &syscon->pwrcnt);
-
-	/* Enable the uart in devicecfg */
-	value = readl(&syscon->devicecfg);
-	value |= 1<<18 /* U1EN */;
-	writel(0xAA, &syscon->sysswlock);
-	writel(value, &syscon->devicecfg);
-
-	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
-	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* We have a console */
-	gd->have_console = 1;
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bd)
-{
-	return ep93xx_eth_initialize(0, MAC_BASE);
-}
-
-int dram_init(void)
-{
-	unsigned int *src, *dst;
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		const ulong bank_size = get_ram_size((long *)bank_addr[i],
-						MAX_BANK_SIZE);
-		if (bank_size) {
-			gd->bd->bi_dram[i].start = bank_addr[i];
-			gd->bd->bi_dram[i].size = bank_size;
-		}
-	}
-
-	/* copy exception vectors */
-	src = (unsigned int *)_armboot_start;
-	dst = (unsigned int *)PHYS_SDRAM_1;
-	memcpy(dst, src, 16 * sizeof(unsigned int));
-
-	return 0;
-}
diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c
deleted file mode 100644
index a4c2048..0000000
--- a/board/edb93xx/flash_cfg.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Flash setup for Cirrus edb93xx boards
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-#define SMC_BCR6_VALUE	(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT |	\
-				SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT |		\
-				1 << SMC_BCR_MW_SHIFT)
-
-void flash_cfg(void)
-{
-	struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
-
-	writel(SMC_BCR6_VALUE, &smc->bcr6);
-}
diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c
deleted file mode 100644
index a687af0..0000000
--- a/board/edb93xx/pll_cfg.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * PLL setup for Cirrus edb93xx boards
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include "pll_cfg.h"
-#include "early_udelay.h"
-
-void pll_cfg(void)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	/* setup PLL1 */
-	writel(CLKSET1_VAL, &syscon->clkset1);
-
-	/*
-	 * flush the pipeline
-	 * writing to CLKSET1 causes the EP93xx to enter standby for between
-	 * 8 ms to 16 ms, until PLL1 stabilizes
-	 */
-	asm("nop");
-	asm("nop");
-	asm("nop");
-	asm("nop");
-	asm("nop");
-
-	/* setup PLL2 */
-	writel(CLKSET2_VAL, &syscon->clkset2);
-
-	/*
-	 * the user's guide recommends to wait at least 1 ms for PLL2 to
-	 * stabilize
-	 */
-	early_udelay(1000);
-}
diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
deleted file mode 100644
index 0b6f469..0000000
--- a/board/edb93xx/pll_cfg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * PLL register values for Cirrus edb93xx boards
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/ep93xx.h>
-
-#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
-	defined(CONFIG_EDB9302A)
-/*
- * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
- * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
- * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
- */
-#define CLKSET1_VAL	(7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
-			8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
-			19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
-			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	\
-			3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
-			SYSCON_CLKSET1_NBYP1 |			\
-			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
-#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
-	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
-	defined(CONFIG_EDB9315A)
-/*
- * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
- * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
- * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
- */
-#define CLKSET1_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
-			30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
-			20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
-			1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT |	\
-			2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
-			SYSCON_CLKSET1_NBYP1 |			\
-			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
-#else
-#error "Undefined board"
-#endif
-
-/*
- * usb_div: 4, nbyp2: 1, pll2_en: 1
- * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
- * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
- */
-#define CLKSET2_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
-			24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
-			24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
-			1 << SYSCON_CLKSET_PLL_PS_SHIFT |	\
-			SYSCON_CLKSET2_PLL2_EN |		\
-			SYSCON_CLKSET2_NBYP2 |			\
-			3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
deleted file mode 100644
index 440ad11..0000000
--- a/board/edb93xx/sdram_cfg.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/io.h>
-#include "sdram_cfg.h"
-#include "early_udelay.h"
-
-#define PROGRAM_MODE_REG(bank)		(*(volatile uint32_t *)		\
-		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
-
-#define PRECHARGE_BANK(bank)		(*(volatile uint32_t *)		\
-		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
-
-static void precharge_all_banks(void);
-static void setup_refresh_timer(void);
-static void program_mode_registers(void);
-
-void sdram_cfg(void)
-{
-	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
-
-	writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
-
-	/* Issue continous NOP commands */
-	writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
-
-	early_udelay(200);
-
-	precharge_all_banks();
-
-	setup_refresh_timer();
-
-	program_mode_registers();
-
-	/* Select normal operation mode */
-	writel(GLCONFIG_CKE, &sdram->glconfig);
-}
-
-static void precharge_all_banks(void)
-{
-	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
-
-	/* Issue PRECHARGE ALL commands */
-	writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
-
-	/*
-	 * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
-	 * issued
-	 *
-	 * Cirrus proposes a workaround which consists in performing a read from
-	 * each bank to force the precharge. This causes some boards to hang.
-	 * Writing to the SDRAM banks instead of reading has the same
-	 * side-effect (the SDRAM controller issues the necessary precharges),
-	 * but is known to work on all supported boards
-	 */
-
-	PRECHARGE_BANK(0);
-
-#if (CONFIG_NR_DRAM_BANKS >= 2)
-	PRECHARGE_BANK(1);
-#endif
-
-#if (CONFIG_NR_DRAM_BANKS >= 3)
-	PRECHARGE_BANK(2);
-#endif
-
-#if (CONFIG_NR_DRAM_BANKS == 4)
-	PRECHARGE_BANK(3);
-#endif
-}
-
-static void setup_refresh_timer(void)
-{
-	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
-
-	/* Load refresh timer with 10 to issue refresh every 10 cycles */
-	writel(0x0a, &sdram->refrshtimr);
-
-	/*
-	 * Wait at least 80 clock cycles to provide 8 refresh cycles
-	 * to all SDRAMs
-	 */
-	early_udelay(1);
-
-	/*
-	 * Program refresh timer with normal value
-	 * We need 8192 refresh cycles every 64ms
-	 * at 15ns (HCLK >= 66MHz) per cycle:
-	 * 64ms / 8192 = 7.8125us
-	 * 7.8125us / 15ns = 520 (0x208)
-	 */
-	/*
-	 * TODO: redboot uses 0x1e0 for the slowest possible device
-	 * but i don't understand how this value is calculated
-	 */
-	writel(0x208, &sdram->refrshtimr);
-}
-
-static void program_mode_registers(void)
-{
-	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
-
-	/* Select mode register update mode */
-	writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
-
-	/*
-	 * The mode registers are programmed by performing a read from each
-	 * SDRAM bank. The value of the address that is read defines the value
-	 * that is written into the mode register
-	 */
-
-	PROGRAM_MODE_REG(0);
-
-#if (CONFIG_NR_DRAM_BANKS >= 2)
-	PROGRAM_MODE_REG(1);
-#endif
-
-#if (CONFIG_NR_DRAM_BANKS >= 3)
-	PROGRAM_MODE_REG(2);
-#endif
-
-#if (CONFIG_NR_DRAM_BANKS == 4)
-	PROGRAM_MODE_REG(3);
-#endif
-}
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
deleted file mode 100644
index 757b63c..0000000
--- a/board/edb93xx/sdram_cfg.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/ep93xx.h>
-
-#define SDRAM_BASE_ADDR		PHYS_SDRAM_1
-
-#ifdef CONFIG_EDB93XX_SDCS0
-#define SDRAM_DEVCFG_REG	devcfg0
-#elif defined(CONFIG_EDB93XX_SDCS3)
-#define SDRAM_DEVCFG_REG	devcfg3
-#else
-#error "SDRAM bank configuration"
-#endif
-
-#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
-	defined(CONFIG_EDB9302A)
-/*
- * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
- *
- * CLK cycle time min:
- *	@ CAS latency = 3: 7.5ns
- *	@ CAS latency = 2: 10ns
- * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
- * so it's safe to use CAS latency = 2
- *
- * RAS-to-CAS delay min:
- *	20ns
- * At 15ns cycle time, we use RAS-to-CAS delay = 2
- *
- * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
- * as four blocks of 8MB size, instead of eight blocks of 4MB size:
- *
- * EDB9301/EDB9302:
- *
- * 0x00000000 - 0x007fffff
- * 0x01000000 - 0x017fffff
- * 0x04000000 - 0x047fffff
- * 0x05000000 - 0x057fffff
- *
- *
- * EDB9302a:
- *
- * 0xc0000000 - 0xc07fffff
- * 0xc1000000 - 0xc17fffff
- * 0xc4000000 - 0xc47fffff
- * 0xc5000000 - 0xc57fffff
- *
- * BANKCOUNT = 1: This is a device with four banks
- */
-
-#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT |			\
-				SDRAM_DEVCFG_SROMLL |			\
-				SDRAM_DEVCFG_CASLAT_2 |			\
-				SDRAM_DEVCFG_RASTOCAS_2 |		\
-				SDRAM_DEVCFG_EXTBUSWIDTH)
-
-/*
- * 16 bit ext. bus
- *
- * A[22:09] is output as SYA[13:0]
- * CAS latency: 2
- * Burst type: sequential
- * Burst length: 8 (required for 16 bit ext. bus)
- * SYA[13:0] = 0x0023
- */
-#define SDRAM_MODE_REG_VAL	0x4600
-
-#define SDRAM_BANK_SEL_0	0x00000000 /* A[22:21] = b00 */
-#define SDRAM_BANK_SEL_1	0x00200000 /* A[22:21] = b01 */
-#define SDRAM_BANK_SEL_2	0x00400000 /* A[22:21] = b10 */
-#define SDRAM_BANK_SEL_3	0x00600000 /* A[22:21] = b11 */
-
-#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
-	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
-	defined(CONFIG_EDB9315A)
-/*
- * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
- *
- * CLK cycle time min:
- *	@ CAS latency = 3: 7.5ns
- *	@ CAS latency = 2: 10ns
- * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
- * so it's safe to use CAS latency = 2
- *
- * RAS-to-CAS delay min:
- *	20ns
- * At 10ns cycle time, we use RAS-to-CAS delay = 2
- *
- * EDB9307, EDB9312, EDB9315:
- *
- * 0x00000000 - 0x01ffffff
- * 0x04000000 - 0x05ffffff
- *
- *
- * EDB9307a, EDB9315a:
- *
- * 0xc0000000 - 0xc1ffffff
- * 0xc4000000 - 0xc5ffffff
- */
-
-#define SDRAM_DEVCFG_VAL	(SDRAM_DEVCFG_BANKCOUNT |		\
-				SDRAM_DEVCFG_SROMLL |			\
-				SDRAM_DEVCFG_CASLAT_2 |			\
-				SDRAM_DEVCFG_RASTOCAS_2)
-
-/*
- * 32 bit ext. bus
- *
- * A[23:10] is output as SYA[13:0]
- * CAS latency: 2
- * Burst type: sequential
- * Burst length: 4
- * SYA[13:0] = 0x0022
- */
-#define SDRAM_MODE_REG_VAL	0x8800
-
-#define SDRAM_BANK_SEL_0	0x00000000 /* A[23:22] = b00 */
-#define SDRAM_BANK_SEL_1	0x00400000 /* A[23:22] = b01 */
-#define SDRAM_BANK_SEL_2	0x00800000 /* A[23:22] = b10 */
-#define SDRAM_BANK_SEL_3	0x00c00000 /* A[23:22] = b11 */
-#endif