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authorJon Loeliger <jdl@freescale.com>2008-11-10 10:04:51 -0600
committerJon Loeliger <jdl@freescale.com>2008-11-10 10:04:51 -0600
commit33211469f7d7e2afacf103cc55790f734572f7a6 (patch)
tree7c374cde48fba08b52b4f83bdf00aae89d7f85a3 /board
parent1266df887781c779deaf6d05eea2ef90a470cb34 (diff)
parent1378174a1351c0285736863a665ab758fe8d5f71 (diff)
downloadu-boot-imx-33211469f7d7e2afacf103cc55790f734572f7a6.zip
u-boot-imx-33211469f7d7e2afacf103cc55790f734572f7a6.tar.gz
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Merge commit 'wd/master'
Diffstat (limited to 'board')
-rw-r--r--board/BuS/EB+MCF-EV123/Makefile2
-rw-r--r--board/BuS/EB+MCF-EV123/mii.c304
-rw-r--r--board/afeb9260/Makefile56
-rw-r--r--board/afeb9260/afeb9260.c243
-rw-r--r--board/afeb9260/config.mk1
-rw-r--r--board/afeb9260/nand.c78
-rw-r--r--board/afeb9260/partition.c37
-rw-r--r--board/amcc/canyonlands/init.S2
-rw-r--r--board/atmel/at91cap9adk/at91cap9adk.c8
-rw-r--r--board/atmel/at91sam9260ek/at91sam9260ek.c8
-rw-r--r--board/atmel/at91sam9261ek/at91sam9261ek.c6
-rw-r--r--board/atmel/at91sam9263ek/at91sam9263ek.c8
-rw-r--r--board/atmel/at91sam9rlek/at91sam9rlek.c6
-rw-r--r--board/atum8548/atum8548.c2
-rw-r--r--board/cobra5272/Makefile2
-rw-r--r--board/cobra5272/mii.c303
-rw-r--r--board/delta/nand.c2
-rw-r--r--board/freescale/m52277evb/config.mk4
-rw-r--r--board/freescale/m52277evb/m52277evb.c26
-rw-r--r--board/freescale/m52277evb/u-boot.spa (renamed from board/freescale/m52277evb/u-boot.lds)0
-rw-r--r--board/freescale/m52277evb/u-boot.stm (renamed from board/freescale/m5235evb/u-boot.lds)20
-rw-r--r--board/freescale/m5235evb/Makefile2
-rw-r--r--board/freescale/m5235evb/mii.c307
-rw-r--r--board/freescale/m5271evb/Makefile2
-rw-r--r--board/freescale/m5271evb/mii.c303
-rw-r--r--board/freescale/m5272c3/Makefile2
-rw-r--r--board/freescale/m5272c3/flash.c378
-rw-r--r--board/freescale/m5272c3/mii.c303
-rw-r--r--board/freescale/m5275evb/Makefile2
-rw-r--r--board/freescale/m5275evb/mii.c319
-rw-r--r--board/freescale/m5282evb/Makefile2
-rw-r--r--board/freescale/m5282evb/mii.c304
-rw-r--r--board/freescale/m53017evb/Makefile44
-rw-r--r--board/freescale/m53017evb/config.mk25
-rw-r--r--board/freescale/m53017evb/m53017evb.c94
-rw-r--r--board/freescale/m53017evb/u-boot.lds (renamed from board/freescale/m54455evb/u-boot.lds)6
-rw-r--r--board/freescale/m5329evb/Makefile2
-rw-r--r--board/freescale/m5329evb/mii.c306
-rw-r--r--board/freescale/m5329evb/nand.c57
-rw-r--r--board/freescale/m5373evb/Makefile2
-rw-r--r--board/freescale/m5373evb/mii.c306
-rw-r--r--board/freescale/m5373evb/nand.c17
-rw-r--r--board/freescale/m54451evb/Makefile2
-rw-r--r--board/freescale/m54451evb/mii.c303
-rw-r--r--board/freescale/m54455evb/Makefile2
-rw-r--r--board/freescale/m54455evb/mii.c324
-rw-r--r--board/freescale/m547xevb/Makefile2
-rw-r--r--board/freescale/m547xevb/mii.c322
-rw-r--r--board/freescale/m548xevb/Makefile2
-rw-r--r--board/freescale/m548xevb/mii.c322
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c6
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c2
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c2
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c2
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c6
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c2
-rw-r--r--board/freescale/mpc8641hpcn/ddr.c16
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c2
-rw-r--r--board/idmr/Makefile2
-rw-r--r--board/idmr/mii.c303
-rw-r--r--board/keymile/mgcoge/mgcoge.c276
-rw-r--r--board/keymile/mgsuvd/mgsuvd.c8
-rw-r--r--board/sbc8548/sbc8548.c2
-rw-r--r--board/sbc8641d/sbc8641d.c2
-rw-r--r--board/tqc/tqm8260/Makefile2
-rw-r--r--board/tqc/tqm8260/flash.c497
-rw-r--r--board/tqc/tqm85xx/tqm85xx.c4
-rw-r--r--board/versatile/versatile.c22
-rw-r--r--board/zylonite/nand.c2
69 files changed, 843 insertions, 5495 deletions
diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile
index ceeffa7..ed3ac07 100644
--- a/board/BuS/EB+MCF-EV123/Makefile
+++ b/board/BuS/EB+MCF-EV123/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
+COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c
deleted file mode 100644
index 7f92514..0000000
--- a/board/BuS/EB+MCF-EV123/mii.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- if (setclear) {
- MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
- } else {
- MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_AMD79C874VC "AMD79C874VC"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- strcpy(info->phy_name,
- STR_ID_AMD79C874VC);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- printf(STR_ID_AMD79C874VC);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile
new file mode 100644
index 0000000..60c4304
--- /dev/null
+++ b/board/afeb9260/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += afeb9260.o
+COBJS-y += partition.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
new file mode 100644
index 0000000..32445ab
--- /dev/null
+++ b/board/afeb9260/afeb9260.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <netdev.h>
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void afeb9260_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+ at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
+ at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+ at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
+ at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+ at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
+ at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3 /* DBGU */
+ at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
+ at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+static void afeb9260_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_TDF_(2));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(AT91_PIN_PC13, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(AT91_PIN_PC14, 1);
+}
+
+static void afeb9260_spi_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
+ at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
+
+ at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
+ at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
+ at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+}
+
+#ifdef CONFIG_MACB
+static void afeb9260_macb_hw_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ AT91_RSTC_ERSTL | (0x0D << 8) |
+ AT91_RSTC_URSTEN);
+
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+ /* Restore NRST value */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ AT91_RSTC_ERSTL | (0x0 << 8) |
+ AT91_RSTC_URSTEN);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+ at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
+ at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
+ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
+ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
+ at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
+ at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
+ at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
+ at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
+ at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
+ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
+
+#ifndef CONFIG_RMII
+ at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
+ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
+ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
+ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
+ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
+ at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
+ at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
+ at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
+#endif
+
+}
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* arch number of AT91SAM9260EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ afeb9260_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ afeb9260_nand_hw_init();
+#endif
+ afeb9260_spi_hw_init();
+#ifdef CONFIG_MACB
+ afeb9260_macb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
diff --git a/board/afeb9260/config.mk b/board/afeb9260/config.mk
new file mode 100644
index 0000000..9ce161e
--- /dev/null
+++ b/board/afeb9260/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000
diff --git a/board/afeb9260/nand.c b/board/afeb9260/nand.c
new file mode 100644
index 0000000..c5ac634
--- /dev/null
+++ b/board/afeb9260/nand.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+#define MASK_ALE (1 << 21) /* our ALE is AD21 */
+#define MASK_CLE (1 << 22) /* our CLE is AD22 */
+
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+{
+ return at91_get_gpio_value(AT91_PIN_PC13);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+#ifdef CONFIG_SYS_NAND_DBW_16
+ nand->options = NAND_BUSWIDTH_16;
+#endif
+ nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
+ nand->dev_ready = at91sam9260ek_nand_ready;
+ nand->chip_delay = 20;
+
+ return 0;
+}
diff --git a/board/afeb9260/partition.c b/board/afeb9260/partition.c
new file mode 100644
index 0000000..0b5dc5e
--- /dev/null
+++ b/board/afeb9260/partition.c
@@ -0,0 +1,37 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
+
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 694cc89..51b46d7 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -98,7 +98,7 @@ tlbtab:
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
#if defined(CONFIG_RAPIDIO)
- /* TLB-entries for RapidIO (SRIO) */
+ /* TLB-entries for RapidIO (SRIO) */
tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c
index a1a9238..af145cc 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -52,19 +52,19 @@ static void at91cap9_serial_hw_init(void)
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
@@ -412,7 +412,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
#endif
return rc;
}
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 372cfb2..ef99b8b 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -48,19 +48,19 @@ static void at91sam9260ek_serial_hw_init(void)
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
@@ -255,7 +255,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
#endif
return rc;
}
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 70f1db9..185d6e1 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -48,19 +48,19 @@ static void at91sam9261ek_serial_hw_init(void)
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 63f95e7..4feed9a 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -51,19 +51,19 @@ static void at91sam9263ek_serial_hw_init(void)
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
@@ -344,7 +344,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
#endif
return rc;
}
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 37e371f..992dd4c 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -48,19 +48,19 @@ static void at91sam9rlek_serial_hw_init(void)
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 7b7a968..226ef57 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -377,7 +377,7 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile
index be704b7..cf07cf4 100644
--- a/board/cobra5272/Makefile
+++ b/board/cobra5272/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o mii.o
+COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c
deleted file mode 100644
index 161c694..0000000
--- a/board/cobra5272/mii.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if (setclear) {
- gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
- } else {
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_AMD79C874VC "AMD79C874VC"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- strcpy(info->phy_name,
- STR_ID_AMD79C874VC);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- printf(STR_ID_AMD79C874VC);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 14382f5..aff7c54 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -46,8 +46,6 @@
# define DFC_DEBUG3(fmt, args...)
#endif
-#define MIN(x, y) ((x < y) ? x : y)
-
/* These really don't belong here, as they are specific to the NAND Model */
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk
index ce014ed..b42fcc9 100644
--- a/board/freescale/m52277evb/config.mk
+++ b/board/freescale/m52277evb/config.mk
@@ -22,4 +22,6 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index 838a6de..9109edb 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -38,8 +38,18 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
+ u32 dramsize;
+
+#ifdef CONFIG_CF_SBF
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- u32 dramsize, i;
+ volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
}
i--;
+ gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
@@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ __asm__("nop");
/* Issue LEMR */
- /*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ __asm__("nop");
+ sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ __asm__("nop");
udelay(1000);
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ __asm__("nop");
/* Perform two refresh cycles */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ __asm__("nop");
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ __asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
udelay(100);
-
+#endif
return (dramsize);
};
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.spa
index 7ae70d4..7ae70d4 100644
--- a/board/freescale/m52277evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.spa
diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m52277evb/u-boot.stm
index c0611b9..03ff532 100644
--- a/board/freescale/m5235evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.stm
@@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
+ .rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
@@ -55,15 +55,7 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf523x/start.o (.text)
- cpu/mcf523x/cpu_init.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ cpu/mcf5227x/start.o (.text)
*(.text)
*(.fixup)
@@ -129,7 +121,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
- .bss (NOLOAD) :
+ .bss :
{
_sbss = .;
*(.sbss) *(.scommon)
diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile
index 74c2528..981763d 100644
--- a/board/freescale/m5235evb/Makefile
+++ b/board/freescale/m5235evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c
deleted file mode 100644
index 5fbbd66..0000000
--- a/board/freescale/m5235evb/mii.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if (setclear) {
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
- } else {
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-#define STR_ID_KS8721BL "KS8721BL"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- strcpy(info->phy_name,
- STR_ID_KS8721BL);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- printf(STR_ID_KS8721BL);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile
index 2ec71ee..424ab1c 100644
--- a/board/freescale/m5271evb/Makefile
+++ b/board/freescale/m5271evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5271evb/mii.c b/board/freescale/m5271evb/mii.c
deleted file mode 100644
index e79fa19..0000000
--- a/board/freescale/m5271evb/mii.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- if (setclear) {
- /* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
- } else {
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-#define STR_ID_KS8721BL "KS8721BL"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- strcpy(info->phy_name,
- STR_ID_KS8721BL);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- printf(STR_ID_KS8721BL);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile
index be704b7..424ab1c 100644
--- a/board/freescale/m5272c3/Makefile
+++ b/board/freescale/m5272c3/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5272c3/flash.c b/board/freescale/m5272c3/flash.c
deleted file mode 100644
index 586a2cf..0000000
--- a/board/freescale/m5272c3/flash.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE 0x200000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (AMD_MANUFACT & FLASH_VENDMASK):
- printf ("AMD: ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (AMD_ID_PL160CB & FLASH_TYPEMASK):
- printf ("AM29PL160CB (16Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-
- Done:
- return;
-}
-
-
-unsigned long flash_init (void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id =
- (AMD_MANUFACT & FLASH_VENDMASK) |
- (AMD_ID_PL160CB & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- if (i == 0)
- flashbase = PHYS_FLASH_1;
- else
- panic ("configured to many flash banks!\n");
-
- for (j = 0; j < flash_info[i].sector_count; j++) {
- if (j == 0) {
- /* 1st is 16 KiB */
- flash_info[i].start[j] = flashbase;
- }
- if ((j >= 1) && (j <= 2)) {
- /* 2nd and 3rd are 8 KiB */
- flash_info[i].start[j] =
- flashbase + 0x4000 + 0x2000 * (j - 1);
- }
- if (j == 3) {
- /* 4th is 224 KiB */
- flash_info[i].start[j] = flashbase + 0x8000;
- }
- if ((j >= 4) && (j <= 10)) {
- /* rest is 256 KiB */
- flash_info[i].start[j] =
- flashbase + 0x40000 + 0x40000 * (j -
- 4);
- }
- }
- size += flash_info[i].size;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
-
- return size;
-}
-
-
-#define CMD_READ_ARRAY 0x00F0
-#define CMD_UNLOCK1 0x00AA
-#define CMD_UNLOCK2 0x0055
-#define CMD_ERASE_SETUP 0x0080
-#define CMD_ERASE_CONFIRM 0x0030
-#define CMD_PROGRAM 0x00A0
-#define CMD_UNLOCK_BYPASS 0x0020
-
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
-
-#define BIT_ERASE_DONE 0x0080
-#define BIT_RDY_MASK 0x0080
-#define BIT_PROGRAM_ERROR 0x0020
-#define BIT_TIMEOUT 0x80000000 /* our flag */
-
-#define READY 1
-#define ERR 2
-#define TMO 4
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- ulong result;
- int iflag, cflag, prot, sect;
- int rc = ERR_OK;
- int chip1;
-
- /* first look for protection bits */
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (AMD_MANUFACT & FLASH_VENDMASK)) {
- return ERR_UNKNOWN_FLASH_VENDOR;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot)
- return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- cflag = icache_status ();
- icache_disable ();
- iflag = disable_interrupts ();
-
- printf ("\n");
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- set_timer (0);
-
- if (info->protect[sect] == 0) { /* not protected */
- volatile u16 *addr =
- (volatile u16 *) (info->start[sect]);
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- *addr = CMD_ERASE_CONFIRM;
-
- /* wait until flash is ready */
- chip1 = 0;
-
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
- chip1 = TMO;
- break;
- }
-
- if (!chip1
- && (result & 0xFFFF) & BIT_ERASE_DONE)
- chip1 = READY;
-
- } while (!chip1);
-
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
- if (chip1 == ERR) {
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if (chip1 == TMO) {
- rc = ERR_TIMOUT;
- goto outahere;
- }
-
- printf ("ok.\n");
- } else { /* it was protected */
-
- printf ("protected!\n");
- }
- }
-
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- outahere:
- /* allow flash to settle - wait 10 ms */
- udelay (10000);
-
- if (iflag)
- enable_interrupts ();
-
- if (cflag)
- icache_enable ();
-
- return rc;
-}
-
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile u16 *addr = (volatile u16 *) dest;
- ulong result;
- int rc = ERR_OK;
- int cflag, iflag;
- int chip1;
-
- /*
- * Check if Flash is (sufficiently) erased
- */
- result = *addr;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
-
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- cflag = icache_status ();
- icache_disable ();
- iflag = disable_interrupts ();
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_PROGRAM;
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- set_timer (0);
-
- /* wait until flash is ready */
- chip1 = 0;
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- chip1 = ERR | TMO;
- break;
- }
- if (!chip1 && ((result & 0x80) == (data & 0x80)))
- chip1 = READY;
-
- } while (!chip1);
-
- *addr = CMD_READ_ARRAY;
-
- if (chip1 == ERR || *addr != data)
- rc = ERR_PROG_ERROR;
-
- if (iflag)
- enable_interrupts ();
-
- if (cflag)
- icache_enable ();
-
- return rc;
-}
-
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp, data;
- int rc;
-
- if (addr & 1) {
- printf ("unaligned destination not supported\n");
- return ERR_ALIGN;
- }
-
-#if 0
- if (cnt & 1) {
- printf ("odd transfer sizes not supported\n");
- return ERR_ALIGN;
- }
-#endif
-
- wp = addr;
-
- if (addr & 1) {
- data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
- src);
- if ((rc = write_word (info, wp - 1, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- while (cnt >= 2) {
- data = *((volatile u16 *) src);
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 2;
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 1) {
- data = (*((volatile u8 *) src) << 8) |
- *((volatile u8 *) (wp + 1));
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- return ERR_OK;
-}
diff --git a/board/freescale/m5272c3/mii.c b/board/freescale/m5272c3/mii.c
deleted file mode 100644
index 161c694..0000000
--- a/board/freescale/m5272c3/mii.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if (setclear) {
- gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
- } else {
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_AMD79C874VC "AMD79C874VC"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- strcpy(info->phy_name,
- STR_ID_AMD79C874VC);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- printf(STR_ID_AMD79C874VC);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile
index 74c2528..981763d 100644
--- a/board/freescale/m5275evb/Makefile
+++ b/board/freescale/m5275evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5275evb/mii.c b/board/freescale/m5275evb/mii.c
deleted file mode 100644
index 706d8d6..0000000
--- a/board/freescale/m5275evb/mii.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- struct fec_info_s *info = (struct fec_info_s *) dev->priv;
- volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-
- if (setclear) {
- /* Enable Ethernet pins */
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
- gpio->par_feci2c |= 0x0F00;
- gpio->par_fec0hl |= 0xC0;
- } else {
- gpio->par_feci2c |= 0x00A0;
- gpio->par_fec1hl |= 0xC0;
- }
- } else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
- gpio->par_feci2c &= ~0x0F00;
- gpio->par_fec0hl &= ~0xC0;
- } else {
- gpio->par_feci2c &= ~0x00A0;
- gpio->par_fec1hl &= ~0xC0;
- }
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-#define STR_ID_KS8721BL "KS8721BL"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- strcpy(info->phy_name,
- STR_ID_KS8721BL);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- printf(STR_ID_KS8721BL);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile
index 2ec71ee..424ab1c 100644
--- a/board/freescale/m5282evb/Makefile
+++ b/board/freescale/m5282evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5282evb/mii.c b/board/freescale/m5282evb/mii.c
deleted file mode 100644
index 7f92514..0000000
--- a/board/freescale/m5282evb/mii.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- if (setclear) {
- MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
- } else {
- MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_AMD79C874VC "AMD79C874VC"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- strcpy(info->phy_name,
- STR_ID_AMD79C874VC);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_AMD79C874VC:
- printf(STR_ID_AMD79C874VC);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m53017evb/Makefile b/board/freescale/m53017evb/Makefile
new file mode 100644
index 0000000..981763d
--- /dev/null
+++ b/board/freescale/m53017evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m53017evb/config.mk b/board/freescale/m53017evb/config.mk
new file mode 100644
index 0000000..ce014ed
--- /dev/null
+++ b/board/freescale/m53017evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
new file mode 100644
index 0000000..f331786
--- /dev/null
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M53017EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+#endif
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+ udelay(500);
+
+ /* Issue PALL */
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ /* Perform two refresh cycles */
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ asm("nop");
+
+ /* Issue LEMR */
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ asm("nop");
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ asm("nop");
+
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ asm("nop");
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index bcf30c3..dc53141 100644
--- a/board/freescale/m54455evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -55,9 +55,9 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5445x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ cpu/mcf532x/start.o (.text)
+ cpu/mcf532x/libmcf532x.a (.text)
+ lib_m68k/libm68k.a (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile
index ab0f11e..07b693c 100644
--- a/board/freescale/m5329evb/Makefile
+++ b/board/freescale/m5329evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o nand.o
+COBJS = $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c
deleted file mode 100644
index c0f5817..0000000
--- a/board/freescale/m5329evb/mii.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if (setclear) {
- gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
- gpio->par_feci2c |=
- GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
- } else {
- gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_DP83848VV:
- strcpy(info->phy_name,
- STR_ID_DP83848VV);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_DP83848VV:
- printf(STR_ID_DP83848VV);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 82492f6..cf27dda 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR;
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
-#define CLR_CLE ~SET_CLE
#define SET_ALE 0x08
-#define CLR_ALE ~SET_ALE
-static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
-/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
- u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+ volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- nand_baseaddr |= SET_CLE;
- else
- nand_baseaddr &= CLR_CLE;
- if ( ctrl & NAND_ALE )
- nand_baseaddr |= SET_ALE;
- else
- nand_baseaddr &= CLR_ALE;
- }
- this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
+ IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+ *nCE &= 0xFFFB;
-static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
- struct nand_chip *this = mtdinfo->priv;
- *((volatile u8 *)(this->IO_ADDR_W)) = byte;
-}
+ if (ctrl & NAND_NCE)
+ *nCE |= 0x0004;
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= SET_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= SET_ALE;
-static u8 nand_read_byte(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtdinfo->priv;
- return (u8) (*((volatile u8 *)this->IO_ADDR_R));
-}
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
-static int nand_dev_ready(struct mtd_info *mtdinfo)
-{
- return 1;
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
-
- /* set up pin configuration */
+ /*
+ * set up pin configuration - enabled 2nd output buffer's signals
+ * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+ * to use nCE signal
+ */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
@@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand)
nand->chip_delay = 50;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_hwcontrol;
- nand->read_byte = nand_read_byte;
- nand->write_byte = nand_write_byte;
- nand->dev_ready = nand_dev_ready;
return 0;
}
diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile
index ab0f11e..07b693c 100644
--- a/board/freescale/m5373evb/Makefile
+++ b/board/freescale/m5373evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o nand.o
+COBJS = $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m5373evb/mii.c b/board/freescale/m5373evb/mii.c
deleted file mode 100644
index c0f5817..0000000
--- a/board/freescale/m5373evb/mii.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if (setclear) {
- gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
- gpio->par_feci2c |=
- GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
- } else {
- gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_DP83848VV:
- strcpy(info->phy_name,
- STR_ID_DP83848VV);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_DP83848VV:
- printf(STR_ID_DP83848VV);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index d01b819..3ebef05 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR;
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+ volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(SET_ALE | SE_CLE);
+ IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+ *nCE &= 0xFFFB;
+
+ if (ctrl & NAND_NCE)
+ *nCE |= 0x0004;
if (ctrl & NAND_CLE)
IO_ADDR_W |= SET_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= SET_ALE;
- at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
@@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
- /* set up pin configuration */
+ /*
+ * set up pin configuration - enabled 2nd output buffer's signals
+ * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+ * to use nCE signal
+ */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
index 74c2528..981763d 100644
--- a/board/freescale/m54451evb/Makefile
+++ b/board/freescale/m54451evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m54451evb/mii.c b/board/freescale/m54451evb/mii.c
deleted file mode 100644
index 6e24736..0000000
--- a/board/freescale/m54451evb/mii.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_s *info = (struct fec_info_s *)dev->priv;
-
- if (setclear) {
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
- else
- gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
- } else {
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
- else
- gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_KSZ8041NL 0x00221512
-#define STR_ID_KSZ8041NL "KSZ8041NL"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- struct eth_device *dev;
- int i, miispd;
- u16 rst = 0;
-
- dev = eth_get_dev();
-
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
- for (i = 0; i < FEC_RESET_DELAY; ++i) {
- udelay(500);
- miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
- if ((rst & PHY_BMCR_RESET) == 0)
- break;
- }
- if (i == FEC_RESET_DELAY)
- printf("Mii reset timeout %d\n", i);
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_KSZ8041NL:
- strcpy(info->phy_name,
- STR_ID_KSZ8041NL);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_KSZ8041NL:
- printf(STR_ID_KSZ8041NL);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile
index 74c2528..981763d 100644
--- a/board/freescale/m54455evb/Makefile
+++ b/board/freescale/m54455evb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c
deleted file mode 100644
index c195191..0000000
--- a/board/freescale/m54455evb/mii.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_s *info = (struct fec_info_s *)dev->priv;
-
- if (setclear) {
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
- else
- gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
- } else {
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
- else
- gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- struct eth_device *dev;
- int i, miispd;
- u16 rst = 0;
-
- dev = eth_get_dev();
-
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
- for (i = 0; i < FEC_RESET_DELAY; ++i) {
- udelay(500);
- miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
- if ((rst & PHY_BMCR_RESET) == 0)
- break;
- }
- if (i == FEC_RESET_DELAY)
- printf("Mii reset timeout %d\n", i);
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_DP83848VV:
- strcpy(info->phy_name,
- STR_ID_DP83848VV);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_DP83848VV:
- printf(STR_ID_DP83848VV);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile
index 74c2528..981763d 100644
--- a/board/freescale/m547xevb/Makefile
+++ b/board/freescale/m547xevb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m547xevb/mii.c b/board/freescale/m547xevb/mii.c
deleted file mode 100644
index 4d11506..0000000
--- a/board/freescale/m547xevb/mii.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-
-#include <asm/immap.h>
-#include <asm/fec.h>
-#include <asm/fsl_mcdmafec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
-
- if (setclear) {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2cirq |= 0xF000;
- else
- gpio->par_feci2cirq |= 0x0FC0;
- } else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2cirq &= 0x0FFF;
- else
- gpio->par_feci2cirq &= 0xF03F;
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-#define STR_ID_BCM5222 "BCM5222"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_dma *info)
-{
- volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_dma *info;
- struct eth_device *dev;
- volatile fecdma_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fecdma_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_dma *info = dev->priv;
- int phyaddr, pass, temp;
- uint phyno, phytype;
-
- if (info->phyname_init) {
- return info->phy_addr;
- }
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- temp = 0;
- if (info->index > 0) {
- /* Some phy have multiple address, to solve the issue
- where phyno keeps starting from 0, check the
- previous phy address if both miibase are the same. */
- if (info->miibase == (info->next)->miibase) {
- temp = (info->next)->phy_addr + 1;
- }
- }
-
- for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_BCM5222:
- strcpy(info->phy_name, STR_ID_BCM5222);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_BCM5222:
- printf(STR_ID_BCM5222);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fecdma_t *fecp;
- struct fec_info_dma *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fecdma_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile
index 74c2528..981763d 100644
--- a/board/freescale/m548xevb/Makefile
+++ b/board/freescale/m548xevb/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/m548xevb/mii.c b/board/freescale/m548xevb/mii.c
deleted file mode 100644
index 4d11506..0000000
--- a/board/freescale/m548xevb/mii.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-
-#include <asm/immap.h>
-#include <asm/fec.h>
-#include <asm/fsl_mcdmafec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
-
- if (setclear) {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2cirq |= 0xF000;
- else
- gpio->par_feci2cirq |= 0x0FC0;
- } else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2cirq &= 0x0FFF;
- else
- gpio->par_feci2cirq &= 0xF03F;
- }
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-#define STR_ID_BCM5222 "BCM5222"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_dma *info)
-{
- volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_dma *info;
- struct eth_device *dev;
- volatile fecdma_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fecdma_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_dma *info = dev->priv;
- int phyaddr, pass, temp;
- uint phyno, phytype;
-
- if (info->phyname_init) {
- return info->phy_addr;
- }
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- temp = 0;
- if (info->index > 0) {
- /* Some phy have multiple address, to solve the issue
- where phyno keeps starting from 0, check the
- previous phy address if both miibase are the same. */
- if (info->miibase == (info->next)->miibase) {
- temp = (info->next)->phy_addr + 1;
- }
- }
-
- for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_BCM5222:
- strcpy(info->phy_name, STR_ID_BCM5222);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_BCM5222:
- printf(STR_ID_BCM5222);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fecdma_t *fecp;
- struct fec_info_dma *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fecdma_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 2978b7d..6fed4ea 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -439,8 +439,8 @@ int board_early_init_r(void)
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
+ flush_dcache();
+ invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
@@ -646,7 +646,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 600d606..545d869 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -488,7 +488,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 6eb62ea..af5ff42 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -479,7 +479,7 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_pci_setup(void *blob, bd_t *bd)
{
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 28e3892..688d8c3 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -496,7 +496,7 @@ pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index d1528a7..3a78c98 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -362,8 +362,8 @@ int board_early_init_r(void)
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
+ flush_dcache();
+ invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
@@ -560,7 +560,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 02dc744..2792778 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -403,7 +403,7 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 517c6ee..3789b54 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -47,12 +47,12 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
- u32 n_ranks;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
+ u32 datarate_mhz_low;
+ u32 datarate_mhz_high;
+ u32 n_ranks;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
} board_specific_parameters_t;
/* XXX: these values need to be checked for all interleaving modes. */
@@ -84,7 +84,7 @@ const board_specific_parameters_t board_specific_parameters[2][16] = {
{
/* memory controller 1 */
- /* lo| hi| num| clk| cpo|wrdata */
+ /* lo| hi| num| clk| cpo|wrdata */
/* mhz| mhz|ranks|adjst| | delay */
{ 0, 333, 4, 7, 7, 3},
{334, 400, 4, 7, 9, 3},
@@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (i&1) { /* odd CS */
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 0;
- } else { /* even CS */
+ } else { /* even CS */
if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
(pdimm[i/2].n_ranks != 0)) {
popts->cs_local_opts[i].odt_rd_cfg = 3;
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index d6a0a56..15be0c6 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -249,7 +249,7 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
diff --git a/board/idmr/Makefile b/board/idmr/Makefile
index be704b7..cf07cf4 100644
--- a/board/idmr/Makefile
+++ b/board/idmr/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o mii.o
+COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/idmr/mii.c b/board/idmr/mii.c
deleted file mode 100644
index e79fa19..0000000
--- a/board/idmr/mii.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
- if (setclear) {
- /* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
- } else {
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
-#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
-#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
-
-#define STR_ID_LXT970 "LXT970"
-#define STR_ID_LXT971 "LXT971"
-#define STR_ID_82555 "Intel82555"
-#define STR_ID_QS6612 "QS6612"
-#define STR_ID_AMD79C784 "AMD79C784"
-#define STR_ID_LSI80225 "LSI80225"
-#define STR_ID_LSI80225B "LSI80225/B"
-#define STR_ID_DP83848VV "N83848"
-#define STR_ID_DP83849 "N83849"
-#define STR_ID_KS8721BL "KS8721BL"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
- volatile fec_t *fecp = (fec_t *) (info->miibase);
- int i;
-
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
- udelay(1);
- }
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
- }
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
- struct fec_info_s *info;
- struct eth_device *dev;
- volatile fec_t *ep;
- uint mii_reply;
- int j = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- ep = (fec_t *) info->miibase;
-
- ep->mmfr = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("MII not complete\n");
- return -1;
- }
-
- mii_reply = ep->mmfr; /* result from phy */
- ep->eir = FEC_EIR_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
- struct fec_info_s *info = dev->priv;
- int phyaddr, pass;
- uint phyno, phytype;
-
- if (info->phyname_init)
- return info->phy_addr;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay(10000); /* wait 10ms */
- }
-
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- strcpy(info->phy_name,
- STR_ID_KS8721BL);
- info->phyname_init = 1;
- break;
- default:
- strcpy(info->phy_name, "unknown");
- info->phyname_init = 1;
- break;
- }
-
-#ifdef ET_DEBUG
- printf("PHY @ 0x%x pass %d type ", phyno, pass);
- switch (phytype & 0xffffffff) {
- case PHY_ID_KS8721BL:
- printf(STR_ID_KS8721BL);
- break;
- default:
- printf("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0)
- printf("No PHY device found.\n");
-
- return phyaddr;
-}
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
- volatile fec_t *fecp;
- struct fec_info_s *info;
- struct eth_device *dev;
- int miispd = 0, i = 0;
- u16 autoneg = 0;
-
- /* retrieve from register structure */
- dev = eth_get_dev();
- info = dev->priv;
-
- fecp = (fec_t *) info->miibase;
-
- fecpin_setclear(dev, 1);
-
- mii_reset(info);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set MII speed */
- miispd = (gd->bus_clk / 1000000) / 5;
- fecp->mscr = miispd << 1;
-
- info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
- while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
- i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
- break;
-
- udelay(500);
- }
- if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
- }
-
- /* adapt to the half/full speed settings */
- info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
- info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send(mk_mii_read(addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
- printf("0x%04x\n", value);
-#endif
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index 6dda920..3683417 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -45,152 +45,152 @@ extern int ivm_read_eeprom (void);
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
- /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
- /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
- /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
- /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
- /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
- /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
- /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
- /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
- /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
- /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
- /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
- /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
+ /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
+ /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
+ /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
+ /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
+ /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
+ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
+ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
+ /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
+ /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
+ /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
+ /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
+ /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
+ /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
+ /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
+ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
+ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
+ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
+ /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
+ /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
+ /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
+ /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
},
/* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
- /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
- /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
- /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
- /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
- /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
- /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
- /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
- /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
- /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
- /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
- /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
- /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
- /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
+ /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
+ /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
+ /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
+ /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
+ /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
+ /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
+ /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
+ /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
+ /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
+ /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
+ /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
+ /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
+ /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
+ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
},
/* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
- /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
- /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
+ /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
+ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+ /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
+ /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
+ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
+ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
+ /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
+ /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
},
/* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
- /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
- /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
- /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
+ /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
+ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
+ /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
+ /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
+ /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
+ /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
+ /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
+ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#else
- /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
+ /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
+ /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
+ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
+ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
}
};
@@ -309,10 +309,10 @@ int hush_init_var (void)
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
extern int fdt_set_node_and_value (void *blob,
- char *nodename,
- char *regname,
- void *var,
- int size);
+ char *nodename,
+ char *regname,
+ void *var,
+ int size);
/*
* update "memory" property in the blob
diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c
index 0fd28da..3726acf 100644
--- a/board/keymile/mgsuvd/mgsuvd.c
+++ b/board/keymile/mgsuvd/mgsuvd.c
@@ -151,10 +151,10 @@ int hush_init_var (void)
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
extern int fdt_set_node_and_value (void *blob,
- char *nodename,
- char *regname,
- void *var,
- int size);
+ char *nodename,
+ char *regname,
+ void *var,
+ int size);
/*
* update "memory" property in the blob
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e27c92d..9548ac6 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -530,7 +530,7 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index e33dbee..1471e58 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -322,7 +322,7 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup (void *blob, bd_t *bd)
{
diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile
index 61221fd..94ba1e9 100644
--- a/board/tqc/tqm8260/Makefile
+++ b/board/tqc/tqm8260/Makefile
@@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o
+COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c
deleted file mode 100644
index cabc818..0000000
--- a/board/tqc/tqm8260/flash.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for AMD devices on the TQM8260 board
- *
- *--------------------------------------------------------------------
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define V_ULONG(a) (*(volatile unsigned long *)( a ))
-#define V_BYTE(a) (*(volatile unsigned char *)( a ))
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_reset (void)
-{
- if (flash_info[0].flash_id != FLASH_UNKNOWN) {
- V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
- V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (ulong baseaddr, flash_info_t * info)
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- /* Write auto select command sequence and test FLASH answer */
- V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
- V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
- V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
- V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
-
- flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */
- flashtest_l = V_ULONG (baseaddr + 4);
-
- switch ((int) flashtest_h) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- flashtest_h = V_ULONG (baseaddr + 8); /* device ID */
- flashtest_l = V_ULONG (baseaddr + 12);
- if (flashtest_h != flashtest_l) {
- info->flash_id = FLASH_UNKNOWN;
- } else {
- switch (flashtest_h) {
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00400000;
- break; /* 4 * 1 MB = 4 MB */
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00400000;
- break; /* 4 * 1 MB = 4 MB */
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00800000;
- break; /* 4 * 2 MB = 8 MB */
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00800000;
- break; /* 4 * 2 MB = 8 MB */
- case AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* 4 * 4 MB = 16 MB */
- case AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x02000000;
- break; /* 4 * 8 MB = 32 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* no or unknown flash */
- }
- }
-
- if (flashtest_h == AMD_ID_LV640U) {
-
- /* set up sector start adress table (uniform sector type) */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = baseaddr + (i * 0x00040000);
-
- } else if (info->flash_id & FLASH_BTYPE) {
-
- /* set up sector start adress table (bottom sector type) */
- info->start[0] = baseaddr + 0x00000000;
- info->start[1] = baseaddr + 0x00010000;
- info->start[2] = baseaddr + 0x00018000;
- info->start[3] = baseaddr + 0x00020000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
- }
-
- } else {
-
- /* set up sector start adress table (top sector type) */
- i = info->sector_count - 1;
- info->start[i--] = baseaddr + info->size - 0x00010000;
- info->start[i--] = baseaddr + info->size - 0x00018000;
- info->start[i--] = baseaddr + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = baseaddr + i * 0x00040000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
- (V_ULONG (info->start[i] + 20) & 0x00010001)) {
- info->protect[i] = 1; /* D0 = 1 if protected */
- } else {
- info->protect[i] = 0;
- }
- }
-
- flash_reset ();
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 >> 20);
- }
-
- /*
- * protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
- &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM800T:
- printf ("29LV800T (8 M, top sector)\n");
- break;
- case FLASH_AM800B:
- printf ("29LV800T (8 M, bottom sector)\n");
- break;
- case FLASH_AM160T:
- printf ("29LV160T (16 M, top sector)\n");
- break;
- case FLASH_AM160B:
- printf ("29LV160B (16 M, bottom sector)\n");
- break;
- case FLASH_AMDL322T:
- printf ("29DL322T (32 M, top sector)\n");
- break;
- case FLASH_AMDL322B:
- printf ("29DL322B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL323T:
- printf ("29DL323T (32 M, top sector)\n");
- break;
- case FLASH_AMDL323B:
- printf ("29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_AM640U:
- printf ("29LV640D (64 M, uniform sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
- udelay (1000);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- V_ULONG (info->start[sect]) = 0x00300030;
- V_ULONG (info->start[sect] + 4) = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
- (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
- {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- flash_reset ();
-
- printf (" done\n");
- return 0;
-}
-
-static int write_dword (flash_info_t *, ulong, unsigned char *);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong dp;
- static unsigned char bb[8];
- int i, l, rc, cc = cnt;
-
- dp = (addr & ~7); /* get lower dword aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - dp) != 0) {
- for (i = 0; i < 8; i++)
- bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
- if ((rc = write_dword (info, dp, bb)) != 0) {
- return (rc);
- }
- dp += 8;
- cc -= 8 - l;
- }
-
- /*
- * handle word aligned part
- */
- while (cc >= 8) {
- if ((rc = write_dword (info, dp, src)) != 0) {
- return (rc);
- }
- dp += 8;
- src += 8;
- cc -= 8;
- }
-
- if (cc <= 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- for (i = 0; i < 8; i++) {
- bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
- }
- return (write_dword (info, dp, bb));
-}
-
-/*-----------------------------------------------------------------------
- * Write a dword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
-{
- ulong start, cl, ch;
- int flag, i;
-
- for (ch = 0, i = 0; i < 4; i++)
- ch = (ch << 8) + *pdata++; /* high word */
- for (cl = 0, i = 0; i < 4; i++)
- cl = (cl << 8) + *pdata++; /* low word */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *) dest) & ch) != ch
- || (*((vu_long *) (dest + 4)) & cl) != cl) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
- V_ULONG (dest) = ch;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
- V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
- V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
- V_ULONG (dest + 4) = cl;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
- ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 97d49ea..3a828ed 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -23,7 +23,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -702,7 +702,7 @@ void pci_init_board (void)
#ifdef CONFIG_OF_BOARD_SETUP
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+ struct pci_controller *hose);
void ft_board_setup (void *blob, bd_t *bd)
{
diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c
index 3b9b020..0f35caa 100644
--- a/board/versatile/versatile.c
+++ b/board/versatile/versatile.c
@@ -37,10 +37,6 @@
DECLARE_GLOBAL_DATA_PTR;
-void flash__init (void);
-void ether__init (void);
-void peripheral_power_enable (void);
-
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
@@ -82,8 +78,6 @@ int board_init (void)
icache_enable ();
- flash__init ();
- ether__init ();
return 0;
}
@@ -98,22 +92,6 @@ int misc_init_r (void)
Routine:
Description:
******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
int dram_init (void)
{
return 0;
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 895fb2b..899445e 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -46,8 +46,6 @@
# define DFC_DEBUG3(fmt, args...)
#endif
-#define MIN(x, y) ((x < y) ? x : y)
-
/* These really don't belong here, as they are specific to the NAND Model */
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };