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authorPaul Gortmaker <paul.gortmaker@windriver.com>2009-09-20 20:36:04 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:05:00 -0500
commit11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab (patch)
tree084dfd5667b06957a383a14c5a67bdbaf4b10ad6 /board
parent0c7e4d45d9fb3c9e503ee93d50572d346dae150e (diff)
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sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
-rw-r--r--board/sbc8548/sbc8548.c8
-rw-r--r--board/sbc8548/tlb.c23
2 files changed, 23 insertions, 8 deletions
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index ce998e1..f4bfd92 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -149,7 +149,7 @@ local_bus_init(void)
void
sdram_init(void)
{
-#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -169,6 +169,12 @@ sdram_init(void)
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
asm("msync");
+ out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
+ asm("msync");
+
+ out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
+ asm("msync");
+
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index a0b4e36..a1795fc 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -93,14 +93,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 5: 64M Cacheable, non-guarded
- * 0xf0000000 64M LBC SDRAM
+ * 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 6: 16M Cacheable, non-guarded
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf4000000 64M LBC SDRAM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+ CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 7: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
@@ -108,24 +117,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
+ 0, 7, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 7: 4M Non-cacheable, guarded
+ * TLB 8: 4M Non-cacheable, guarded
* 0xfb800000 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 8, BOOKE_PAGESZ_4M, 1),
/*
- * TLB 8: 4M Non-cacheable, guarded
+ * TLB 9: 4M Non-cacheable, guarded
* 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4M, 1),
+ 0, 9, BOOKE_PAGESZ_4M, 1),
};