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authorSimon Glass <sjg@chromium.org>2011-09-21 12:40:02 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-10-27 21:56:29 +0200
commit03c609f69b12dca47b9422595fdde29be1fb35c9 (patch)
treeaa4e9f2bb9ac562ace58b5891d7001704ef8d812 /board
parentc30a15e590c7e5bfd27e4704c81648071f11d51f (diff)
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tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the code now deals with both PLL clocks and source clocks. This also tidied up the assert() to match the one sent upstream, and fixes an error in the PWM id. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board')
-rw-r--r--board/nvidia/common/board.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 160dac8..32d3cfb 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -77,7 +77,7 @@ int timer_init(void)
static void clock_init_uart(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
+ struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
u32 reg;
reg = readl(&pll->pll_base);