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authorJames Doublesin <doublesin@ti.com>2014-12-22 16:26:12 -0600
committerTom Rini <trini@ti.com>2015-01-13 11:53:39 -0500
commitc87b6a96aca6748d519fd047da10fb7ed47017ad (patch)
tree63203dc1d913fd01a3f2ae18c6b38f2478109fc7 /board
parentfc46bae2ae38c8d0b1570427b5c9520281eaae4f (diff)
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arm: am437x: Correct PLL frequency for 25MHz
The frequencies for 25MHz in dpll_per were out of spec for 25MHz, correct. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'board')
-rw-r--r--board/ti/am43xx/board.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d851f83..9874773 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -124,7 +124,7 @@ const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
- {32, 0, 8, -1, -1, -1, -1}, /* 25 MHz */
+ {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
};