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authorLarry Johnson <lrj@arlinx.com>2007-12-22 15:15:13 -0500
committerStefan Roese <sr@denx.de>2007-12-27 19:35:36 +0100
commitc46f53333b22b1f9098676bea8884fc7db820cf3 (patch)
tree8799bc7addb2224f8f5959367ad4b4e01434e291 /board
parentc348578bf612d0c56d8d376d23cae16defbd86af (diff)
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Add definitions for 440EPx/GRx SDRAM controller to ppc440.h
This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: Larry Johnson <lrj@acm.org>
Diffstat (limited to 'board')
-rw-r--r--board/amcc/sequoia/sdram.h4
-rw-r--r--board/lwmon5/sdram.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h
index 7f847aa..6a7bf01 100644
--- a/board/amcc/sequoia/sdram.h
+++ b/board/amcc/sequoia/sdram.h
@@ -395,8 +395,8 @@
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h
index 7f847aa..6a7bf01 100644
--- a/board/lwmon5/sdram.h
+++ b/board/lwmon5/sdram.h
@@ -395,8 +395,8 @@
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000