Merge branch 'mpc86xx'

8 files changed, 669 insertions, 103 deletions

diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile
index d6037c1..2613730 100644
--- a/board/mpc8641hpcn/Makefile
+++ b/board/mpc8641hpcn/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o oftree.o
+OBJS	:= $(BOARD).o pixis.o oftree.o
 SOBJS	:= init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk
index 4bdceec..989a40b 100644
--- a/board/mpc8641hpcn/config.mk
+++ b/board/mpc8641hpcn/config.mk
@@ -1,5 +1,5 @@
 # Copyright 2004 Freescale Semiconductor.
-# Modified by Jeff Brown (jeffrey@freescale.com)
+# Modified by Jeff Brown
 #
 # See file CREDITS for list of people who contributed to this
 # project.
diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S
index 4d555a5..69954a8 100644
--- a/board/mpc8641hpcn/init.S
+++ b/board/mpc8641hpcn/init.S
@@ -1,6 +1,6 @@
 /*
  * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -36,11 +36,10 @@
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
  * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
+ * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
  * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
  *
  * Notes:
@@ -60,7 +59,6 @@
 #define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
-/*#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */
 #define LAWAR3	(~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
 
 /*
@@ -73,14 +71,20 @@
 #define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
 
 #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
-/*#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */
 #define LAWAR6	(~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
 
- #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
- #define LAWAR7	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
+#define LAWAR7	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
 
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR8 0
+#define LAWAR8  ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
 
-      	.section .bootpg, "ax"
+	.section .bootpg, "ax"
 	.globl	law_entry
 law_entry:
 	lis	r7,CFG_CCSRBAR@h
@@ -104,8 +108,8 @@ law_entry:
 	stwu    r6, 0x20(r4)
 
 	lis     r6,LAWAR2@h
-        ori     r6,r6,LAWAR2@l
-        stwu    r6, 0x20(r5)
+	ori     r6,r6,LAWAR2@l
+	stwu    r6, 0x20(r5)
 
 	/* LAWBAR3, LAWAR3 */
 	lis     r6,LAWBAR3@h
@@ -121,7 +125,7 @@ law_entry:
 	ori     r6,r6,LAWBAR4@l
 	stwu    r6, 0x20(r4)
 
-        lis     r6,LAWAR4@h
+	lis     r6,LAWAR4@h
 	ori     r6,r6,LAWAR4@l
 	stwu    r6, 0x20(r5)
 	/* LAWBAR5, LAWAR5 */
@@ -151,5 +155,14 @@ law_entry:
 	ori     r6,r6,LAWAR7@l
 	stwu    r6, 0x20(r5)
 
+	/* LAWBAR8, LAWAR8 */
+	lis     r6,LAWBAR8@h
+	ori     r6,r6,LAWBAR8@l
+	stwu    r6, 0x20(r4)
+
+	lis     r6,LAWAR8@h
+	ori     r6,r6,LAWAR8@l
+	stwu    r6, 0x20(r5)
+
 	blr
 
diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c
index d02a7ef..c6b2a5b 100644
--- a/board/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/mpc8641hpcn/mpc8641hpcn.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@ -25,6 +25,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
@@ -35,20 +36,23 @@
 extern void ft_cpu_setup(void *blob, bd_t *bd);
 #endif
 
+#include "pixis.h"
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
 
-void local_bus_init(void);
 void sdram_init(void);
 long int fixed_sdram(void);
 
 
 int board_early_init_f (void)
 {
-    return 0;
+	return 0;
 }
 
 int checkboard (void)
@@ -57,41 +61,34 @@ int checkboard (void)
 
 #ifdef CONFIG_PCI
 
-        volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-        volatile ccsr_gur_t *gur = &immap->im_gur;
-        volatile ccsr_pex_t *pex1 = &immap->im_pex1;
-
-        uint devdisr = gur->devdisr;
-        uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
-        uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
-        uint pex1_agent =  (host1_agent == 0) || (host1_agent == 1);
-
-        
-        if ((io_sel==2 || io_sel==3 || io_sel==5 \
-	     || io_sel==6 || io_sel==7 || io_sel==0xF)
-	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
-		debug ("PCI-EXPRESS 1: %s \n",
-		       pex1_agent ? "Agent" : "Host");
-                debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
-                if (pex1->pme_msg_det) {
-                        pex1->pme_msg_det = 0xffffffff;
-                        debug (" with errors.  Clearing.  Now 0x%08x",
-			       pex1->pme_msg_det);
-                }
-                debug ("\n");
-        } else {
-                printf ("PCI-EXPRESS 1: Disabled\n");
-        }
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_pex_t *pex1 = &immap->im_pex1;
+
+	uint devdisr = gur->devdisr;
+	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint pex1_agent =  (host1_agent == 0) || (host1_agent == 1);
+
+	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+		debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
+		if (pex1->pme_msg_det) {
+			pex1->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+			      pex1->pme_msg_det);
+		}
+		debug ("\n");
+	} else {
+		puts("PCI-EXPRESS 1: Disabled\n");
+	}
 
 #else
-	printf("PCI-EXPRESS1: Disabled\n");
+	puts("PCI-EXPRESS1: Disabled\n");
 #endif
 
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init();
-
 	return 0;
 }
 
@@ -100,7 +97,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	extern long spd_sdram (void);
 
 #if defined(CONFIG_SPD_EEPROM)
 	dram_size = spd_sdram ();
@@ -112,7 +108,7 @@ initdram(int board_type)
 	puts("    DDR: ");
 	return dram_size;
 #endif
-	
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
@@ -125,34 +121,6 @@ initdram(int board_type)
 }
 
 
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
-	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-}
-
 #if defined(CFG_DRAM_TEST)
 int testdram(void)
 {
@@ -160,7 +128,7 @@ int testdram(void)
 	uint *pend = (uint *) CFG_MEMTEST_END;
 	uint *p;
 
-	printf("SDRAM test phase 1:\n");
+	puts("SDRAM test phase 1:\n");
 	for (p = pstart; p < pend; p++)
 		*p = 0xaaaaaaaa;
 
@@ -171,7 +139,7 @@ int testdram(void)
 		}
 	}
 
-	printf("SDRAM test phase 2:\n");
+	puts("SDRAM test phase 2:\n");
 	for (p = pstart; p < pend; p++)
 		*p = 0x55555555;
 
@@ -182,7 +150,7 @@ int testdram(void)
 		}
 	}
 
-	printf("SDRAM test passed.\n");
+	puts("SDRAM test passed.\n");
 	return 0;
 }
 #endif
@@ -207,9 +175,9 @@ long int fixed_sdram(void)
 	ddr->sdram_mode_1 = CFG_DDR_MODE_1;
 	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
 	ddr->sdram_interval = CFG_DDR_INTERVAL;
-        ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
 	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
-	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;	
+	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
 	ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
 
 #if defined (CONFIG_DDR_ECC)
@@ -217,7 +185,7 @@ long int fixed_sdram(void)
 	ddr->err_sbe = 0x00ff0000;
 #endif
 	asm("sync;isync");
-	
+
 	udelay(500);
 
 #if defined (CONFIG_DDR_ECC)
@@ -228,7 +196,7 @@ long int fixed_sdram(void)
 	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
 #endif
 	asm("sync; isync");
-	
+
 	udelay(500);
 #endif
 	return CFG_SDRAM_SIZE * 1024 * 1024;
@@ -281,15 +249,113 @@ ft_board_setup(void *blob, bd_t *bd)
 	int len;
 
 	ft_cpu_setup(blob, bd);
-	
+
 	p = ft_get_prop(blob, "/memory/reg", &len);
 	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
-
 }
 #endif
 
 
+void
+mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char cmd;
+	ulong val;
+	ulong corepll;
 
+	/*
+	 * No args is a simple reset request.
+	 */
+	if (argv <= 0) {
+		out8(PIXIS_BASE + PIXIS_RST, 0);
+		/* not reached */
+	}
+
+	cmd = argv[1][1];
+	switch (cmd) {
+	case 'f':    /* reset with frequency changed */
+		if (argc < 5)
+			goto my_usage;
+		read_from_px_regs(0);
+
+		val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+		corepll = strfractoint(argv[3]);
+		val = val + set_px_corepll(corepll);
+		val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+		if (val == 3) {
+			puts("Setting registers VCFGEN0 and VCTL\n");
+			read_from_px_regs(1);
+			puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+			set_px_go();
+		} else
+			goto my_usage;
+
+		while (1); /* Not reached */
+
+	case 'l':
+		if (argv[2][1] == 'f') {
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			/* reset with frequency changed */
+			val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+
+			corepll = strfractoint(argv[4]);
+			val = val + set_px_corepll(corepll);
+			val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
+			if (val == 3) {
+				puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+				set_altbank();
+				read_from_px_regs(1);
+				read_from_px_regs_altbank(1);
+				puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+				set_px_go_with_watchdog();
+			} else
+				goto my_usage;
+
+			while(1); /* Not reached */
+
+		} else if(argv[2][1] == 'd'){
+			/*
+			 * Reset from alternate bank without changing
+			 * frequencies but with watchdog timer enabled.
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+			set_altbank();
+			read_from_px_regs_altbank(1);
+			puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+			set_px_go_with_watchdog();
+			while(1); /* Not reached */
+
+		} else {
+			/*
+			 * Reset from next bank without changing
+			 * frequency and without watchdog timer enabled.
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			if(argc > 2)
+				goto my_usage;
+			puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+			set_altbank();
+			read_from_px_regs_altbank(1);
+			puts("Resetting board to boot from the other bank....\n");
+			set_px_go();
+		}
+
+	default:
+		goto my_usage;
+	}
+
+my_usage:
+	puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+	puts("       reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+	puts("       reset altbank [wd]\n");
+	puts("For example:   reset cf 40 2.5 10\n");
+	puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+}
diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts
index ef28fc3..a11c321 100644
--- a/board/mpc8641hpcn/oftree.dts
+++ b/board/mpc8641hpcn/oftree.dts
@@ -18,7 +18,7 @@
 	linux,phandle = <100>;
 
 	cpus {
-		#cpus = <1>;
+		#cpus = <2>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		linux,phandle = <200>;
@@ -30,19 +30,32 @@
 			i-cache-line-size = <20>;	// 32 bytes
 			d-cache-size = <8000>;		// L1, 32K
 			i-cache-size = <8000>;		// L1, 32K
-			timebase-frequency = <0>;	//  33 MHz, from uboot
-			bus-frequency = <0>;	// 166 MHz
-			clock-frequency = <0>;	// 825 MHz, from uboot
+			timebase-frequency = <0>;	// 33 MHz, from uboot
+			bus-frequency = <0>;		// From uboot
+			clock-frequency = <0>;		// From uboot
 			32-bit;
 			linux,phandle = <201>;
 			linux,boot-cpu;
 		};
+		PowerPC,8641@1 {
+			device_type = "cpu";
+			reg = <1>;
+			d-cache-line-size = <20>;	// 32 bytes
+			i-cache-line-size = <20>;	// 32 bytes
+			d-cache-size = <8000>;		// L1, 32K
+			i-cache-size = <8000>;		// L1, 32K
+			timebase-frequency = <0>;	// 33 MHz, from uboot
+			bus-frequency = <0>;		// From uboot
+			clock-frequency = <0>;		// From uboot
+			32-bit;
+			linux,phandle = <202>;
+		};
 	};
 
 	memory {
 		device_type = "memory";
 		linux,phandle = <300>;
-		reg = <00000000 10000000>;	// 256M at 0x0
+		reg = <00000000 40000000>;	// 1G at 0x0
 	};
 
 	soc8641@f8000000 {
@@ -63,6 +76,15 @@
 			dfsrr;
 		};
 
+		i2c@3100 {
+			device_type = "i2c";
+			compatible = "fsl-i2c";
+			reg = <3100 100>;
+			interrupts = <2b 0>;
+			interrupt-parent = <40000>;
+			dfsrr;
+		};
+
 		mdio@24520 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -73,28 +95,28 @@
 			ethernet-phy@0 {
 				linux,phandle = <2452000>;
 				interrupt-parent = <40000>;
-				interrupts = <a 0>;
+				interrupts = <3a 0>;
 				reg = <0>;
 				device_type = "ethernet-phy";
 			};
 			ethernet-phy@1 {
 				linux,phandle = <2452001>;
 				interrupt-parent = <40000>;
-				interrupts = <a 0>;
+				interrupts = <3a 0>;
 				reg = <1>;
 				device_type = "ethernet-phy";
 			};
 			ethernet-phy@2 {
 				linux,phandle = <2452002>;
 				interrupt-parent = <40000>;
-				interrupts = <a 0>;
+				interrupts = <3a 0>;
 				reg = <2>;
 				device_type = "ethernet-phy";
 			};
 			ethernet-phy@3 {
 				linux,phandle = <2452003>;
 				interrupt-parent = <40000>;
-				interrupts = <a 0>;
+				interrupts = <3a 0>;
 				reg = <3>;
 				device_type = "ethernet-phy";
 			};
@@ -154,8 +176,8 @@
 		serial@4500 {
 			device_type = "serial";
 			compatible = "ns16550"; 
-			reg = <4500 100>; 	// reg base, size
-			clock-frequency = <0>; 	// should we fill in in uboot?
+			reg = <4500 100>;
+			clock-frequency = <0>;
 			interrupts = <2a 3>;
 			interrupt-parent = <40000>;
 		};
@@ -163,12 +185,120 @@
 		serial@4600 {
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;	// reg base, size
-			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 3>;
+			reg = <4600 100>;
+			clock-frequency = <0>;
+			interrupts = <1c 3>;
 			interrupt-parent = <40000>;
 		};
 
+		pci@8000 {
+			compatible = "86xx";
+			device_type = "pci";
+			linux,phandle = <8000>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <8000 1000>;
+			bus-range = <0 fe>;
+			ranges = <02000000 0 80000000 80000000 0 20000000
+				  01000000 0 00000000 e2000000 0 00100000>;
+			clock-frequency = <1fca055>;
+			interrupt-parent = <40000>;
+			interrupts = <8 0>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x11 */
+				8800 0 0 1 40000 3 0
+				8800 0 0 2 40000 4 0
+				8800 0 0 3 40000 5 0
+				8800 0 0 4 40000 6 0
+
+				/* IDSEL 0x12 */
+				9000 0 0 1 40000 4 0
+				9000 0 0 2 40000 5 0
+				9000 0 0 3 40000 6 0
+				9000 0 0 4 40000 3 0
+
+				/* IDSEL 0x13 */
+				9800 0 0 1 40000 5 0
+				9800 0 0 2 40000 6 0
+				9800 0 0 3 40000 3 0
+				9800 0 0 4 40000 4 0
+
+				/* IDSEL 0x14 */
+				a000 0 0 1 40000 6 0
+				a000 0 0 2 40000 3 0
+				a000 0 0 3 40000 4 0
+				a000 0 0 4 40000 5 0
+
+				/* IDSEL 0x15 */
+				a800 0 0 1 40000 0 0
+				a800 0 0 2 40000 0 0
+				a800 0 0 3 40000 0 0
+				a800 0 0 4 40000 0 0
+
+				/* IDSEL 0x16 */
+				b000 0 0 1 40000 0 0
+				b000 0 0 2 40000 0 0
+				b000 0 0 3 40000 0 0
+				b000 0 0 4 40000 0 0
+
+				/* IDSEL 0x17 */
+				b800 0 0 1 40000 0 0
+				b800 0 0 2 40000 0 0
+				b800 0 0 3 40000 0 0
+				b800 0 0 4 40000 0 0
+
+				/* IDSEL 0x18 */
+				c000 0 0 1 40000 0 0
+				c000 0 0 2 40000 0 0
+				c000 0 0 3 40000 0 0
+				c000 0 0 4 40000 0 0
+
+				/* IDSEL 0x19 */
+				c800 0 0 1 40000 0 0
+				c800 0 0 2 40000 0 0
+				c800 0 0 3 40000 0 0
+				c800 0 0 4 40000 0 0
+
+				/* IDSEL 0x1a */
+				d000 0 0 1 40000 0 0
+				d000 0 0 2 40000 0 0
+				d000 0 0 3 40000 0 0
+				d000 0 0 4 40000 0 0
+
+
+				/* IDSEL 0x1b */
+				d800 0 0 1 40000 0 0
+				d800 0 0 2 40000 0 0
+				d800 0 0 3 40000 0 0
+				d800 0 0 4 40000 0 0
+
+				/* IDSEL 0x1c */
+				e000 0 0 1 40000 0 0
+				e000 0 0 2 40000 0 0
+				e000 0 0 3 40000 0 0
+				e000 0 0 4 40000 0 0
+
+				/* IDSEL 0x1d */
+				e800 0 0 1 40000 0 0
+				e800 0 0 2 40000 0 0
+				e800 0 0 3 40000 0 0
+				e800 0 0 4 40000 0 0
+
+				/* IDSEL 0x1e */
+				f000 0 0 1 40000 0 0
+				f000 0 0 2 40000 0 0
+				f000 0 0 3 40000 0 0
+				f000 0 0 4 40000 0 0
+
+				/* IDSEL 0x1f */
+				f800 0 0 1 40000 6 0
+				f800 0 0 2 40000 6 0
+				f800 0 0 3 40000 6 0
+				f800 0 0 4 40000 6 0
+				>;
+		};
 		pic@40000 {
 			linux,phandle = <40000>;
 			clock-frequency = <0>;
diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c
new file mode 100644
index 0000000..f226b3e
--- /dev/null
+++ b/board/mpc8641hpcn/pixis.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#include "pixis.h"
+
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+int set_px_sysclk(ulong sysclk)
+{
+	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+	switch (sysclk) {
+	case 33:
+		sysclk_s = 0x04;
+		sysclk_r = 0x04;
+		sysclk_v = 0x07;
+		sysclk_aux = 0x00;
+		break;
+	case 40:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x20;
+		sysclk_aux = 0x01;
+		break;
+	case 50:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x2A;
+		sysclk_aux = 0x02;
+		break;
+	case 66:
+		sysclk_s = 0x01;
+		sysclk_r = 0x04;
+		sysclk_v = 0x04;
+		sysclk_aux = 0x03;
+		break;
+	case 83:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x04;
+		break;
+	case 100:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x5C;
+		sysclk_aux = 0x05;
+		break;
+	case 134:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x3B;
+		sysclk_aux = 0x06;
+		break;
+	case 166:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x07;
+		break;
+	default:
+		printf("Unsupported SYSCLK frequency.\n");
+		return 0;
+	}
+
+	vclkh = (sysclk_s << 5) | sysclk_r ;
+	vclkl = sysclk_v;
+
+	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
+	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+
+	out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux);
+
+	return 1;
+}
+
+
+int set_px_mpxpll(ulong mpxpll)
+{
+	u8 tmp;
+	u8 val;
+
+	switch (mpxpll) {
+	case 2:
+	case 4:
+	case 6:
+	case 8:
+	case 10:
+	case 12:
+	case 14:
+	case 16:
+		val = (u8)mpxpll;
+		break;
+	default:
+		printf("Unsupported MPXPLL ratio.\n");
+		return 0;
+	}
+
+	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+	tmp = (tmp & 0xF0) | (val & 0x0F);
+	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+
+	return 1;
+}
+
+
+int set_px_corepll(ulong corepll)
+{
+	u8 tmp;
+	u8 val;
+
+	switch ((int)corepll) {
+	case 20:
+		val = 0x08;
+		break;
+	case 25:
+		val = 0x0C;
+		break;
+	case 30:
+		val = 0x10;
+		break;
+	case 35:
+		val = 0x1C;
+		break;
+	case 40:
+		val = 0x14;
+		break;
+	case 45:
+		val = 0x0E;
+		break;
+	default:
+		printf("Unsupported COREPLL ratio.\n");
+		return 0;
+	}
+
+	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+	tmp = (tmp & 0xE0) | (val & 0x1F);
+	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+
+	return 1;
+}
+
+
+void read_from_px_regs(int set)
+{
+	u8 mask = 0x1C;
+	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+
+	if (set)
+		tmp = tmp | mask;
+	else
+		tmp = tmp & ~mask;
+	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+}
+
+
+void read_from_px_regs_altbank(int set)
+{
+	u8 mask = 0x04;
+	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+
+	if (set)
+		tmp = tmp | mask;
+	else
+		tmp = tmp & ~mask;
+	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+}
+
+
+void set_altbank(void)
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+	tmp ^= 0x40;
+
+	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+}
+
+
+void set_px_go(void)
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp & 0x1E;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp | 0x01;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+void set_px_go_with_watchdog(void)
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp & 0x1E;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp | 0x09;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp & 0x1E;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	/* setting VCTL[WDEN] to 0 to disable watch dog */
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp &= ~ 0x08;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	diswd, 1, 0, disable_watchdog,
+	"diswd	- Disable watchdog timer \n",
+	NULL
+);
+
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+
+ulong strfractoint(uchar *strptr)
+{
+	int i, j, retval;
+	int mulconst;
+	int intarr_len = 0, decarr_len = 0, no_dec = 0;
+	ulong intval = 0, decval = 0;
+	uchar intarr[3], decarr[3];
+
+	/* Assign the integer part to intarr[]
+	 * If there is no decimal point i.e.
+	 * if the ratio is an integral value
+	 * simply create the intarr.
+	 */
+	i = 0;
+	while (strptr[i] != 46) {
+		if (strptr[i] == 0) {
+			no_dec = 1;
+			break;
+		}
+		intarr[i] = strptr[i];
+		i++;
+	}
+
+	/* Assign length of integer part to intarr_len. */
+	intarr_len = i;
+	intarr[i] = '\0';
+
+	if (no_dec) {
+		/* Currently needed only for single digit corepll ratios */
+		mulconst=10;
+		decval = 0;
+	} else {
+		j = 0;
+		i++; /* Skipping the decimal point */
+		while ((strptr[i] > 47) && (strptr[i] < 58)) {
+			decarr[j] = strptr[i];
+			i++;
+			j++;
+		}
+
+		decarr_len = j;
+		decarr[j] = '\0';
+
+		mulconst = 1;
+		for (i = 0; i < decarr_len; i++)
+			mulconst *= 10;
+		decval = simple_strtoul(decarr, NULL, 10);
+	}
+
+	intval = simple_strtoul(intarr, NULL, 10);
+	intval = intval * mulconst;
+
+	retval = intval + decval;
+
+	return retval;
+}
diff --git a/board/mpc8641hpcn/pixis.h b/board/mpc8641hpcn/pixis.h
new file mode 100644
index 0000000..cd9a45d
--- /dev/null
+++ b/board/mpc8641hpcn/pixis.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern int set_px_sysclk(ulong sysclk);
+extern int set_px_mpxpll(ulong mpxpll);
+extern int set_px_corepll(ulong corepll);
+extern void read_from_px_regs(int set);
+extern void read_from_px_regs_altbank(int set);
+extern void set_altbank(void);
+extern void set_px_go(void);
+extern void set_px_go_with_watchdog(void);
+extern int disable_watchdog(cmd_tbl_t *cmdtp,
+			    int flag, int argc, char *argv[]);
+extern ulong strfractoint(uchar *strptr);
diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds
index c5c40e7..b34de8e 100644
--- a/board/mpc8641hpcn/u-boot.lds
+++ b/board/mpc8641hpcn/u-boot.lds
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2004, Freescale, Inc.
  * (C) Copyright 2002,2003, Motorola,Inc.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  *
  * See file CREDITS for list of people who contributed to this
  * project.