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authorTom Rini <trini@ti.com>2015-01-30 13:56:15 -0500
committerTom Rini <trini@ti.com>2015-01-30 13:56:15 -0500
commita0573d19885236ba03d412f7788104f75f0dea64 (patch)
tree95432f4b7dba3fb9fd4a7d8a4fc61330c7d8c734 /board
parent8e3da9dd113699eed2fa05fcde3c55a2ff410913 (diff)
parenteef88dfb3e16e4631e078f42714dbcef3216e3e1 (diff)
downloadu-boot-imx-a0573d19885236ba03d412f7788104f75f0dea64.zip
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Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'board')
-rw-r--r--board/imgtec/malta/malta.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 78c4bd4..79562f7 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <ide.h>
#include <netdev.h>
#include <pci.h>
#include <pci_gt64120.h>
@@ -123,6 +124,7 @@ void _machine_restart(void)
reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
__raw_writel(GORESET, reset_base);
+ mdelay(1000);
}
int board_early_init_f(void)
@@ -217,4 +219,22 @@ void pci_init_board(void)
pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+
+ bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB, 0);
+ if (bdf == -1)
+ panic("Failed to find PIIX4 IDE controller\n");
+
+ /* enable bus master & IO access */
+ val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+ pci_write_config_dword(bdf, PCI_COMMAND, val32);
+
+ /* set latency */
+ pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
+
+ /* enable IDE/ATA */
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
+ PCI_CFG_PIIX4_IDETIM_IDE);
}