Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

4 files changed, 76 insertions, 14 deletions

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 23874d2..158f7bb 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CONFIG_SYS_BCSR3_PCIE		0x10
+	struct board_bcsr {
+		u8	board_id;
+		u8	cpld_rev;
+		u8	led_user;
+		u8	board_status;
+		u8	reset_ctrl;
+		u8	flash_ctrl;
+		u8	eth_ctrl;
+		u8	usb_ctrl;
+		u8	irq_ctrl;
+};
 
 #define BOARD_CANYONLANDS_PCIE	1
 #define BOARD_CANYONLANDS_SATA	2
@@ -112,6 +122,9 @@ int board_early_init_f(void)
 {
 #if !defined(CONFIG_ARCHES)
 	u32 sdr0_cust0;
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+
 #endif
 
 	/*
@@ -172,14 +185,10 @@ int board_early_init_f(void)
 
 #if !defined(CONFIG_ARCHES)
 	/* Enable ethernet and take out of reset */
-	out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
+	out_8(&bcsr_data->eth_ctrl, 0) ;
 
 	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
-	out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
-
-	/* Enable USB host & USB-OTG */
-	out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
-
+	out_8(&bcsr_data->flash_ctrl, 0) ;
 	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
 
 	/* Setup PLB4-AHB bridge based on the system address map */
@@ -201,6 +210,41 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+	u8 val;
+
+	/* Enable USB host & USB-OTG */
+	val = in_8(&bcsr_data->usb_ctrl);
+	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+	out_8(&bcsr_data->usb_ctrl, val);
+
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+	u8 val;
+
+	/* Disable USB host & USB-OTG */
+	val = in_8(&bcsr_data->usb_ctrl);
+	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+	out_8(&bcsr_data->usb_ctrl, val);
+
+	return 0;
+}
+
+int usb_board_init_fail(void)
+{
+	return usb_board_stop();
+}
+#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
+
 #if !defined(CONFIG_ARCHES)
 static void canyonlands_sata_init(int board_type)
 {
@@ -244,11 +288,13 @@ int get_cpu_num(void)
 #if !defined(CONFIG_ARCHES)
 int checkboard(void)
 {
+	struct board_bcsr *bcsr_data =
+		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 	char *s = getenv("serial#");
 
 	if (pvr_460ex()) {
 		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
-		if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
+		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
 			gd->board_type = BOARD_CANYONLANDS_PCIE;
 		else
 			gd->board_type = BOARD_CANYONLANDS_SATA;
@@ -268,7 +314,7 @@ int checkboard(void)
 		break;
 	}
 
-	printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
+	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
 
 	if (s != NULL) {
 		puts(", serial# ");
diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
index c00bf16..98ab49f 100644
--- a/board/t3corp/chip_config.c
+++ b/board/t3corp/chip_config.c
@@ -27,13 +27,27 @@
 
 struct ppc4xx_config ppc4xx_config_val[] = {
 	{
-		"600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		"600-67", "CPU: 600 PLB: 200 OPB:  67 EBC:  67",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
 		{
 			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
 			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
 	{
+		"667", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
+		{
+			0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
+			0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
 		"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
 		{
 			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index 4a4217f..ecd35ff 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -81,11 +81,13 @@ tlbtab:
 	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
 
 	/* TLB-entry for FPGA(s) */
-	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
 		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+		 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
 		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
 		 AC_RW | SA_IG)
 
 	/* TLB-entry for OCM */
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
index 8ffa321..ddf5897 100644
--- a/board/t3corp/t3corp.c
+++ b/board/t3corp/t3corp.c
@@ -45,7 +45,7 @@ int board_early_init_f(void)
 	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 	mtdcr(UIC1ER, 0x00000000);	/* disable all */
 	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1PR, 0x7fffffff);	/* per ref-board manual */
 	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
 	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(UIC1SR, 0xffffffff);	/* clear all */