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authorpekon gupta <pekon@ti.com>2014-07-22 16:03:24 +0530
committerTom Rini <trini@ti.com>2014-08-25 10:48:12 -0400
commit9352697aa060e9b1b5d891e4490fdfa6f5ba6114 (patch)
tree3b99b784f58c2f384f4fe18e562b6911d8f130f9 /board
parent54a97d2849979acd84a0475486edf0d0c18e47c7 (diff)
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board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
Diffstat (limited to 'board')
-rw-r--r--board/ti/dra7xx/mux_data.h36
1 files changed, 34 insertions, 2 deletions
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 1ea236b..5bc4fc9 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -21,6 +21,37 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+#if defined(CONFIG_NOR)
+ /* NOR only pin-mux */
+ {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
+ {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
+ {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
+ {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
+ {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
+ {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
+ {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
+ {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
+ {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
+ {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
+ {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
+ {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
+ {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
+ {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
+ {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
+ {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
+ {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
+ {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
+ {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
+ {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
+ {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
+ {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
+ {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
+ {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
+ {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
+ {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
+ {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
+#else
+ /* eMMC pinmux */
{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
@@ -31,6 +62,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+#endif
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
@@ -68,7 +100,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{VIN2A_D21, (IEN | M3)},
{VIN2A_D22, (IEN | M3)},
{VIN2A_D23, (IEN | M3)},
-#ifdef CONFIG_NAND
+#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
/* NAND / NOR pin-mux */
{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
{GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
@@ -105,7 +137,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
-#endif /* CONFIG_NAND */
+#endif /* CONFIG_NAND || CONFIG_NOR */
{USB2_DRVVBUS, (M0 | IEN | FSC) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */