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authorWolfgang Denk <wd@denx.de>2011-10-28 00:15:19 +0200
committerWolfgang Denk <wd@denx.de>2011-10-28 00:15:19 +0200
commit87a5d601031652293ec4b729fdb7ee01bbd940a8 (patch)
tree91ede3ee45b228736c1876a700024782d7bc2032 /board
parent606a76f8ef479e42ae4d06f8f3ce87e9a1c72acf (diff)
parent37fc0ed268dc5acacd3a83adafa26eb1a84e90af (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Diffstat (limited to 'board')
-rw-r--r--board/Marvell/aspenite/aspenite.c1
-rw-r--r--board/Marvell/dkb/dkb.c43
-rw-r--r--board/Marvell/dreamplug/Makefile54
-rw-r--r--board/Marvell/dreamplug/dreamplug.c151
-rw-r--r--board/Marvell/dreamplug/dreamplug.h42
-rw-r--r--board/Marvell/dreamplug/kwbimage.cfg163
-rw-r--r--board/Marvell/gplugd/gplugd.c13
-rw-r--r--board/Marvell/guruplug/guruplug.c1
-rw-r--r--board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c1
-rw-r--r--board/Marvell/openrd/openrd.c1
-rw-r--r--board/Marvell/rd6281a/rd6281a.c1
-rw-r--r--board/Marvell/sheevaplug/sheevaplug.c1
-rw-r--r--board/davedenx/qong/qong.c107
-rw-r--r--board/davinci/da8xxevm/da830evm.c63
-rw-r--r--board/davinci/da8xxevm/da850evm.c23
-rw-r--r--board/efikamx/efikamx.c51
-rw-r--r--board/freescale/mx31ads/mx31ads.c16
-rw-r--r--board/freescale/mx31pdk/mx31pdk.c14
-rw-r--r--board/freescale/mx35pdk/mx35pdk.c18
-rw-r--r--board/freescale/mx51evk/mx51evk.c47
-rw-r--r--board/freescale/mx53evk/mx53evk.c17
-rw-r--r--board/highbank/Makefile49
-rw-r--r--board/highbank/highbank.c57
-rw-r--r--board/imx31_phycore/imx31_phycore.c41
-rw-r--r--board/karo/tx25/tx25.c2
-rw-r--r--board/keymile/km_arm/km_arm.c1
-rw-r--r--board/logicpd/imx27lite/imx27lite.c6
-rw-r--r--board/logicpd/imx31_litekit/imx31_litekit.c30
-rw-r--r--board/logicpd/zoom2/debug_board.c1
-rw-r--r--board/logicpd/zoom2/zoom2.c1
-rw-r--r--board/nvidia/common/board.c243
-rw-r--r--board/nvidia/common/board.h4
-rw-r--r--board/nvidia/harmony/harmony.c26
-rw-r--r--board/nvidia/seaboard/seaboard.c35
-rw-r--r--board/overo/overo.c14
-rw-r--r--board/overo/overo.h8
-rw-r--r--board/samsung/goni/goni.c4
-rw-r--r--board/ti/am335x/Makefile43
-rw-r--r--board/ti/am335x/common_def.h24
-rw-r--r--board/ti/am335x/evm.c48
-rw-r--r--board/ti/am335x/mux.c278
-rw-r--r--board/ti/beagle/beagle.c6
-rw-r--r--board/ti/panda/panda.c17
-rw-r--r--board/ti/panda/panda_mux_data.h14
-rw-r--r--board/timll/devkit8000/devkit8000.c2
-rw-r--r--board/ttcontrol/vision2/vision2.c33
46 files changed, 1441 insertions, 374 deletions
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
index 34ac7aa..3be33bf 100644
--- a/board/Marvell/aspenite/aspenite.c
+++ b/board/Marvell/aspenite/aspenite.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <mvmfp.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/mfp.h>
#include <asm/arch/armada100.h>
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
index 00f73e7..4a9abee 100644
--- a/board/Marvell/dkb/dkb.c
+++ b/board/Marvell/dkb/dkb.c
@@ -24,8 +24,12 @@
#include <common.h>
#include <mvmfp.h>
+#include <i2c.h>
#include <asm/arch/mfp.h>
#include <asm/arch/cpu.h>
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -40,6 +44,20 @@ int board_early_init_f(void)
MFP53_CI2C_SCL,
MFP54_CI2C_SDA,
+ /* MMC1 */
+ MFP_MMC1_DAT7,
+ MFP_MMC1_DAT6,
+ MFP_MMC1_DAT5,
+ MFP_MMC1_DAT4,
+ MFP_MMC1_DAT3,
+ MFP_MMC1_DAT2,
+ MFP_MMC1_DAT1,
+ MFP_MMC1_DAT0,
+ MFP_MMC1_CMD,
+ MFP_MMC1_CLK,
+ MFP_MMC1_CD,
+ MFP_MMC1_WP,
+
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
@@ -56,3 +74,28 @@ int board_init(void)
gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
return 0;
}
+
+#ifdef CONFIG_GENERIC_MMC
+#define I2C_SLAVE_ADDR 0x34
+#define LDO13_REG 0x28
+#define LDO_V30 0x6
+#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
+#define LDO_EN 0x1
+int board_mmc_init(bd_t *bd)
+{
+ ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+ u8 i, data;
+
+ /* set LDO 13 to 3.0v */
+ data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
+ i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
+
+ for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+ if (mv_sdh_init(mmc_base_address[i], 0, 0,
+ SDHCI_QUIRK_32BIT_DMA_ADDR))
+ return 1;
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile
new file mode 100644
index 0000000..9ee5406
--- /dev/null
+++ b/board/Marvell/dreamplug/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := dreamplug.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c
new file mode 100644
index 0000000..13b4013
--- /dev/null
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "dreamplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
+ DREAMPLUG_OE_VAL_HIGH,
+ DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_SPI_SCn, /* SPI Flash */
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD, /* Serial */
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK, /* SDIO Slot */
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0, /* Gigabit Ethernet */
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GE1_15,
+ MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_TDM_SPI_SCK,
+ MPP41_TDM_SPI_MISO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO, /* Bluetooth LED */
+ MPP48_GPIO, /* Wifi LED */
+ MPP49_GPIO, /* Wifi AP LED */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1116_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ /* configure and initialize both PHY's */
+ mv_phy_88e1116_init("egiga0");
+ mv_phy_88e1116_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/dreamplug/dreamplug.h b/board/Marvell/dreamplug/dreamplug.h
new file mode 100644
index 0000000..ad5ffcf
--- /dev/null
+++ b/board/Marvell/dreamplug/dreamplug.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DREAMPLUG_H
+#define __DREAMPLUG_H
+
+#define DREAMPLUG_OE_LOW (~(0))
+#define DREAMPLUG_OE_HIGH (~(0))
+#define DREAMPLUG_OE_VAL_LOW 0
+#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1116_MAC_CTRL2_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DREAMPLUG_H */
diff --git a/board/Marvell/dreamplug/kwbimage.cfg b/board/Marvell/dreamplug/kwbimage.cfg
new file mode 100644
index 0000000..ca9cd74
--- /dev/null
+++ b/board/Marvell/dreamplug/kwbimage.cfg
@@ -0,0 +1,163 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index b4f7f81..a697c19 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -30,6 +30,7 @@
#include <common.h>
#include <mvmfp.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/mfp.h>
#include <asm/arch/armada100.h>
#include <asm/gpio.h>
@@ -72,6 +73,12 @@ int board_early_init_f(void)
MFP101_ETH_MDIO,
MFP103_ETH_RXDV,
+ /* SSP2 */
+ MFP107_SSP2_RXD,
+ MFP108_SSP2_TXD,
+ MFP110_SSP2_CS,
+ MFP111_SSP2_CLK,
+
MFP_EOC /*End of configuration*/
};
/* configure MFP's */
@@ -81,6 +88,9 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct armd1apb2_registers *apb2_regs =
+ (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
+
/* arch number of Board */
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
@@ -90,6 +100,9 @@ int board_init(void)
udelay(10);
/* Deassert PHY_RST# */
gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
+
+ /* Enable SSP2 clock */
+ writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
return 0;
}
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index 1f0e67a..057c558 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <miiphy.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "guruplug.h"
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index 80fd20b..4c41f3b 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -26,6 +26,7 @@
#include <common.h>
#include <netdev.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "mv88f6281gtw_ge.h"
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
index 87939de..2a10e69 100644
--- a/board/Marvell/openrd/openrd.c
+++ b/board/Marvell/openrd/openrd.c
@@ -29,6 +29,7 @@
#include <common.h>
#include <miiphy.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "openrd.h"
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index ecdea82..9c768bf 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "rd6281a.h"
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index d7dc80c..71e6793 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <miiphy.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "sheevaplug.h"
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 99432ed..5b2830c 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -25,8 +25,10 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <nand.h>
+#include <pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
#include "qong_fpga.h"
@@ -41,7 +43,7 @@ void hw_watchdog_reset(void)
}
#endif
-int dram_init (void)
+int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
@@ -58,14 +60,20 @@ static void qong_fpga_reset(void)
udelay(300);
}
-int board_early_init_f (void)
+int board_early_init_f(void)
{
#ifdef CONFIG_QONG_FPGA
- /* CS1: FPGA/Network Controller/GPIO */
- /* 16-bit, no DTACK */
- __REG(CSCR_U(1)) = 0x00000A01;
- __REG(CSCR_L(1)) = 0x20040501;
- __REG(CSCR_A(1)) = 0x04020C00;
+ /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
+ static const struct mxc_weimcs cs1 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(1, &cs1);
/* setup pins for FPGA */
mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
@@ -141,55 +149,21 @@ int board_early_init_f (void)
}
-int board_init (void)
+int board_init(void)
{
/* Chip selects */
/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
- __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
- (0 << 30) | /* WP */
- (0 << 28) | /* BCD */
- (0 << 24) | /* BCS */
- (0 << 22) | /* PSZ */
- (0 << 21) | /* PME */
- (0 << 20) | /* SYNC */
- (0 << 16) | /* DOL */
- (3 << 14) | /* CNC */
- (21 << 8) | /* WSC */
- (0 << 7) | /* EW */
- (0 << 4) | /* WWS */
- (6 << 0) /* EDC */
- );
-
- __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
- (1 << 24) | /* OEN */
- (3 << 20) | /* EBWA */
- (3 << 16) | /* EBWN */
- (1 << 12) | /* CSA */
- (1 << 11) | /* EBC */
- (5 << 8) | /* DSZ */
- (1 << 4) | /* CSN */
- (0 << 3) | /* PSR */
- (0 << 2) | /* CRE */
- (0 << 1) | /* WRAP */
- (1 << 0) /* CSEN */
- );
-
- __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
- (1 << 24) | /* EBRN */
- (2 << 20) | /* RWA */
- (2 << 16) | /* RWN */
- (0 << 15) | /* MUM */
- (0 << 13) | /* LAH */
- (2 << 10) | /* LBN */
- (0 << 8) | /* LBA */
- (0 << 6) | /* DWW */
- (0 << 4) | /* DCT */
- (0 << 3) | /* WWU */
- (0 << 2) | /* AGE */
- (0 << 1) | /* CNC2 */
- (0 << 0) /* FCE */
- );
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_QONG;
@@ -203,11 +177,15 @@ int board_init (void)
int board_late_init(void)
{
u32 val;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Enable RTC battery */
- val = pmic_reg_read(REG_POWER_CTL0);
- pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
- pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+ pmic_reg_read(p, REG_POWER_CTL0, &val);
+ pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
+ pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
mxc_hw_watchdog_enable();
@@ -216,13 +194,13 @@ int board_late_init(void)
return 0;
}
-int checkboard (void)
+int checkboard(void)
{
printf("Board: DAVE/DENX Qong\n");
return 0;
}
-int misc_init_r (void)
+int misc_init_r(void)
{
#ifdef CONFIG_QONG_FPGA
u32 tmp;
@@ -247,11 +225,18 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
static void board_nand_setup(void)
{
-
/* CS3: NAND 8-bit */
- __REG(CSCR_U(3)) = 0x00004f00;
- __REG(CSCR_L(3)) = 0x20013b31;
- __REG(CSCR_A(3)) = 0x00020800;
+ static const struct mxc_weimcs cs3 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(3, &cs3);
+
__REG(IOMUXC_GPR) |= 1 << 13;
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
index 0650653..2021e73 100644
--- a/board/davinci/da8xxevm/da830evm.c
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -40,6 +40,8 @@
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/nand_defs.h>
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -98,6 +100,56 @@ static const struct pinmux_config i2c_pins[] = {
{ pinmux(8), 2, 4 }
};
+#ifdef CONFIG_USE_NAND
+/* NAND pin muxer settings */
+const struct pinmux_config aemif_pins[] = {
+ { pinmux(13), 1, 6 },
+ { pinmux(13), 1, 7 },
+ { pinmux(14), 1, 0 },
+ { pinmux(14), 1, 1 },
+ { pinmux(14), 1, 2 },
+ { pinmux(14), 1, 3 },
+ { pinmux(14), 1, 4 },
+ { pinmux(14), 1, 5 },
+ { pinmux(14), 1, 6 },
+ { pinmux(14), 1, 7 },
+ { pinmux(15), 1, 0 },
+ { pinmux(15), 1, 1 },
+ { pinmux(15), 1, 2 },
+ { pinmux(15), 1, 3 },
+ { pinmux(15), 1, 4 },
+ { pinmux(15), 1, 5 },
+ { pinmux(15), 1, 6 },
+ { pinmux(15), 1, 7 },
+ { pinmux(16), 1, 0 },
+ { pinmux(16), 1, 1 },
+ { pinmux(16), 1, 2 },
+ { pinmux(16), 1, 3 },
+ { pinmux(16), 1, 4 },
+ { pinmux(16), 1, 5 },
+ { pinmux(16), 1, 6 },
+ { pinmux(16), 1, 7 },
+ { pinmux(17), 1, 0 },
+ { pinmux(17), 1, 1 },
+ { pinmux(17), 1, 2 },
+ { pinmux(17), 1, 3 },
+ { pinmux(17), 1, 4 },
+ { pinmux(17), 1, 5 },
+ { pinmux(17), 1, 6 },
+ { pinmux(17), 1, 7 },
+ { pinmux(18), 1, 0 },
+ { pinmux(18), 1, 1 },
+ { pinmux(18), 1, 2 },
+ { pinmux(18), 1, 3 },
+ { pinmux(18), 1, 4 },
+ { pinmux(18), 1, 5 },
+ { pinmux(18), 1, 6 },
+ { pinmux(18), 1, 7 },
+ { pinmux(10), 1, 0 }
+};
+#endif
+
+
/* USB0_DRVVBUS pin muxer settings */
static const struct pinmux_config usb_pins[] = {
{ pinmux(9), 1, 1 }
@@ -114,6 +166,7 @@ static const struct pinmux_resource pinmuxes[] = {
#endif
#ifdef CONFIG_USE_NAND
PINMUX_ITEM(emifa_nand_pins),
+ PINMUX_ITEM(aemif_pins),
#endif
#if defined(CONFIG_DRIVER_TI_EMAC)
PINMUX_ITEM(emac_pins),
@@ -184,6 +237,16 @@ int board_init(void)
return(0);
}
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_DRIVER_TI_EMAC)
#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 46924d3..e0a3bbe 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -278,6 +278,20 @@ u32 get_board_rev(void)
return rev;
}
+int board_early_init_f(void)
+{
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ return 0;
+}
+
int board_init(void)
{
#ifdef CONFIG_USE_NOR
@@ -310,15 +324,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
- /*
- * Power on required peripherals
- * ARM does not have access by default to PSC0 and PSC1
- * assuming here that the DSP bootloader has set the IOPU
- * such that PSC access is available to ARM
- */
- if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
- return 1;
-
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 0c4e24b..b78bf6c 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -34,6 +34,7 @@
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
@@ -205,34 +206,38 @@ static void power_init(void)
{
unsigned int val;
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Write needed to Power Gate 2 register */
- val = pmic_reg_read(REG_POWER_MISC);
+ pmic_reg_read(p, REG_POWER_MISC, &val);
val &= ~PWGT2SPIEN;
- pmic_reg_write(REG_POWER_MISC, val);
+ pmic_reg_write(p, REG_POWER_MISC, val);
/* Externally powered */
- val = pmic_reg_read(REG_CHARGE);
+ pmic_reg_read(p, REG_CHARGE, &val);
val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
- pmic_reg_write(REG_CHARGE, val);
+ pmic_reg_write(p, REG_CHARGE, val);
/* power up the system first */
- pmic_reg_write(REG_POWER_MISC, PWUP);
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
/* Set core voltage to 1.1V */
- val = pmic_reg_read(REG_SW_0);
+ pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
- pmic_reg_write(REG_SW_0, val);
+ pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
- val = pmic_reg_read(REG_SW_1);
+ pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(REG_SW_1, val);
+ pmic_reg_write(p, REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
- val = pmic_reg_read(REG_SW_2);
+ pmic_reg_read(p, REG_SW_2, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_write(p, REG_SW_2, val);
udelay(50);
/* Raise the core frequency to 800MHz */
@@ -240,46 +245,46 @@ static void power_init(void)
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
/* Setup the switcher mode for SW1 & SW2*/
- val = pmic_reg_read(REG_SW_4);
+ pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(REG_SW_4, val);
+ pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg_read(REG_SW_5);
+ pmic_reg_read(p, REG_SW_5, &val);
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
(SWMODE_MASK << SWMODE4_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
- pmic_reg_write(REG_SW_5, val);
+ pmic_reg_write(p, REG_SW_5, val);
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
- val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
- pmic_reg_write(REG_SETTING_0, val);
+ pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- val = pmic_reg_read(REG_SETTING_1);
+ pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
- pmic_reg_write(REG_SETTING_1, val);
+ pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
- val = pmic_reg_read(REG_POWER_CTL2);
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
val |= WDIRESET;
- pmic_reg_write(REG_POWER_CTL2, val);
+ pmic_reg_write(p, REG_POWER_CTL2, val);
udelay(2500);
}
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
index 4dd1e63..1def0d9 100644
--- a/board/freescale/mx31ads/mx31ads.c
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -25,6 +25,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,9 +49,16 @@ int board_early_init_f(void)
* the only non-zero field "Wait State Control" is set to half the
* default value.
*/
- __REG(CSCR_U(0)) = 0x00000f00;
- __REG(CSCR_L(0)) = 0x10000D03;
- __REG(CSCR_A(0)) = 0x00720900;
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
@@ -104,7 +112,7 @@ int board_init(void)
return 0;
}
-int checkboard (void)
+int checkboard(void)
{
printf("Board: MX31ADS\n");
return 0;
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 276d451..0e7e0ce 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -28,6 +28,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -50,9 +51,16 @@ int dram_init(void)
int board_early_init_f(void)
{
/* CS5: CPLD incl. network controller */
- __REG(CSCR_U(5)) = 0x0000d843;
- __REG(CSCR_L(5)) = 0x22252521;
- __REG(CSCR_A(5)) = 0x22220a00;
+ static const struct mxc_weimcs cs5 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(5, &cs5);
/* Setup UART1 and SPI2 pins */
mx31_uart1_hw_init();
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index 2ce6e8e..a5b51a0 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -30,6 +30,7 @@
#include <asm/arch/mx35_pins.h>
#include <asm/arch/iomux.h>
#include <i2c.h>
+#include <pmic.h>
#include <fsl_pmic.h>
#include <mc9sdz60.h>
#include <mc13892.h>
@@ -202,9 +203,10 @@ int board_init(void)
static inline int pmic_detect(void)
{
- int id;
+ unsigned int id;
+ struct pmic *p = get_pmic();
- id = pmic_reg_read(REG_IDENTIFICATION);
+ pmic_reg_read(p, REG_IDENTIFICATION, &id);
id = (id >> 6) & 0x7;
if (id == 0x7)
@@ -225,15 +227,19 @@ int board_late_init(void)
{
u8 val;
u32 pmic_val;
+ struct pmic *p;
+ pmic_init();
if (pmic_detect()) {
+ p = get_pmic();
mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
MUX_CONFIG_ALT1);
- pmic_val = pmic_reg_read(REG_SETTING_0);
- pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
- pmic_val = pmic_reg_read(REG_MODE_0);
- pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
+ pmic_reg_read(p, REG_SETTING_0, &pmic_val);
+ pmic_reg_write(p, REG_SETTING_0,
+ pmic_val | VO_1_30V | VO_1_50V);
+ pmic_reg_read(p, REG_MODE_0, &pmic_val);
+ pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index f998610..2a0dad0 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -32,6 +32,7 @@
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
@@ -182,34 +183,38 @@ static void power_init(void)
{
unsigned int val;
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Write needed to Power Gate 2 register */
- val = pmic_reg_read(REG_POWER_MISC);
+ pmic_reg_read(p, REG_POWER_MISC, &val);
val &= ~PWGT2SPIEN;
- pmic_reg_write(REG_POWER_MISC, val);
+ pmic_reg_write(p, REG_POWER_MISC, val);
/* Externally powered */
- val = pmic_reg_read(REG_CHARGE);
+ pmic_reg_read(p, REG_CHARGE, &val);
val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
- pmic_reg_write(REG_CHARGE, val);
+ pmic_reg_write(p, REG_CHARGE, val);
/* power up the system first */
- pmic_reg_write(REG_POWER_MISC, PWUP);
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
/* Set core voltage to 1.1V */
- val = pmic_reg_read(REG_SW_0);
+ pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
- pmic_reg_write(REG_SW_0, val);
+ pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
- val = pmic_reg_read(REG_SW_1);
+ pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(REG_SW_1, val);
+ pmic_reg_write(p, REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
- val = pmic_reg_read(REG_SW_2);
+ pmic_reg_read(p, REG_SW_2, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_write(p, REG_SW_2, val);
udelay(50);
/* Raise the core frequency to 800MHz */
@@ -217,36 +222,36 @@ static void power_init(void)
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
/* Setup the switcher mode for SW1 & SW2*/
- val = pmic_reg_read(REG_SW_4);
+ pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(REG_SW_4, val);
+ pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg_read(REG_SW_5);
+ pmic_reg_read(p, REG_SW_5, &val);
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
(SWMODE_MASK << SWMODE4_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
- pmic_reg_write(REG_SW_5, val);
+ pmic_reg_write(p, REG_SW_5, val);
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
- val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
- pmic_reg_write(REG_SETTING_0, val);
+ pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- val = pmic_reg_read(REG_SETTING_1);
+ pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
- pmic_reg_write(REG_SETTING_1, val);
+ pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
gpio_direction_output(46, 0);
@@ -257,7 +262,7 @@ static void power_init(void)
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
udelay(500);
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index fd821c0..eab9c5f 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -32,6 +32,7 @@
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
#include <mc13892.h>
@@ -124,12 +125,16 @@ static void setup_i2c(unsigned int port_number)
void power_init(void)
{
unsigned int val;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Set VDDA to 1.25V */
- val = pmic_reg_read(REG_SW_2);
+ pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_25;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_write(p, REG_SW_2, val);
/*
* Need increase VCC and VDDA to 1.3V
@@ -137,16 +142,16 @@ void power_init(void)
*/
if (is_soc_rev(CHIP_REV_2_0) == 0) {
/* Set VCC to 1.3V for TO2 */
- val = pmic_reg_read(REG_SW_1);
+ pmic_reg_read(p, REG_SW_1, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
- pmic_reg_write(REG_SW_1, val);
+ pmic_reg_write(p, REG_SW_1, val);
/* Set VDDA to 1.3V for TO2 */
- val = pmic_reg_read(REG_SW_2);
+ pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_write(p, REG_SW_2, val);
}
}
diff --git a/board/highbank/Makefile b/board/highbank/Makefile
new file mode 100644
index 0000000..d5b8362
--- /dev/null
+++ b/board/highbank/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := highbank.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
new file mode 100644
index 0000000..8db8a2b
--- /dev/null
+++ b/board/highbank/highbank.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+
+#include <asm/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ ahci_init(0xffe08000);
+ scsi_scan(1);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = SZ_512M;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 47f1a8d..c165590 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -27,6 +27,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -49,17 +50,39 @@ int board_init(void)
int board_early_init_f(void)
{
- __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
- __REG(CSCR_L(0)) = 0x10000d03;
- __REG(CSCR_A(0)) = 0x00720900;
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
+ };
+
+ /* CS1: Network Controller */
+ static const struct mxc_weimcs cs1 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
- __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
- __REG(CSCR_L(1)) = 0x444a4541;
- __REG(CSCR_A(1)) = 0x44443302;
+ /* CS4: SRAM */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
+ };
- __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
- __REG(CSCR_L(4)) = 0x22252521;
- __REG(CSCR_A(4)) = 0x22220a00;
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(1, &cs1);
+ mxc_setup_weimcs(4, &cs4);
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
index ec83f99..d3d8ea5 100644
--- a/board/karo/tx25/tx25.c
+++ b/board/karo/tx25/tx25.c
@@ -151,7 +151,7 @@ int board_late_init(void)
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 67f158c..6ef5e5d 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -34,6 +34,7 @@
#include <netdev.h>
#include <miiphy.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
index 2b273ac..8a5015c 100644
--- a/board/logicpd/imx27lite/imx27lite.c
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init (void)
+int board_init(void)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
#if defined(CONFIG_SYS_NAND_LARGEPAGE)
@@ -64,7 +64,7 @@ int board_init (void)
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
@@ -86,7 +86,7 @@ void dram_init_banksize(void)
int checkboard(void)
{
- puts ("Board: ");
+ puts("Board: ");
puts(CONFIG_BOARDNAME);
return 0;
}
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index 7214008..b038e0d 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -26,6 +26,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,13 +40,28 @@ int dram_init(void)
int board_early_init_f(void)
{
- __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
- __REG(CSCR_L(0)) = 0xa0330d01;
- __REG(CSCR_A(0)) = 0x00220800;
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
- __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
- __REG(CSCR_L(4)) = 0x444a4541;
- __REG(CSCR_A(4)) = 0x44443302;
+ /* CS4: Network Controller */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(4, &cs4);
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
@@ -75,7 +91,7 @@ int board_init(void)
return 0;
}
-int checkboard (void)
+int checkboard(void)
{
printf("Board: i.MX31 Litekit\n");
return 0;
diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c
index 33aa600..071e7f9 100644
--- a/board/logicpd/zoom2/debug_board.c
+++ b/board/logicpd/zoom2/debug_board.c
@@ -40,7 +40,6 @@ static void zoom2_debug_board_detect (void)
*/
gpio_direction_input(158);
val = gpio_get_value(158);
- gpio_free(158);
}
if (!val)
diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c
index 21964c2..be3083d 100644
--- a/board/logicpd/zoom2/zoom2.c
+++ b/board/logicpd/zoom2/zoom2.c
@@ -95,7 +95,6 @@ void zoom2_identify(void)
gpio_direction_input(94);
val = gpio_get_value(94);
- gpio_free(94);
if (val)
revision = ZOOM2_REVISION_BETA;
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 160dac8..d13537d 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -43,24 +43,6 @@ const struct tegra2_sysinfo sysinfo = {
CONFIG_TEGRA2_BOARD_STRING
};
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- /* Initialize periph clocks */
- clock_init();
-
- /* Initialize periph pinmuxes */
- pinmux_init();
-
- /* Initialize periph GPIOs */
- gpio_init();
-
- /* Init UART, scratch regs, and start CPU */
- tegra2_start();
- return 0;
-}
-#endif /* EARLY_INIT */
-
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
@@ -70,62 +52,31 @@ int timer_init(void)
return 0;
}
-/*
- * Routine: clock_init_uart
- * Description: init the PLL and clock for the UART(s)
- */
-static void clock_init_uart(void)
+static void enable_uart(enum periph_id pid)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
- u32 reg;
-
- reg = readl(&pll->pll_base);
- if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
- /* Override pllp setup for 216MHz operation. */
- reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
- (1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
- reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
- writel(reg, &pll->pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
-
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
- }
-
-#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
/* Assert UART reset and enable clock */
- reset_set_enable(PERIPH_ID_UART1, 1);
- clock_enable(PERIPH_ID_UART1);
-
- /* Enable pllp_out0 to UART */
- reg = readl(&clkrst->crc_clk_src_uarta);
- reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
- writel(reg, &clkrst->crc_clk_src_uarta);
+ reset_set_enable(pid, 1);
+ clock_enable(pid);
+ clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
- reset_set_enable(PERIPH_ID_UART1, 0);
+ reset_set_enable(pid, 0);
+}
+
+/*
+ * Routine: clock_init_uart
+ * Description: init the PLL and clock for the UART(s)
+ */
+static void clock_init_uart(void)
+{
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+ enable_uart(PERIPH_ID_UART1);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
- /* Assert UART reset and enable clock */
- reset_set_enable(PERIPH_ID_UART4, 1);
- clock_enable(PERIPH_ID_UART4);
-
- /* Enable pllp_out0 to UART */
- reg = readl(&clkrst->crc_clk_src_uartd);
- reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
- writel(reg, &clkrst->crc_clk_src_uartd);
-
- /* wait for 2us */
- udelay(2);
-
- /* De-assert reset to UART */
- reset_set_enable(PERIPH_ID_UART4, 0);
+ enable_uart(PERIPH_ID_UART4);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
@@ -135,66 +86,29 @@ static void clock_init_uart(void)
*/
static void pin_mux_uart(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 reg;
-
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
- reg = readl(&pmt->pmt_ctl_c);
- reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
- writel(reg, &pmt->pmt_ctl_c);
+ pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PIN_IRRX);
- pinmux_tristate_disable(PIN_IRTX);
+ pinmux_tristate_disable(PINGRP_IRRX);
+ pinmux_tristate_disable(PINGRP_IRTX);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
- reg = readl(&pmt->pmt_ctl_b);
- reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
- writel(reg, &pmt->pmt_ctl_b);
+ pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
- pinmux_tristate_disable(PIN_GMC);
+ pinmux_tristate_disable(PINGRP_GMC);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
+#ifdef CONFIG_TEGRA2_MMC
/*
* Routine: clock_init_mmc
* Description: init the PLL and clocks for the SDMMC controllers
*/
static void clock_init_mmc(void)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- /* Do the SDMMC resets/clock enables */
- reset_set_enable(PERIPH_ID_SDMMC4, 1);
- clock_enable(PERIPH_ID_SDMMC4);
-
- /* Enable pllp_out0 to SDMMC4 */
- reg = readl(&clkrst->crc_clk_src_sdmmc4);
- reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
- reg |= (10 << 1); /* n-1, 11-1 shl 1 */
- writel(reg, &clkrst->crc_clk_src_sdmmc4);
-
- /*
- * As per the Tegra2 TRM, section 5.3.4:
- * 'Wait 2 us for the clock to flush through the pipe/logic'
- */
- udelay(2);
-
- reset_set_enable(PERIPH_ID_SDMMC4, 1);
-
- reset_set_enable(PERIPH_ID_SDMMC3, 1);
- clock_enable(PERIPH_ID_SDMMC3);
-
- /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
- reg = readl(&clkrst->crc_clk_src_sdmmc3);
- reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
- reg |= (10 << 1); /* n-1, 11-1 shl 1 */
- writel(reg, &clkrst->crc_clk_src_sdmmc3);
-
- /* wait for 2us */
- udelay(2);
-
- reset_set_enable(PERIPH_ID_SDMMC3, 0);
+ clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000);
+ clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000);
}
/*
@@ -203,65 +117,25 @@ static void clock_init_mmc(void)
*/
static void pin_mux_mmc(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 reg;
-
- /* SDMMC4 */
- /* config 2, x8 on 2nd set of pins */
- reg = readl(&pmt->pmt_ctl_a);
- reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
- writel(reg, &pmt->pmt_ctl_a);
- reg = readl(&pmt->pmt_ctl_b);
- reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
- writel(reg, &pmt->pmt_ctl_b);
- reg = readl(&pmt->pmt_ctl_d);
- reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
- writel(reg, &pmt->pmt_ctl_d);
-
- pinmux_tristate_disable(PIN_ATB);
- pinmux_tristate_disable(PIN_GMA);
- pinmux_tristate_disable(PIN_GME);
-
- /* SDMMC3 */
- /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
- reg = readl(&pmt->pmt_ctl_d);
- reg &= 0xFFFF03FF;
- reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
- reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
- reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
- writel(reg, &pmt->pmt_ctl_d);
-
- pinmux_tristate_disable(PIN_SDC);
- pinmux_tristate_disable(PIN_SDD);
- pinmux_tristate_disable(PIN_SDB);
-}
-
-/*
- * Routine: clock_init
- * Description: Do individual peripheral clock reset/enables
- */
-void clock_init(void)
-{
- clock_init_uart();
-}
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pin_mux_uart();
-}
-
-/*
- * Routine: gpio_init
- * Description: Do individual peripheral GPIO configs
- */
-void gpio_init(void)
-{
- gpio_config_uart();
+ /* SDMMC4: config 3, x8 on 2nd set of pins */
+ pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+
+ pinmux_tristate_disable(PINGRP_ATB);
+ pinmux_tristate_disable(PINGRP_GMA);
+ pinmux_tristate_disable(PINGRP_GME);
+
+ /* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
+ pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
+ pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+
+ pinmux_tristate_disable(PINGRP_SDC);
+ pinmux_tristate_disable(PINGRP_SDD);
+ pinmux_tristate_disable(PINGRP_SDB);
}
+#endif
/*
* Routine: board_init
@@ -269,6 +143,9 @@ void gpio_init(void)
*/
int board_init(void)
{
+ clock_init();
+ clock_verify();
+
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@@ -283,6 +160,7 @@ int board_mmc_init(bd_t *bd)
/* Enable clocks, muxes, etc. for SDMMC controllers */
clock_init_mmc();
pin_mux_mmc();
+ gpio_config_mmc();
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
@@ -294,16 +172,25 @@ int board_mmc_init(bd_t *bd)
return 0;
}
+#endif
-/* this is a weak define that we are overriding */
-int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
{
- debug("board_mmc_getcd called\n");
- /*
- * Hard-code CD presence for now. Need to add GPIO inputs
- * for Seaboard & Harmony (& Kaen/Aebl/Wario?)
- */
- *cd = 1;
+ /* Initialize essential common plls */
+ clock_early_init();
+
+ /* Initialize UART clocks */
+ clock_init_uart();
+
+ /* Initialize periph pinmuxes */
+ pin_mux_uart();
+
+ /* Initialize periph GPIOs */
+ gpio_config_uart();
+
+ /* Init UART, scratch regs, and start CPU */
+ tegra2_start();
return 0;
}
-#endif
+#endif /* EARLY_INIT */
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 4334c02..344e702 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -25,10 +25,8 @@
#define _BOARD_H_
void tegra2_start(void);
-void clock_init(void);
-void pinmux_init(void);
-void gpio_init(void);
void gpio_config_uart(void);
+void gpio_config_mmc(void);
int tegra2_mmc_init(int dev_index, int bus_width);
#endif /* BOARD_H */
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index f1ab050..cbb30d6 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -24,6 +24,9 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra2.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
/*
* Routine: gpio_config_uart
@@ -32,3 +35,26 @@
void gpio_config_uart(void)
{
}
+
+#ifdef CONFIG_TEGRA2_MMC
+/*
+ * Routine: gpio_config_mmc
+ * Description: Set GPIOs for SD card
+ */
+void gpio_config_mmc(void)
+{
+ /* Not implemented for now */
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ debug("board_mmc_getcd called\n");
+ /*
+ * Hard-code CD presence for now. Need to add GPIO inputs
+ * for Harmony
+ */
+ *cd = 1;
+ return 0;
+}
+#endif
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 4b9a8f3..bc67d0f 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -24,7 +24,10 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra2.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
/*
* Routine: gpio_config_uart
@@ -50,3 +53,33 @@ void gpio_config_uart(void)
val |= 1 << GPIO_BIT(gp);
writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]);
}
+
+#ifdef CONFIG_TEGRA2_MMC
+/*
+ * Routine: gpio_config_mmc
+ * Description: Set GPIOs for SDMMC3 SDIO slot.
+ */
+void gpio_config_mmc(void)
+{
+ /* Set EN_VDDIO_SD (GPIO I6) */
+ gpio_direction_output(GPIO_PI6, 1);
+
+ /* Config pin as GPI for Card Detect (GPIO I5) */
+ gpio_direction_input(GPIO_PI5);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ debug("board_mmc_getcd called\n");
+ *cd = 1; /* Assume card is inserted, or eMMC */
+
+ if (IS_SD(mmc)) {
+ /* Seaboard SDMMC3 = SDIO3_CD = GPIO_PI5 */
+ if (gpio_get_value(GPIO_PI5))
+ *cd = 0;
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 850dfee..3c60b06 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -118,10 +118,6 @@ int get_board_revision(void)
revision = gpio_get_value(115) << 2 |
gpio_get_value(113) << 1 |
gpio_get_value(112);
-
- gpio_free(112);
- gpio_free(113);
- gpio_free(115);
} else {
printf("Error: unable to acquire board revision GPIOs\n");
revision = -1;
@@ -153,8 +149,7 @@ int get_sdio2_config(void)
sdio_direct = 0;
}
- gpio_free(130);
- gpio_free(139);
+ gpio_direction_input(130);
} else {
printf("Error: unable to acquire sdio2 clk GPIOs\n");
sdio_direct = -1;
@@ -233,6 +228,9 @@ int misc_init_r(void)
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ /* second lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
+ 0x2B000000, GPMC_SIZE_16M);
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
@@ -310,10 +308,6 @@ static void setup_net_chip(void)
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
- /* second lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
- GPMC_SIZE_16M);
-
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
diff --git a/board/overo/overo.h b/board/overo/overo.h
index d394f90..915f15b 100644
--- a/board/overo/overo.h
+++ b/board/overo/overo.h
@@ -160,10 +160,10 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
@@ -290,7 +290,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index e24cd29..e191bfb 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +39,9 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_GONI;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+#if defined(CONFIG_PMIC)
+ pmic_init();
+#endif
return 0;
}
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
new file mode 100644
index 0000000..d58b185
--- /dev/null
+++ b/board/ti/am335x/Makefile
@@ -0,0 +1,43 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := evm.o mux.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/am335x/common_def.h b/board/ti/am335x/common_def.h
new file mode 100644
index 0000000..1696d60
--- /dev/null
+++ b/board/ti/am335x/common_def.h
@@ -0,0 +1,24 @@
+/*
+ * common_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COMMON_DEF_H__
+#define __COMMON_DEF_H__
+
+extern void enable_uart0_pin_mux(void);
+extern void configure_evm_pin_mux(unsigned char daughter_board_id,
+ unsigned short daughter_board_profile,
+ unsigned char daughter_board_flag);
+
+#endif/*__COMMON_DEF_H__ */
diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c
new file mode 100644
index 0000000..b4eddd8
--- /dev/null
+++ b/board/ti/am335x/evm.c
@@ -0,0 +1,48 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include "common_def.h"
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+/*
+ * Basic board specific setup
+ */
+int init_basic_setup(void)
+{
+ /* Initialize the Timer */
+ init_timer();
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ enable_uart0_pin_mux();
+ init_basic_setup();
+
+ return 0;
+}
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
new file mode 100644
index 0000000..8f27409
--- /dev/null
+++ b/board/ti/am335x/mux.c
@@ -0,0 +1,278 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include "common_def.h"
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset) \
+ __raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) val /* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct module_pin_mux {
+ short reg_offset;
+ unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+/*
+ * Configure the pin mux for the module
+ */
+static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+ int i;
+
+ if (!mod_pin_mux)
+ return;
+
+ for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+ MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index aa5047c..9482c5e 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -127,10 +127,6 @@ int get_board_revision(void)
revision = gpio_get_value(173) << 2 |
gpio_get_value(172) << 1 |
gpio_get_value(171);
-
- gpio_free(171);
- gpio_free(172);
- gpio_free(173);
} else {
printf("Error: unable to acquire board revision GPIOs\n");
revision = -1;
@@ -522,8 +518,6 @@ int do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("NOT pressed.\n");
}
- gpio_free(gpio);
-
return !button;
}
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 9afed80..97320cb 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -71,9 +71,26 @@ void set_muxconf_regs_non_essential(void)
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
+ if (omap_revision() < OMAP4460_ES1_0)
+ do_set_mux(CONTROL_PADCONF_CORE,
+ core_padconf_array_non_essential_4430,
+ sizeof(core_padconf_array_non_essential_4430) /
+ sizeof(struct pad_conf_entry));
+ else
+ do_set_mux(CONTROL_PADCONF_CORE,
+ core_padconf_array_non_essential_4460,
+ sizeof(core_padconf_array_non_essential_4460) /
+ sizeof(struct pad_conf_entry));
+
do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
sizeof(wkup_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
+
+ if (omap_revision() < OMAP4460_ES1_0)
+ do_set_mux(CONTROL_PADCONF_WKUP,
+ wkup_padconf_array_non_essential_4430,
+ sizeof(wkup_padconf_array_non_essential_4430) /
+ sizeof(struct pad_conf_entry));
}
#ifdef CONFIG_GENERIC_MMC
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 63448b6..83d0c3f 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -100,7 +100,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
- {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
@@ -202,6 +201,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
};
+const struct pad_conf_entry core_padconf_array_non_essential_4430[] = {
+ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential_4460[] = {
+ {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */
+};
+
const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
{PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
{PAD1_SIM_CLK, (M0)}, /* sim_clk */
@@ -214,7 +221,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
{PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
- {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */
{PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
@@ -224,4 +230,8 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
{PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
};
+const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
+ {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */
+};
+
#endif /* _PANDA_MUX_DATA_H_ */
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index f50d113..fee0dff 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -120,7 +120,7 @@ void set_muxconf_regs(void)
MUX_DEVKIT8000();
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0);
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index e496f64..d3815b2 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -34,6 +34,7 @@
#include <asm/errno.h>
#include <i2c.h>
#include <mmc.h>
+#include <pmic.h>
#include <fsl_esdhc.h>
#include <fsl_pmic.h>
#include <mc13892.h>
@@ -313,59 +314,63 @@ static void reset_peripherals(int reset)
static void power_init_mx51(void)
{
unsigned int val;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Write needed to Power Gate 2 register */
- val = pmic_reg_read(REG_POWER_MISC);
+ pmic_reg_read(p, REG_POWER_MISC, &val);
/* enable VCAM with 2.775V to enable read from PMIC */
val = VCAMCONFIG | VCAMEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
/*
* Set switchers in Auto in NORMAL mode & STANDBY mode
* Setup the switcher mode for SW1 & SW2
*/
- val = pmic_reg_read(REG_SW_4);
+ pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(REG_SW_4, val);
+ pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg_read(REG_SW_5);
+ pmic_reg_read(p, REG_SW_5, &val);
val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
(SWMODE_MASK << SWMODE3_SHIFT));
val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
- pmic_reg_write(REG_SW_5, val);
+ pmic_reg_write(p, REG_SW_5, val);
/* Set VGEN3 to 1.8V, VCAM to 3.0V */
- val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK);
val |= VCAM_3_0;
- pmic_reg_write(REG_SETTING_0, val);
+ pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
- val = pmic_reg_read(REG_SETTING_1);
+ pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
- pmic_reg_write(REG_SETTING_1, val);
+ pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
- val = pmic_reg_read(REG_POWER_CTL2);
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
val |= WDIRESET;
- pmic_reg_write(REG_POWER_CTL2, val);
+ pmic_reg_write(p, REG_POWER_CTL2, val);
udelay(2500);