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author | Axel Lin <axel.lin@ingics.com> | 2015-02-26 10:45:22 +0800 |
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committer | Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> | 2015-03-30 01:42:49 +0530 |
commit | 52091ad146d766cdc5ccd65430b2a4e5cb7aec32 (patch) | |
tree | fe337a4e09d6e9a10207d58c0f1f0dedb365013a /board | |
parent | 1478aeb32dcf57fdd01fd9efc3e3ab0083450cc3 (diff) | |
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spi: designware_spi: revisit FIFO size detection again
By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
either 0 or 1 byte;
b) FIFO size is incorrectly decreased by 1 which already done by meaning of
TX Level register.
Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'board')
0 files changed, 0 insertions, 0 deletions