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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-30 23:49:17 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-30 23:49:17 +0200
commit1c27059a2f7158a9c9a8778535b030935d75179d (patch)
treebf577d5c9f0da21c5d57feed1091214e54c39dec /board
parent8f0732ac3dc3bdbbcada313dc4b4b38d5d2c376a (diff)
parent4668a086bb0a769b741e3a4ffab85f1c41c7cdb8 (diff)
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Merge remote-tracking branch 'u-boot/master'
Diffstat (limited to 'board')
-rw-r--r--board/apollon/apollon.c470
-rw-r--r--board/apollon/config.mk25
-rw-r--r--board/apollon/lowlevel_init.S337
-rw-r--r--board/apollon/mem.c237
-rw-r--r--board/apollon/mem.h170
-rw-r--r--board/apollon/sys_info.c396
-rw-r--r--board/atmel/atngw100mkii/Makefile (renamed from board/apollon/Makefile)23
-rw-r--r--board/atmel/atngw100mkii/atngw100mkii.c156
-rw-r--r--board/davinci/da8xxevm/README.da85068
-rw-r--r--board/freescale/common/Makefile2
-rw-r--r--board/freescale/common/fman.c31
-rw-r--r--board/freescale/common/fman.h2
-rw-r--r--board/freescale/common/p_corenet/law.c13
-rw-r--r--board/freescale/common/p_corenet/tlb.c18
-rw-r--r--board/freescale/corenet_ds/eth_p4080.c59
-rw-r--r--board/freescale/corenet_ds/pbi.cfg51
-rw-r--r--board/freescale/corenet_ds/rcw_p3041ds.cfg11
-rw-r--r--board/freescale/corenet_ds/rcw_p4080ds.cfg11
-rw-r--r--board/freescale/corenet_ds/rcw_p5020ds.cfg11
-rw-r--r--board/freescale/m5208evbe/m5208evbe.c28
-rw-r--r--board/freescale/m52277evb/m52277evb.c30
-rw-r--r--board/freescale/m5235evb/m5235evb.c43
-rw-r--r--board/freescale/m5253demo/m5253demo.c29
-rw-r--r--board/freescale/m5253evbe/m5253evbe.c30
-rw-r--r--board/freescale/m5272c3/m5272c3.c9
-rw-r--r--board/freescale/m5275evb/m5275evb.c50
-rw-r--r--board/freescale/m53017evb/m53017evb.c28
-rw-r--r--board/freescale/m5329evb/m5329evb.c28
-rw-r--r--board/freescale/m5329evb/nand.c14
-rw-r--r--board/freescale/m5373evb/m5373evb.c28
-rw-r--r--board/freescale/m5373evb/nand.c18
-rw-r--r--board/freescale/m54451evb/m54451evb.c32
-rw-r--r--board/freescale/m54455evb/m54455evb.c90
-rw-r--r--board/freescale/m547xevb/m547xevb.c34
-rw-r--r--board/freescale/m548xevb/m548xevb.c34
-rw-r--r--board/freescale/mpc8308rdb/mpc8308rdb.c58
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c6
-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c6
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c6
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c6
-rw-r--r--board/freescale/p1010rdb/ddr.c7
-rw-r--r--board/freescale/p1_p2_rdb_pc/law.c2
-rw-r--r--board/freescale/p3060qds/README110
-rw-r--r--board/freescale/p3060qds/ddr.c248
-rw-r--r--board/freescale/p3060qds/eth.c482
-rw-r--r--board/freescale/p3060qds/fixed_ddr.c214
-rw-r--r--board/freescale/p3060qds/p3060qds.c342
-rw-r--r--board/freescale/p3060qds/p3060qds.h30
-rw-r--r--board/freescale/p3060qds/p3060qds_qixis.h74
-rw-r--r--board/mcc200/lcd.c20
-rw-r--r--board/overo/overo.c10
-rw-r--r--board/qi/qi_lb60/qi_lb60.c4
-rw-r--r--board/samsung/common/Makefile (renamed from board/freescale/p3060qds/Makefile)23
-rw-r--r--board/samsung/common/multi_i2c.c65
-rw-r--r--board/samsung/goni/lowlevel_init.S120
-rw-r--r--board/samsung/smdkc100/lowlevel_init.S42
-rw-r--r--board/samsung/trats/trats.c23
-rw-r--r--board/xilinx/microblaze-generic/microblaze-generic.c9
58 files changed, 862 insertions, 3661 deletions
diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c
deleted file mode 100644
index 76626f0..0000000
--- a/board/apollon/apollon.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics.
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from omap2420
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/mem.h>
-#include <asm/mach-types.h>
-
-void wait_for_command_complete(unsigned int wd_base);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define write_config_reg(reg, value) \
-do { \
- writeb(value, reg); \
-} while (0)
-
-#define mask_config_reg(reg, mask) \
-do { \
- char value = readb(reg) & ~(mask); \
- writeb(value, reg); \
-} while (0)
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay(unsigned long loops)
-{
- __asm__("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRM, finish GPMC */
-
- gd->bd->bi_arch_number = 919;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with sram stack.
- **********************************************************/
-void s_init(void)
-{
- watchdog_init();
- set_muxconf_regs();
- delay(100);
-
- peripheral_enable();
- icache_enable();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r(void)
-{
- return (0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * The ROM takes care of the secure one. Of the 3 GP ones,
- * 1 can reset us directly, the other 2 only generate MPU interrupts.
- */
- __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
-
-#define MPU_WD_CLOCKED 1
-#if MPU_WD_CLOCKED
- /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
- __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
- wait_for_command_complete(WD3_BASE);
- __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
-
- __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
- wait_for_command_complete(WD4_BASE);
- __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
-#endif
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WWPS);
- } while (pending);
-}
-
-/*******************************************************************
- * Routine:board_eth_init
- * Description: take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- ******************************************************************/
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- int cnt = 20;
-
- __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
-
- __raw_writew(0x0, LAN_RESET_REGISTER);
- do {
- __raw_writew(0x1, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto eth_reset_err_out;
- --cnt;
- } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
-
- cnt = 20;
-
- do {
- __raw_writew(0x0, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto eth_reset_err_out;
- --cnt;
- } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
- udelay(1000);
-
- mask_config_reg(ETH_CONTROL_REG, 0x01);
- udelay(1000);
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-eth_reset_err_out:
-#endif
- return rc;
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init(void)
-{
- unsigned int size;
- u32 mtype, btype;
-#define NOT_EARLY 0
-
- btype = get_board_type();
- mtype = get_mem_type();
-
- display_board_info(btype);
-
- if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
- /* init other chip select */
- do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
- }
-
- size = get_sdr_cs_size(SDRC_CS0_OSET);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size;
-#if CONFIG_NR_DRAM_BANKS > 1
- size = get_sdr_cs_size(SDRC_CS1_OSET);
-
- gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size;
- gd->bd->bi_dram[1].size = size;
-#endif
-
- return 0;
-}
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware
- *********************************************************/
-void set_muxconf_regs(void)
-{
- muxSetupSDRC();
- muxSetupGPMC();
- muxSetupUsb0(); /* USB Device */
- muxSetupUsbHost(); /* USB Host */
- muxSetupUART1();
- muxSetupLCD();
- muxSetupMMCSD();
- muxSetupTouchScreen();
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void peripheral_enable(void)
-{
- unsigned int v, if_clks = 0, func_clks = 0;
-
- /* Enable GP2 timer. */
- if_clks |= BIT4 | BIT3;
- func_clks |= BIT4 | BIT3;
- /* Sys_clk input OMAP2420_GPT2 */
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CONFIG_SYS_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- /* Interface clocks on */
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
- __raw_writel(v, CM_ICLKEN1_CORE);
- /* Functional Clocks on */
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
- __raw_writel(v, CM_FCLKEN1_CORE);
- delay(1000);
-
-#ifndef KERNEL_UPDATED
- {
-#define V1 0xffffffff
-#define V2 0x00000007
-
- __raw_writel(V1, CM_FCLKEN1_CORE);
- __raw_writel(V2, CM_FCLKEN2_CORE);
- __raw_writel(V1, CM_ICLKEN1_CORE);
- __raw_writel(V1, CM_ICLKEN2_CORE);
- }
-#endif
-}
-
-/****************************************
- * Routine: muxSetupUsb0 (ostboot)
- * Description: Setup usb muxing
- *****************************************/
-void muxSetupUsb0(void)
-{
- mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
-}
-
-/****************************************
- * Routine: muxSetupUSBHost (ostboot)
- * Description: Setup USB Host muxing
- *****************************************/
-void muxSetupUsbHost(void)
-{
- /* V19 */
- write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
- /* W20 */
- write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
- /* N14 */
- write_config_reg(CONTROL_PADCONF_GPIO69, 3);
- /* P15 */
- write_config_reg(CONTROL_PADCONF_GPIO70, 3);
- /* L18 */
- write_config_reg(CONTROL_PADCONF_GPIO102, 3);
- /* L19 */
- write_config_reg(CONTROL_PADCONF_GPIO103, 3);
- /* K15 */
- write_config_reg(CONTROL_PADCONF_GPIO104, 3);
- /* K14 */
- write_config_reg(CONTROL_PADCONF_GPIO105, 3);
-}
-
-/****************************************
- * Routine: muxSetupUART1 (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-void muxSetupUART1(void)
-{
- /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
- /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
- /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
- /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
-}
-
-/****************************************
- * Routine: muxSetupLCD (ostboot)
- * Description: Setup lcd muxing
- *****************************************/
-void muxSetupLCD(void)
-{
- /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
- /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
- /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
- /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
- /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
- /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
- /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
- /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
- /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
- /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
- /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
- /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
- /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
- /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
- /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
- /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
- /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
- /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
- /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
- /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
- /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
- /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
-}
-
-/****************************************
- * Routine: muxSetupMMCSD (ostboot)
- * Description: set up MMC muxing
- *****************************************/
-void muxSetupMMCSD(void)
-{
- /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
- /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
- /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
- /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
- /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
- /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
- /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
- /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
- /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
- /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
- /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
- /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
-}
-
-/******************************************
- * Routine: muxSetupTouchScreen (ostboot)
- * Description: Set up touch screen muxing
- *******************************************/
-void muxSetupTouchScreen(void)
-{
- /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
- /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
- /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
- /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
-#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
- /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_GPIO85, 3);
-}
-
-/***************************************************************
- * Routine: muxSetupGPMC (ostboot)
- * Description: Configures balls which cam up in protected mode
- ***************************************************************/
-void muxSetupGPMC(void)
-{
- /* gpmc_io_dir, MCR */
- volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
- *MCR = 0x19000000;
-
- /* NOR FLASH CS0 */
- /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
- write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
- /* MPDB(Multi Port Debug Port) CS1 */
- /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
- /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
- /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
- /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
- /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
- /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
- /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
-}
-
-/****************************************************************
- * Routine: muxSetupSDRC (ostboot)
- * Description: Configures balls which come up in protected mode
- ****************************************************************/
-void muxSetupSDRC(void)
-{
- /* It's set by IPL */
-}
diff --git a/board/apollon/config.mk b/board/apollon/config.mk
deleted file mode 100644
index 66005d4..0000000
--- a/board/apollon/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2005-2007
-# Samsung Electronics
-#
-# Samsung December board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# December has 1 bank of 128MB mDDR-SDRAM on CS0
-# December has 1 bank of 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x83e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-#CONFIG_SYS_TEXT_BASE = 0x40270000
-
-# Handy to get symbols to debug ROM version.
-#CONFIG_SYS_TEXT_BASE = 0x0
-#CONFIG_SYS_TEXT_BASE = 0x08000000
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S
deleted file mode 100644
index f066fe4..0000000
--- a/board/apollon/lowlevel_init.S
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include "mem.h"
-
-#define APOLLON_CS0_BASE 0x00000000
-
-#ifdef PRCM_CONFIG_I
-#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
-#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
-#define SDRC_RFR_CTRL_0_VAL 0x00044C01
-#elif defined(PRCM_CONFIG_II)
-#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
-#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
-#define SDRC_RFR_CTRL_0_VAL 0x00030001
-#endif
-
-#define SDRAM_BASE_ADDRESS 0x80008000
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#ifdef CONFIG_SYS_NOR_BOOT
- /* Check running in SDRAM */
- mov r0, pc, lsr #28
- cmp r0, #8
- beq prcm_setup
-
-flash_setup:
- /* In Flash */
- ldr r0, =WD2_BASE
- ldr r1, =WD_UNLOCK1
- str r1, [r0, #WSPR]
-
- ldr r1, =WD_UNLOCK2
- str r1, [r0, #WSPR]
-
- /* Pin muxing for SDRC */
- mov r1, #0x00
- ldr r0, =0x480000A1 /* ball C12, mode 0 */
- strb r1, [r0]
-
- ldr r0, =0x48000032 /* ball D11, mode 0 */
- strb r1, [r0]
-
- ldr r0, =0x480000A3 /* ball B13, mode 0 */
- strb r1, [r0]
-
- /* SDRC setting */
- ldr r0, =OMAP2420_SDRC_BASE
- ldr r1, =0x00000010
- str r1, [r0, #0x10]
-
- ldr r1, =0x00000100
- str r1, [r0, #0x44]
-
- /* SDRC CS0 configuration */
- ldr r1, =0x00d04011
- str r1, [r0, #0x80]
-
- ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
- str r1, [r0, #0x9C]
-
- ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
- str r1, [r0, #0xA0]
-
- ldr r1, =SDRC_RFR_CTRL_0_VAL
- str r1, [r0, #0xA4]
-
- ldr r1, =0x00000041
- str r1, [r0, #0x70]
-
- /* Manual command sequence */
- ldr r1, =0x00000007
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000000
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000001
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000002
- str r1, [r0, #0xA8]
- str r1, [r0, #0xA8]
-
- /*
- * CS0 SDRC Mode register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- ldr r1, =0x00000032
- str r1, [r0, #0x84]
-
- /* Note: You MUST set EMR values */
- /* EMR1 & EMR2 */
- ldr r1, =0x00000000
- str r1, [r0, #0x88]
- str r1, [r0, #0x8C]
-
-#ifdef OLD_SDRC_DLLA_CTRL
- /* SDRC_DLLA_CTRL */
- ldr r1, =0x00007306
- str r1, [r0, #0x60]
-
- ldr r1, =0x00007303
- str r1, [r0, #0x60]
-#else
- /* SDRC_DLLA_CTRL */
- ldr r1, =0x00000506
- str r1, [r0, #0x60]
-
- ldr r1, =0x00000503
- str r1, [r0, #0x60]
-#endif
-
-#ifdef __BROKEN_FEATURE__
- /* SDRC_DLLB_CTRL */
- ldr r1, =0x00000506
- str r1, [r0, #0x68]
-
- ldr r1, =0x00000503
- str r1, [r0, #0x68]
-#endif
-
- /* little delay after init */
- mov r2, #0x1800
-1:
- subs r2, r2, #0x1
- bne 1b
-
- /* Setup base address */
- ldr r0, =0x00000000 /* NOR address */
- ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
- ldr r2, =0x20000 /* Size: 128KB */
-
-copy_loop:
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- cmp r0, r2
- ble copy_loop
-
- ldr r1, =SDRAM_BASE_ADDRESS
- mov lr, pc
- mov pc, r1
-#endif
-
-prcm_setup:
- ldr r0, =OMAP2420_CM_BASE
- ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
- bic r1, r1, #0x03
- orr r1, r1, #0x02
- str r1, [r0, #0x544]
-
- ldr r1, [r0, #0x500]
- bic r1, r1, #0x03
- orr r1, r1, #0x01
- str r1, [r0, #0x500]
-
- ldr r1, [r0, #0x140]
- bic r1, r1, #0x1f
- orr r1, r1, #0x02
- str r1, [r0, #0x140]
-
-#ifdef PRCM_CONFIG_I
- ldr r1, =0x000003C3
-#else
- ldr r1, =0x00000343
-#endif
- str r1, [r0, #0x840]
-
- ldr r1, =0x00000002
- str r1, [r0, #0x340]
-
- ldr r1, =CM_CLKSEL1_CORE
-#ifdef PRCM_CONFIG_I
- ldr r2, =0x08300C44
-#else
- ldr r2, =0x04600C26
-#endif
- str r2, [r1]
-
- ldr r0, =OMAP2420_CM_BASE
- ldr r1, [r0, #0x084]
- and r1, r1, #0x01
- cmp r1, #0x01
- bne clkvalid
-
- b .
-
-clkvalid:
- mov r1, #0x01
- str r1, [r0, #0x080]
-
-waitvalid:
- ldr r1, [r0, #0x084]
- and r1, r1, #0x01
- cmp r1, #0x00
- bne waitvalid
-
- ldr r0, =CM_CLKSEL1_PLL
-#ifdef PRCM_CONFIG_I
- ldr r1, =0x01837100
-#else
- ldr r1, =0x01832100
-#endif
- str r1, [r0]
-
- ldr r0, =PRCM_CLKCFG_CTRL
- mov r1, #0x01
- str r1, [r0]
- mov r6, #0x50
-loop1:
- subs r6, r6, #0x01
- cmp r6, #0x01
- bne loop1
-
- ldr r0, =CM_CLKEN_PLL
- mov r1, #0x0f
- str r1, [r0]
-
- mov r6, #0x100
-loop2:
- subs r6, r6, #0x01
- cmp r6, #0x01
- bne loop2
-
- ldr r0, =0x48008200
- ldr r1, =0xbfffffff
- str r1, [r0]
-
- ldr r0, =0x48008210
- ldr r1, =0xfffffff9
- str r1, [r0]
-
- ldr r0, =0x4806a004
- ldr r1, =0x00
- strb r1, [r0]
-
- ldr r0, =0x4806a020
- ldr r1, =0x07
- strb r1, [r0]
-
- ldr r0, =0x4806a00c
- ldr r1, =0x83
- strb r1, [r0]
-
- ldr r0, =0x4806a000
- ldr r1, =0x1a
- strb r1, [r0]
-
- ldr r0, =0x4806a004
- ldr r1, =0x00
- strb r1, [r0]
-
- ldr r0, =0x4806a00c
- ldr r1, =0x03
- strb r1, [r0]
-
- ldr r0, =0x4806a010
- ldr r1, =0x03
- strb r1, [r0]
-
- ldr r0, =0x4806a008
- ldr r1, =0x04
- strb r1, [r0]
-
- ldr r0, =0x4806a020
- ldr r1, =0x00
- strb r1, [r0]
-
-#if 0
- ldr r0, =0x4806a000
- mov r1, #'u'
- strb r1, [r0]
-#endif
-
-#if 0
- /* LED0 OFF */
- ldr r3, =0x480000E5
- mov r4, #0x0b
- strb r4, [r3]
-#endif
-
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
diff --git a/board/apollon/mem.c b/board/apollon/mem.c
deleted file mode 100644
index 36bf6e9..0000000
--- a/board/apollon/mem.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from omap2420
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-
-#include "mem.h"
-
-/************************************************************
- * sdelay() - simple spin loop. Will be constant time as
- * its generally used in 12MHz bypass conditions only. This
- * is necessary until timers are accessible.
- *
- * not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
- __asm__("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/********************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * (config II default).
- * -- called from SRAM, or Flash (using temp SRAM stack).
- ********************************************************************/
-void prcm_init(void) { }
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- * command line mem=xyz use all memory with out discontigious support
- * compiled in. Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
- u32 size, a_add_low, a_add_high;
-
- size = get_sdr_cs_size(SDRC_CS0_OSET);
- size /= SZ_32M; /* find size to offset CS1 */
- a_add_high = (size & 3) << 8; /* set up low field */
- a_add_low = (size & 0x3C) >> 2; /* set up high field */
- __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
-
-}
-
-/********************************************************
- * mem_ok() - test used to see if timings are correct
- * for a part. Helps in gussing which part
- * we are currently using.
- *******************************************************/
-u32 mem_ok(void)
-{
- u32 val1, val2;
- u32 pattern = 0x12345678;
-
- /* clear pos A */
- __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
- /* pattern to pos B */
- __raw_writel(pattern, OMAP2420_SDRC_CS0);
- /* remove pattern off the bus */
- __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
- /* get pos A value */
- val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
- val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
-
- /* see if pos A value changed */
- if ((val1 != 0) || (val2 != pattern))
- return (0);
- else
- return (1);
-}
-
-/********************************************************
- * sdrc_init() - init the sdrc chip selects CS0 and CS1
- * - early init routines, called from flash or
- * SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-#define EARLY_INIT 1
- /* only init up first bank here */
- do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- * -called from low level code with stack only.
- * -code sets up SDRAM timing and muxing for 2422 or 2420.
- * -optimal settings can be placed here, or redone after i2c
- * inspection of board info
- *
- * This is a bit ugly, but should handle all memory moduels
- * used with the APOLLON. The first time though this code from s_init()
- * we configure the first chip select. Later on we come back and
- * will configure the 2nd chip select if it exists.
- *
- **************************************************************************/
-void do_sdrc_init(u32 offset, u32 early)
-{
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
- u32 mux = 0, mtype, mwidth, rev, tval;
-
- rev = get_cpu_rev();
- if (rev == CPU_2420_2422_ES1)
- tval = 1;
- else
- tval = 0; /* disable bit switched meaning */
-
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
-#ifdef CONFIG_SYS_NAND_BOOT
- /* set nWP, disable limited addr */
- __raw_writel(0x001, GPMC_CONFIG);
-#else
- /* set nWP, disable limited addr */
- __raw_writel(0x111, GPMC_CONFIG);
-#endif
-
- /* discover bus connection from sysboot */
- if (is_gpmc_muxed() == GPMC_MUXED)
- mux = BIT9;
- mtype = get_gpmc0_type();
- mwidth = get_gpmc0_width();
-
- /* setup cs0 */
- __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
- sdelay(1000);
-
-#ifdef CONFIG_SYS_NOR_BOOT
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
-#else
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
- GPMC_CONFIG1_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
-#endif
- sdelay(2000);
-
- /* setup cs1 */
- __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
- sdelay(1000);
-
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
- sdelay(2000);
-
- /* setup cs2 */
- __raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */
- sdelay(1000);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
- GPMC_CONFIG1_2);
- /* It's same as cs 0 */
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
-#ifdef CONFIG_SYS_NOR_BOOT
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
-#else
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
-#endif
-
-#ifndef CONFIG_SYS_NOR_BOOT
- /* setup cs3 */
- __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
- sdelay(1000);
-
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
-#endif
-
-#ifndef ASYNC_NOR
- __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
- __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
- __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
-#endif
- sdelay(2000);
-}
diff --git a/board/apollon/mem.h b/board/apollon/mem.h
deleted file mode 100644
index 09c4ea4..0000000
--- a/board/apollon/mem.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _APOLLON_OMAP24XX_MEM_H_
-#define _APOLLON_OMAP24XX_MEM_H_
-
-/* Slower full frequency range default timings for x32 operation*/
-#define APOLLON_2420_SDRC_SHARING 0x00000100
-#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
-#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
-
-/* optimized timings good for current shipping parts */
-#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
-#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
-
-#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
-#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
-
-#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
-#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
-
-#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
-#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
-
-#ifdef PRCM_CONFIG_I
-#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
-#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
-#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
-#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
-#elif PRCM_CONFIG_II
-#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
-#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
-#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
-#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
-#endif
-
-/* GPMC settings */
-#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
-/* CS0: OneNAND */
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
-
-/* CS1: Ethernet */
-# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203
-# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
-# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
-# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
-# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
-# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
-# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
-
-/* CS2: OneNAND */
-/* It's same as CS0 */
-# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
-
-/* CS3: NOR */
-#ifdef ASYNC_NOR
-# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
-#else
-# define SYNC_NOR_VALUE 0x24aaa
-# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
-#endif /* ASYNC_NOR */
-# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
-#endif /* endif PRCM_CONFIG_I */
-
-#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
-/* CS0: OneNAND */
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
-
-/* CS1: ethernet */
-# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
-# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
-# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
-# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
-# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
-# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
-
-/* CS2: OneNAND */
-/* It's same as CS0 */
-# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
-
-/* CS3: NOR */
-#define ASYNC_NOR
-#ifdef ASYNC_NOR
-# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
-#else
-# define SYNC_NOR_VALUE 0x24aaa
-# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
-#endif /* ASYNC_NOR */
-# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
-#endif /* endif PRCM_CONFIG_II */
-
-#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
-# else /* NOR boot */
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
-# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
-# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
-# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
-# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
-# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
-# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
-#endif /* endif CONFIG_SYS_PRCM_III */
-
-#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c
deleted file mode 100644
index 4f950ae..0000000
--- a/board/apollon/sys_info.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from omap2420
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h> /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <i2c.h>
-
-/**************************************************************************
- * get_prod_id() - get id info from chips
- ***************************************************************************/
-static u32 get_prod_id(void)
-{
- u32 p;
- p = __raw_readl(PRODUCTION_ID); /* get production ID */
- return ((p & CPU_242X_PID_MASK) >> 16);
-}
-
-/**************************************************************************
- * get_cpu_type() - low level get cpu type
- * - no C globals yet.
- * - just looking to say if this is a 2422 or 2420 or ...
- * - to start with we will look at switch settings..
- * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
- * (mux for 2420, non-mux for 2422).
- ***************************************************************************/
-u32 get_cpu_type(void)
-{
- u32 v;
-
- switch (get_prod_id()) {
- case 1:; /* 2420 */
- case 2:
- return (CPU_2420);
- break; /* 2420 pop */
- case 4:
- return (CPU_2422);
- break;
- case 8:
- return (CPU_2423);
- break;
- default:
- break; /* early 2420/2422's unmarked */
- }
-
- v = __raw_readl(TAP_IDCODE_REG);
- v &= CPU_24XX_ID_MASK;
- /* currently 2420 and 2422 have same id */
- if (v == CPU_2420_CHIPID) {
- if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
- return (CPU_2420);
- else
- return (CPU_2422);
- } else
- return (CPU_2420); /* don't know, say 2420 */
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return (v + 1); /* currently 2422 and 2420 match up */
-}
-
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
- volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
- if (*burst == H4_2420_SDRC_MR_0_SDR)
- return (1);
- return (0);
-}
-
-/***********************************************************
- * get_mem_type() - identify type of mDDR part used.
- * 2422 uses stacked DDR, 2 parts CS0/CS1.
- * 2420 may have 1 or 2, no good way to know...only init 1...
- * when eeprom data is up we can select 1 more.
- *************************************************************/
-u32 get_mem_type(void)
-{
- u32 cpu, sdr = is_mem_sdr();
-
- cpu = get_cpu_type();
- if (cpu == CPU_2422 || cpu == CPU_2423)
- return (DDR_STACKED);
-
- if (get_prod_id() == 0x2)
- return (XDR_POP);
-
- if (get_board_type() == BOARD_H4_MENELAUS)
- if (sdr)
- return (SDR_DISCRETE);
- else
- return (DDR_COMBO);
- else if (sdr) /* SDP + SDR kit */
- return (SDR_DISCRETE);
- else
- return (DDR_DISCRETE); /* origional SDP */
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 offset)
-{
- u32 size;
- size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */
- size &= 0x2FF; /* remove unwanted bits */
- size *= SZ_2M; /* find size in MB */
- return (size);
-}
-
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
- * when they are available we can get info from there. This should
- * be correct of all known boards up until today.
- ************************************************************************/
-u32 get_board_type(void)
-{
- return (BOARD_H4_SDP);
-}
-
-/******************************************************************
- * get_sysboot_value() - get init word settings (dip switch on h4)
- ******************************************************************/
-inline u32 get_sysboot_value(void)
-{
- return (0x00000FFF & __raw_readl(CONTROL_STATUS));
-}
-
-/***************************************************************************
- * get_gpmc0_base() - Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- * - for u-boot we currently map:
- * -- 0 to nothing,
- * -- 4 to flash
- * -- 8 to enent
- * -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
- u32 b;
-
- b = __raw_readl(GPMC_CONFIG7_0);
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return (b);
-}
-
-/*****************************************************************
- * is_gpmc_muxed() - tells if address/data lines are multiplexed
- *****************************************************************/
-u32 is_gpmc_muxed(void)
-{
- u32 mux;
- mux = get_sysboot_value();
- if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
- return (GPMC_MUXED); /* NAND Boot mode */
- if (mux & BIT1) /* if mux'ed */
- return (GPMC_MUXED);
- else
- return (GPMC_NONMUXED);
-}
-
-/************************************************************************
- * get_gpmc0_type() - read sysboot lines to see type of memory attached
- ************************************************************************/
-u32 get_gpmc0_type(void)
-{
- u32 type;
- type = get_sysboot_value();
- if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
- return (TYPE_NAND);
- else
- return (TYPE_NOR);
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
- u32 width;
- width = get_sysboot_value();
- if ((width & 0xF) == (BIT3 | BIT2))
- return (WIDTH_8BIT);
- else
- return (WIDTH_16BIT);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return (1);
- if (i == bound)
- return (0);
- } while (1);
-}
-
-/*********************************************************************
- * display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
- char cpu_2420[] = "2420"; /* cpu type */
- char cpu_2422[] = "2422";
- char cpu_2423[] = "2423";
- char mem_sdr[] = "mSDR"; /* memory type */
- char mem_ddr[] = "mDDR";
- char t_tst[] = "TST"; /* security level */
- char t_emu[] = "EMU";
- char t_hs[] = "HS";
- char t_gp[] = "GP";
- char unk[] = "?";
-
- char *cpu_s, *mem_s, *sec_s;
- u32 cpu, rev, sec;
-
- rev = get_cpu_rev();
- cpu = get_cpu_type();
- sec = get_device_type();
-
- if (is_mem_sdr())
- mem_s = mem_sdr;
- else
- mem_s = mem_ddr;
-
- if (cpu == CPU_2423)
- cpu_s = cpu_2423;
- else if (cpu == CPU_2422)
- cpu_s = cpu_2422;
- else
- cpu_s = cpu_2420;
-
- switch (sec) {
- case TST_DEVICE:
- sec_s = t_tst;
- break;
- case EMU_DEVICE:
- sec_s = t_emu;
- break;
- case HS_DEVICE:
- sec_s = t_hs;
- break;
- case GP_DEVICE:
- sec_s = t_gp;
- break;
- default:
- sec_s = unk;
- }
-
- printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
- printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = 242x IP platform (first 2xx boards)
- * 1 = 242x Menelaus platfrom.
- *************************************************************************/
-u32 get_board_rev(void)
-{
- u32 rev = 0;
- u32 btype = get_board_type();
-
- if (btype == BOARD_H4_MENELAUS)
- rev = 1;
- return (rev);
-}
-
-/********************************************************
- * get_base(); get upper addr of current execution
- *******************************************************/
-u32 get_base(void)
-{
- u32 val;
- __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
- val &= 0xF0000000;
- val >>= 28;
- return (val);
-}
-
-/********************************************************
- * get_base2(); get 2upper addr of current execution
- *******************************************************/
-u32 get_base2(void)
-{
- u32 val;
- __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
- val &= 0xFF000000;
- val >>= 24;
- return (val);
-}
-
-/********************************************************
- * running_in_flash() - tell if currently running in
- * flash.
- *******************************************************/
-u32 running_in_flash(void)
-{
- if (get_base() < 4)
- return (1); /* in flash */
- return (0); /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- * running_in_sram() - tell if currently running in
- * sram.
- *******************************************************/
-u32 running_in_sram(void)
-{
- if (get_base() == 4)
- return (1); /* in SRAM */
- return (0); /* running in FLASH or SDRAM */
-}
-
-/********************************************************
- * running_in_sdram() - tell if currently running in
- * flash.
- *******************************************************/
-u32 running_in_sdram(void)
-{
- if (get_base() > 4)
- return (1); /* in sdram */
- return (0); /* running in SRAM or FLASH */
-}
-
-/*************************************************************
- * running_from_internal_boot() - am I a signed NOR image.
- *************************************************************/
-u32 running_from_internal_boot(void)
-{
- u32 v, base;
-
- v = get_sysboot_value() & BIT3;
- base = get_base2();
- /* if running at mask rom flash address and
- * sysboot3 says this was an internal boot
- */
- if ((base == 0x08) && v)
- return (1);
- else
- return (0);
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
- return (mode >>= 8);
-}
diff --git a/board/apollon/Makefile b/board/atmel/atngw100mkii/Makefile
index 1bf1a32..7fbd20d 100644
--- a/board/apollon/Makefile
+++ b/board/atmel/atngw100mkii/Makefile
@@ -1,9 +1,7 @@
#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2005-2006 Atmel Corporation
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# See file CREDITS for list of people who contributed to this project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -19,25 +17,24 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB := $(obj)lib$(BOARD).o
-COBJS-y := apollon.o mem.o sys_info.o
-SOBJS := lowlevel_init.o
+COBJS := $(BOARD).o
-COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c
new file mode 100644
index 0000000..f4023b3
--- /dev/null
+++ b/board/atmel/atngw100mkii/atngw100mkii.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2010 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <spi.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
+ .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 10,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 6,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
+ | HMATRIX_BIT(EBI_NAND_ENABLE));
+
+ portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
+ PORTMUX_DRIVE_HIGH);
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
+ | PORTMUX_DRIVE_MIN);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+ portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850
new file mode 100644
index 0000000..313a1ef
--- /dev/null
+++ b/board/davinci/da8xxevm/README.da850
@@ -0,0 +1,68 @@
+Summary
+=======
+The README is for the boot procedure used for various DA850 (or compatible
+parts such as the AM1808) based boards.
+
+In the context of U-Boot, the board is booted in three stages. The initial
+bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
+in the internal ROM. The RBL initializes the internal memory and then
+depending on the exact board and pin configurations will initialize another
+controller (such as SPI or NAND) to continue the boot process by loading
+the secondary program loader (SPL). The SPL will initialize the system
+further (some clocks, SDRAM) and then load the full u-boot from a
+predefined location in persistent storage to DDR and jumps to the u-boot
+entry point.
+
+AIS is an image format defined by TI for the images that are to be loaded
+to memory by the RBL. The image is divided into a series of sections and
+the image's entry point is specified. Each section comes with meta data
+like the target address the section is to be copied to and the size of the
+section, which is used by the RBL to load the image. At the end of the
+image the RBL jumps to the image entry point. The AIS format allows for
+other things such as programming the clocks and SDRAM if the header is
+programmed for it. We do not take advantage of this and instead use SPL as
+it allows for additional flexibility (run-time detect of board revision,
+loading the next image from a different media, etc).
+
+
+Compilation
+===========
+The exact build target you need will depend on the board you have. For
+Logic PD boards, or other boards which store the ethernet MAC address at
+the end of SPI flash, run 'make da850evm'. For boards which store the
+ethernet MAC address in the i2c EEPROM located at 0x50, run
+'make da850_am18xxevm'. Once this build completes you will have a
+u-boot.ais file that needs to be written to the correct persistent
+storage.
+
+
+Flashing the images to SPI
+==========================
+The AIS image can be written to SPI flash using the following commands.
+Assuming that the network is configured and enabled and the u-boot.ais file
+is tftp'able.
+
+U-Boot > sf probe 0
+U-Boot > sf erase 0 +320000
+U-Boot > tftp u-boot.ais
+U-Boot > sf write c0700000 0 $filesize
+
+
+Recovery
+========
+
+In the case of a "bricked" board, you need to use the TI tools found
+here[1] to write the u-boot.ais file. An example of recovering to the SPI
+flash of an AM1808 would be:
+
+$ mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \
+ -flash_noubl /path/to/u-boot.ais
+
+For other target types and flash locations:
+
+$ mono sfh_OMAP-L138.exe -h
+
+Links
+=====
+[1]
+ http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 0b40dc7..54cb098 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -51,14 +51,12 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
-COBJS-$(CONFIG_P3060QDS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
-SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 6ddf816..3ef4936 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -25,6 +25,9 @@
#include <libfdt_env.h>
#include <fdt_support.h>
+#include <fm_eth.h>
+#include <asm/fsl_serdes.h>
+
/*
* Given the following ...
*
@@ -67,3 +70,31 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
}
+
+/*
+ * Return the SerDes device enum for a given Fman port
+ *
+ * This function just maps the fm_port namespace to the srds_prtcl namespace.
+ */
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
+{
+ static const enum srds_prtcl srds_table[] = {
+ [FM1_DTSEC1] = SGMII_FM1_DTSEC1,
+ [FM1_DTSEC2] = SGMII_FM1_DTSEC2,
+ [FM1_DTSEC3] = SGMII_FM1_DTSEC3,
+ [FM1_DTSEC4] = SGMII_FM1_DTSEC4,
+ [FM1_DTSEC5] = SGMII_FM1_DTSEC5,
+ [FM1_10GEC1] = XAUI_FM1,
+ [FM2_DTSEC1] = SGMII_FM2_DTSEC1,
+ [FM2_DTSEC2] = SGMII_FM2_DTSEC2,
+ [FM2_DTSEC3] = SGMII_FM2_DTSEC3,
+ [FM2_DTSEC4] = SGMII_FM2_DTSEC4,
+ [FM2_DTSEC5] = SGMII_FM2_DTSEC5,
+ [FM2_10GEC1] = XAUI_FM2,
+ };
+
+ if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
+ return NONE;
+ else
+ return srds_table[port];
+}
diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h
index d39ef08..734b1da 100644
--- a/board/freescale/common/fman.h
+++ b/board/freescale/common/fman.h
@@ -23,4 +23,6 @@
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
+
#endif
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index c4566dd..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,19 +48,6 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index da21627..e5cf208 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
- * SRIOBOOT-SLAVE. When slave boot, the address of the
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
- * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
- * and ENV from master
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index b87b092..2c69c51 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -68,6 +68,15 @@ static char *mdio_names[16] = {
NULL, NULL, NULL,
};
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+ 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
static char *p4080ds_mdio_name_for_muxval(u32 muxval)
{
return mdio_names[(muxval & EMI_MASK) >> 28];
@@ -290,15 +299,6 @@ void fdt_fixup_board_enet(void *fdt)
}
}
-enum board_slots {
- SLOT1 = 1,
- SLOT2,
- SLOT3,
- SLOT4,
- SLOT5,
- SLOT6,
-};
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
@@ -307,27 +307,6 @@ int board_eth_init(bd_t *bis)
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
- u8 lane_to_slot[] = {
- SLOT1, /* 0 - Bank 1:A */
- SLOT1, /* 1 - Bank 1:B */
- SLOT2, /* 2 - Bank 1:C */
- SLOT2, /* 3 - Bank 1:D */
- SLOT3, /* 4 - Bank 1:E */
- SLOT3, /* 5 - Bank 1:F */
- SLOT3, /* 6 - Bank 1:G */
- SLOT3, /* 7 - Bank 1:H */
- SLOT6, /* 8 - Bank 1:I */
- SLOT6, /* 9 - Bank 1:J */
- SLOT4, /* 10 - Bank 2:A */
- SLOT4, /* 11 - Bank 2:B */
- SLOT4, /* 12 - Bank 2:C */
- SLOT4, /* 13 - Bank 2:D */
- SLOT5, /* 14 - Bank 3:A */
- SLOT5, /* 15 - Bank 3:B */
- SLOT5, /* 16 - Bank 3:C */
- SLOT5, /* 17 - Bank 3:D */
- };
-
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
@@ -380,17 +359,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT3:
+ case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -417,12 +396,12 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -444,17 +423,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT3:
+ case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -481,12 +460,12 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg
new file mode 100644
index 0000000..50806ca
--- /dev/null
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -0,0 +1,51 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg
new file mode 100644
index 0000000..8813156
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p3041ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P3041DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg
new file mode 100644
index 0000000..6a26339
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p4080ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P4080DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+105a0000 00000000 1e1e181e 0000cccc
+58400000 3c3c2000 58000000 e1000000
+00000000 00000000 00000000 008b6000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
new file mode 100644
index 0000000..b09e409
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5020ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5020DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0C540000 00000000 1E120000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 5f99e2f..355cfed 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index 9109edb..a9bec58 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -59,36 +60,37 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
__asm__("nop");
udelay(1000);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index b9e6126..e9a568e 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,8 +40,8 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 dramsize, i, dramclk;
/*
@@ -48,14 +49,15 @@ phys_size_t initdram(int board_type)
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
- gpio->par_ad =
- GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
- GPIO_PAR_AD_DATAL;
+ out_8(&gpio->par_ad,
+ GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+ GPIO_PAR_AD_DATAL);
/* Initialize PAR to enable SDRAM signals */
- gpio->par_sdram =
- GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
- GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
+ out_8(&gpio->par_sdram,
+ GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+ GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+ GPIO_PAR_SDRAM_SDCS(3));
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
@@ -64,25 +66,28 @@ phys_size_t initdram(int board_type)
}
i--;
- if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
+ if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
- sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
- SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
+ out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+ SDRAMC_DCR_RTIM_6CLKS |
+ SDRAMC_DCR_RC((15 * dramclk) >> 4));
/* Initialize DACR0 */
- sdram->dacr0 =
- SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
- SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+ out_be32(&sdram->dacr0,
+ SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+ SDRAMC_DARCn_PS_32);
asm("nop");
/* Initialize DMR0 */
- sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+ out_be32(&sdram->dmr0,
+ ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
asm("nop");
/* Set IP (bit 3) in DACR */
- sdram->dacr0 |= SDRAMC_DARCn_IP;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
@@ -93,7 +98,7 @@ phys_size_t initdram(int board_type)
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
- sdram->dacr0 |= SDRAMC_DARCn_RE;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 0x2000; i++) {
@@ -101,7 +106,7 @@ phys_size_t initdram(int board_type)
}
/* Finish the configuration by issuing the MRS. */
- sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
asm("nop");
/* Write to the SDRAM Mode Register */
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 8ffb2cc..052993d 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -109,7 +109,7 @@ int ide_preinit(void)
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
@@ -120,7 +120,8 @@ void ide_set_reset(int idereset)
};
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -129,17 +130,19 @@ void ide_set_reset(int idereset)
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(2000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif /* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index ae69f67..658748b 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int checkboard(void)
{
@@ -101,7 +102,7 @@ int ide_preinit(void)
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
@@ -112,7 +113,8 @@ void ide_set_reset(int idereset)
};
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -121,17 +123,19 @@ void ide_set_reset(int idereset)
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(2000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif /* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 902ca3a..c3160ce 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -2,6 +2,8 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -23,6 +25,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int checkboard (void) {
@@ -32,10 +35,10 @@ int checkboard (void) {
};
phys_size_t initdram (int board_type) {
- volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
- sdp->sdram_sdtr = 0xf539;
- sdp->sdram_sdcr = 0x4211;
+ out_be16(&sdp->sdram_sdtr, 0xf539);
+ out_be16(&sdp->sdram_sdcr, 0x4211);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 35c9b20..1bbe5a3 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -4,6 +4,8 @@
*
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,6 +27,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
#define PERIOD 13 /* system bus period in ns */
#define SDRAM_TREFI 7800 /* in ns */
@@ -38,67 +41,68 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
- gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+ /* Enable SDRAM */
+ out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
- sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
- sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+ out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
- sdp->sdcfg1 = 0x83711630;
- sdp->sdcfg2 = 0x46770000;
+ out_be32(&sdp->sdcfg1, 0x83711630);
+ out_be32(&sdp->sdcfg2, 0x46770000);
/* Enable clock */
- sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+ out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
/* Set precharge */
- sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
- sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
- | MCF_SDRAMC_SDMR_AD(0x0)
- | MCF_SDRAMC_SDMR_CMD;
+ setbits_be32(&sdp->sdmr,
+ MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+ MCF_SDRAMC_SDMR_CMD);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
- sdp->sdmr = 0x058d0000;
+ out_be32(&sdp->sdmr, 0x058d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
- sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
- sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
- /* Write mode register, clear reset DLL */
- sdp->sdmr = 0x018d0000;
+
+ out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
/* Turn on auto refresh, lock SDMR */
- sdp->sdcr =
+ out_be32(&sdp->sdcr,
MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_MUX(1)
/* 1 added to round up */
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
- | MCF_SDRAMC_SDCR_DQS_OE(0x3);
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3));
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index f331786..142485f 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index b4df22f..1c14b83 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 16025f9..c70c98c 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index 376de4b..8eb3512 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index df8c03b..ed79e39 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
+ clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 088c8c4..32a9374 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <common.h>
#include <spi.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,14 +52,14 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
- if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
- (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+ if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+ (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +68,33 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(200);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
udelay(100);
#endif
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 2a84514..0ca268e 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
@@ -59,33 +60,34 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
udelay(500);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
@@ -105,26 +107,29 @@ int testdram(void)
int ide_preinit(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
- gpio->par_feci2c |=
- (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
- GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
- gpio->par_ata |=
- (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
- GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
- | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
- GPIO_PAR_ATA_IORDY_IORDY);
- gpio->par_pci |=
- (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u32 tmp;
+
+ tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+ setbits_8(&gpio->par_fec, tmp);
+ tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+ (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+ setbits_be16(&gpio->par_feci2c, tmp);
+
+ setbits_be16(&gpio->par_ata,
+ GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+ GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+ GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+ GPIO_PAR_ATA_IORDY_IORDY);
+ setbits_be16(&gpio->par_pci,
+ GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
return (0);
}
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) MMAP_ATA;
+ atac_t *ata = (atac_t *) MMAP_ATA;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = {
@@ -136,24 +141,27 @@ void ide_set_reset(int idereset)
}; /* PIO 4 */
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(10000);
} else {
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / gd->bus_clk; /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(200000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 9f1ec38..fd9bddd 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,14 +41,14 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile siu_t *siu = (siu_t *) (MMAP_SIU);
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
break;
}
i--;
- siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index fbc0888..fb216d8 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,14 +41,14 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile siu_t *siu = (siu_t *) (MMAP_SIU);
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
break;
}
i--;
- siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index 5c54357..7e3fa1a 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -24,18 +24,56 @@
#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
+#include <spi.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <netdev.h>
+#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK 0x00400000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* active low */
+ clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* inactive high */
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
static u8 read_board_info(void)
{
u8 val8;
@@ -109,6 +147,25 @@ void pci_init_board(void)
*/
int misc_init_r(void)
{
+#ifdef CONFIG_MPC8XXX_SPI
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /*
+ * Set proper bits in SICRH to allow SPI on header J8
+ *
+ * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+ * switch. The pinmux configuration does not have a fine enough
+ * granularity to support both simultaneously.
+ */
+ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+ puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+ /* Set header J8 SPI chip select output, disabled */
+ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
@@ -124,6 +181,7 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
}
#endif
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index c75585e..a275d3a 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -87,10 +87,10 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
@@ -105,7 +105,7 @@ local_bus_init(void)
lbc->lcrr = 0x10000004;
}
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 532d32a..13ca84b 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -269,13 +269,13 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
- lbc->lcrr |= 0x80000000; /* DLL Bypass */
+ lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
- lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
} else {
- lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 3361614..4cfd61c 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -267,13 +267,13 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
- lbc->lcrr |= 0x80000000; /* DLL Bypass */
+ lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
- lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
} else {
- lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 1a165bf..285edbc 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -292,10 +292,10 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
@@ -310,7 +310,7 @@ local_bus_init(void)
lbc->lcrr = 0x10000004;
}
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 10c5a42..6d00caf 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void)
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16bit DDR width */
if (cpu->soc_ver == SVR_P1014) {
+ ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
- ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
- ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
- ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000;
+ /* divide SA and EA by two and then mask the rest so we don't
+ * write to reserved fields */
+ ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 7968919..0da8300 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -25,13 +25,11 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
-#ifndef CONFIG_NAND_SPL
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
-#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/p3060qds/README b/board/freescale/p3060qds/README
deleted file mode 100644
index ec62798..0000000
--- a/board/freescale/p3060qds/README
+++ /dev/null
@@ -1,110 +0,0 @@
-Overview
-=========
-The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
-
-The P3060 Processor combines six e500mc Power Architecture processor
-cores(1.2GHz) with high-performance datapath acceleration
-architecture(DPAA), CoreNet fabric infrastructure, as well as network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and military/aerospace applications.
-
-
-P3060QDS Board Specifications:
-==============================
-Memory subsystem:
- * 2G Bytes UDIMM DDR3(64bit bus) with ECC on
- * 128M Bytes NOR flash single-chip memory
- * 16M Bytes SPI flash
- * 8K Bytes AT24C64 I2C EEPROM for RCW
-
-Ethernet(Default SERDES 0x19):
- * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
- * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
- * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
- * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
- * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
- * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
- * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
- * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
-
-PCIe:
- * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
- * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
-
-RapidIO:
- * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
- * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
-
-USB:
- * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
- * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
-
-I2C:
- * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
- AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
- * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
- ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
- * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
- * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
- * I2C1_CH4: PCIe SLOT1
- * I2C1_CH5: PCIe SLOT2
- * I2C1_CH6: PCIe SLOT3
- * I2C1_CH7: PCIe SLOT4
- * I2C2: NULL
- * I2C3: NULL
-
-UART:
- * Supports two UARTs up to 115200 bps for console
-
-
-Boot from NOR flash
-===================
-1. Build image
- export ARCH=powerpc
- export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
- make P3060QDS_config
- make
-
-2. Program image
- => tftp 1000000 u-boot.bin
- => protect off all
- => erase eff80000 efffffff
- => cp.b 1000000 eff80000 80000
-
-3. Program RCW
- => tftp 1000000 rcw.bin
- => protect off all
- => erase e8000000 e801ffff
- => cp.b 1000000 e8000000 50
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => protect off all
- => erase ef000000 ef0fffff
- => cp.b 1000000 ef000000 2000
-
-5. Change DIP-switch
- RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
- Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Using the Device Tree Source File
-=================================
-To create the DTB (Device Tree Binary) image file, use a command
-similar to this:
- dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
-
-Or use the following command:
- {linux-2.6}/make p3060qds.dtb ARCH=powerpc
-
-then the dtb file will be generated under the following directory:
- {linux-2.6}/arch/powerpc/boot/p3060qds.dtb
-
-
-Booting Linux
-=============
-Place a linux uImage in the TFTP disk area.
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp 3000000 p3060rdb.dtb
- bootm 1000000 2000000 3000000
diff --git a/board/freescale/p3060qds/ddr.c b/board/freescale/p3060qds/ddr.c
deleted file mode 100644
index 9affbf0..0000000
--- a/board/freescale/p3060qds/ddr.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-#include "p3060qds.h"
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- unsigned int lawbar1_target_id;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs,
- fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
-
- /*
- * setup laws for DDR. If not interleaving, presuming half memory on
- * DDR1 and the other half on DDR2
- */
- if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size,
- LAW_TRGT_IF_DDR_INTRLV) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
- } else {
- lawbar1_target_id = LAW_TRGT_IF_DDR_1;
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size,
- lawbar1_target_id) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
- }
- return ddr_size;
-}
-
-struct board_specific_params {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2T;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_params udimm[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 5, 6, 0xff, 2, 0},
- {2, 950, 5, 7, 0xff, 2, 0},
- {2, 1250, 4, 6, 0xff, 2, 0},
- {2, 1350, 5, 7, 0xff, 2, 0},
- {2, 1666, 5, 8, 0xff, 2, 0},
- {1, 850, 4, 5, 0xff, 2, 0},
- {1, 950, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-static const struct board_specific_params rdimm[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 4, 6, 0xff, 2, 0},
- {2, 1050, 4, 7, 0xff, 2, 0},
- {2, 1666, 4, 8, 0xff, 2, 0},
- {1, 850, 4, 5, 0xff, 2, 0},
- {1, 950, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_params *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimm;
- else
- pbsp = udimm;
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twoT_en = pbsp->force_2T;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twoT_en = pbsp_highest->force_2T;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-
-found:
-
- /*
- * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
- * However SPD still claims CL=7 is supported. Extensive tests
- * confirmed this board cannot work stably with CL=7 with this
- * particular DIMM.
- */
- if (ddr_freq >= 800 && ddr_freq < 1066 && \
- !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
- popts->cas_latency_override = 1;
- popts->cas_latency_override_value = 8;
- debug("Override CL to 8\n");
- }
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 60 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
- puts("Initializing....");
-
- if (fsl_use_spd()) {
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
- } else {
- puts("using fixed parameters\n");
- dram_size = fixed_sdram();
- }
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- return dram_size;
-}
diff --git a/board/freescale/p3060qds/eth.c b/board/freescale/p3060qds/eth.c
deleted file mode 100644
index 3f812db..0000000
--- a/board/freescale/p3060qds/eth.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <asm/fsl_dtsec.h>
-
-#include "../common/qixis.h"
-#include "../common/fman.h"
-
-#include "p3060qds_qixis.h"
-
-#define EMI_NONE 0xffffffff
-#define EMI1_RGMII1 0
-#define EMI1_SLOT1 1
-#define EMI1_SLOT2 2
-#define EMI1_SLOT3 3
-#define EMI1_RGMII2 4
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static char *mdio_names[5] = {
- "P3060QDS_MDIO0",
- "P3060QDS_MDIO1",
- "P3060QDS_MDIO2",
- "P3060QDS_MDIO3",
- "P3060QDS_MDIO4",
-};
-
-/*
- * Mapping of all 18 SERDES lanes to board slots.
- * A value of '0' here means that the mapping must be determined
- * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
- */
-static u8 lane_to_slot[] = {
- 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
-};
-
-static char *p3060qds_mdio_name_for_muxval(u32 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u32 muxval)
-{
- struct mii_dev *bus;
- char *name = p3060qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct p3060qds_mdio {
- u32 muxval;
- struct mii_dev *realbus;
-};
-
-static void p3060qds_mux_mdio(u32 muxval)
-{
- u8 brdcfg4;
-
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << 4);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
-}
-
-static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct p3060qds_mdio *priv = bus->priv;
-
- p3060qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct p3060qds_mdio *priv = bus->priv;
-
- p3060qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int p3060qds_mdio_reset(struct mii_dev *bus)
-{
- struct p3060qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int p3060qds_mdio_init(char *realbusname, u32 muxval)
-{
- struct p3060qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate P3060QDS MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate P3060QDS private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = p3060qds_mdio_read;
- bus->write = p3060qds_mdio_write;
- bus->reset = p3060qds_mdio_reset;
- sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- if (mdio_mux[port] == EMI1_RGMII1)
- fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
-
- if (mdio_mux[port] == EMI1_RGMII2)
- fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
-
- if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
- || (srds_prtcl == 0x6))) {
- switch (port) {
- case FM2_DTSEC4:
- fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
- break;
- case FM1_DTSEC4:
- fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
- break;
- default:
- break;
- }
- }
-
- if (mdio_mux[port] == EMI1_SLOT3) {
- switch (port) {
- case FM2_DTSEC3:
- fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
- break;
- case FM1_DTSEC3:
- fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
- break;
- default:
- break;
- }
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- int i, lane, idx;
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
-
- switch (mdio_mux[i]) {
- case EMI1_SLOT1:
- if (lane >= 14) {
- fdt_status_okay_by_alias(fdt,
- "emi1_slot1");
- fdt_status_disabled_by_alias(fdt,
- "emi1_slot1_bk1");
- } else {
- fdt_status_disabled_by_alias(fdt,
- "emi1_slot1");
- fdt_status_okay_by_alias(fdt,
- "emi1_slot1_bk1");
- }
- break;
- case EMI1_SLOT2:
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- break;
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC1)
- fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
-
- if (i == FM1_DTSEC2)
- fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
- break;
- default:
- break;
- }
- }
-#if (CONFIG_SYS_NUM_FMAN == 2)
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- idx = i - FM2_DTSEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
- if (lane >= 0) {
- switch (mdio_mux[i]) {
- case EMI1_SLOT1:
- if (lane >= 14)
- fdt_status_okay_by_alias(fdt,
- "emi1_slot1");
- else
- fdt_status_okay_by_alias(fdt,
- "emi1_slot1_bk1");
- break;
- case EMI1_SLOT2:
- fdt_status_okay_by_alias(fdt,
- "emi1_slot2");
- break;
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt,
- "emi1_slot3");
- break;
- }
- }
- break;
- default:
- break;
- }
- }
-#endif
-}
-
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int sdprtl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- switch (sdprtl) {
- case 0x03:
- case 0x06:
- lane_to_slot[8] = 1;
- lane_to_slot[9] = lane_to_slot[8];
- lane_to_slot[16] = 5;
- lane_to_slot[17] = lane_to_slot[16];
- break;
- case 0x16:
- case 0x19:
- case 0x1C:
- lane_to_slot[8] = 5;
- lane_to_slot[9] = lane_to_slot[8];
- lane_to_slot[16] = 1;
- lane_to_slot[17] = lane_to_slot[16];
- break;
- default:
- puts("Invalid SerDes protocol for P3060QDS\n");
- break;
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
- int i;
- struct fsl_pq_mdio_info dtsec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int srds_cfg = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- initialize_lane_to_slot();
-
- /*
- * Set TBIPA on FM1@DTSEC1. This is needed for configurations
- * where FM1@DTSEC1 isn't used directly, since it provides
- * MDIO for other ports.
- */
- out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- /* Register the 5 muxing front-ends to the MDIO buses */
- if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
- p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-
- if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
- p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-
- if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
- fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
- else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
-
- if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
- fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
- else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
-
- switch (srds_cfg) {
- case 0x03:
- case 0x06:
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0x16:
- case 0x19:
- case 0x1C:
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- default:
- puts("Invalid SerDes protocol for P3060QDS\n");
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1, lane, slot;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- if (QIXIS_READ(present) & (1 << (slot - 1)))
- fm_disable_port(i);
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC1) {
- mdio_mux[i] = EMI1_RGMII1;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- } else if (i == FM1_DTSEC2) {
- mdio_mux[i] = EMI1_RGMII2;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- }
- break;
- default:
- break;
- }
- }
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- int idx = i - FM2_DTSEC1, lane, slot;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- if (QIXIS_READ(present) & (1 << (slot - 1)))
- fm_disable_port(i);
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- default:
- break;
- }
- }
-#endif /* CONFIG_SYS_NUM_FMAN */
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/p3060qds/fixed_ddr.c b/board/freescale/p3060qds/fixed_ddr.c
deleted file mode 100644
index 125988d..0000000
--- a/board/freescale/p3060qds/fixed_ddr.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
-#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
-#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
-#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
-#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
-#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
-#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
-#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
-#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
-#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
-#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
-#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
-#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
-#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
-#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
-#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
-#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
-#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
-#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
-#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
-#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
-#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
-#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
-#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
-#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
-#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
-#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
-#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
-#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
-#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
-#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_TIMING_4 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
-#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {850, 950, &ddr_cfg_regs_900},
- {950, 1050, &ddr_cfg_regs_1000},
- {1050, 1250, &ddr_cfg_regs_1200},
- {0, 0, NULL}
-};
diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c
deleted file mode 100644
index 43e7f28..0000000
--- a/board/freescale/p3060qds/p3060qds.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <configs/P3060QDS.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-#include "../common/qixis.h"
-#include "p3060qds.h"
-#include "p3060qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- u8 sw;
- struct cpu_type *cpu = gd->cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- unsigned int i;
-
- printf("Board: %s", cpu->name);
- puts("QDS, ");
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("Promjet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
-
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
- puts("SERDES Reference Clocks: ");
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < 3; i++) {
- static const char * const freq[] = {"100", "125", "Reserved",
- "156.25"};
- unsigned int clock = (sw >> (2 * i)) & 3;
-
- printf("Bank%u=%sMhz ", i+1, freq[clock]);
- }
- puts("\n");
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
- setbits_be32(&gur->ddrclkdr, 0x00030000);
-
- return 0;
-}
-
-void board_config_serdes_mux(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int cfg = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- switch (cfg) {
- case 0x03:
- case 0x06:
- /* set Lane I,J as SGMII */
- QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
- BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
- break;
- case 0x16:
- case 0x19:
- case 0x1c:
- /* set Lane I,J as Aurora Debug */
- QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
- BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
- break;
- default:
- puts("Invalid SerDes protocol for P3060QDS\n");
- break;
- }
-}
-
-void board_config_usb_mux(void)
-{
- u8 brdcfg4, brdcfg5, brdcfg7;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
- u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
- u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
-
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
- if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
- (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
- brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
-
- } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
- ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
- (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
- brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
-
- } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
- (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
- brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
-
- } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
- ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
- (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
- brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
- } else {
- brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
- }
- QIXIS_WRITE(brdcfg[4], brdcfg4);
-
- brdcfg5 = QIXIS_READ(brdcfg[5]);
- brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
- brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
- QIXIS_WRITE(brdcfg[5], brdcfg5);
-
- brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
- BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
- QIXIS_WRITE(brdcfg[7], brdcfg7);
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
- board_config_serdes_mux();
- board_config_usb_mux();
-
- return 0;
-}
-
-static const char *serdes_clock_to_string(u32 clock)
-{
- switch (clock) {
- case SRDS_PLLCR0_RFCK_SEL_100:
- return "100";
- case SRDS_PLLCR0_RFCK_SEL_125:
- return "125";
- case SRDS_PLLCR0_RFCK_SEL_156_25:
- return "156.25";
- default:
- return "150";
- }
-}
-
-#define NUM_SRDS_BANKS 3
-
-int misc_init_r(void)
-{
- serdes_corenet_t *srds_regs;
- u32 actual[NUM_SRDS_BANKS];
- unsigned int i;
- u8 sw;
-
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < 3; i++) {
- unsigned int clock = (sw >> (2 * i)) & 3;
- switch (clock) {
- case 0:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 3:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- default:
- printf("Warning: SDREFCLK%u switch setting of '10' is "
- "unsupported\n", i + 1);
- break;
- }
- }
-
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
- u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES bank %u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-/*
- * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
- * 18 means CVDD is 1.8v.
- */
-static u8 IO_VSEL[] = {
- 33, 33, 33, 25, 25, 25, 18, 18, 18,
- 33, 33, 33, 25, 25, 25, 18, 18, 18,
- 33, 33, 33, 25, 25, 25, 18, 18, 18,
- 33, 33, 33, 33, 33
-};
-
-#define IO_VSEL_MASK 0x1f
-
-/*
- * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
- * then set status of spi flash nodes to 'disabled' according to CVDD.
- * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
- * flash2, CVDD '18' will select spi flash3.
- */
-void fdt_fixup_board_spi(void *blob)
-{
- u8 sw5 = QIXIS_READ(dutcfg[3]);
-
- switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
- /* 3.3v */
- case 33:
- do_fixup_by_compat(blob, "atmel,at45db081d", "status",
- "disabled", strlen("disabled") + 1, 1);
- do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
- "disabled", strlen("disabled") + 1, 1);
- break;
- /* 2.5v */
- case 25:
- do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
- "disabled", strlen("disabled") + 1, 1);
- do_fixup_by_compat(blob, "spansion,en25q32", "status",
- "disabled", strlen("disabled") + 1, 1);
- do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
- "disabled", strlen("disabled") + 1, 1);
- break;
- /* 1.8v */
- case 18:
- do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
- "disabled", strlen("disabled") + 1, 1);
- do_fixup_by_compat(blob, "spansion,en25q32", "status",
- "disabled", strlen("disabled") + 1, 1);
- do_fixup_by_compat(blob, "atmel,at45db081d", "status",
- "disabled", strlen("disabled") + 1, 1);
- break;
- }
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
- fdt_fixup_board_spi(blob);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-}
diff --git a/board/freescale/p3060qds/p3060qds.h b/board/freescale/p3060qds/p3060qds.h
deleted file mode 100644
index 3da6815..0000000
--- a/board/freescale/p3060qds/p3060qds.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __P3060QDS_H__
-#define __P3060QDS_H__
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/u-boot.h>
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-extern fixed_ddr_parm_t fixed_ddr_parm_0[];
-
-#endif
diff --git a/board/freescale/p3060qds/p3060qds_qixis.h b/board/freescale/p3060qds/p3060qds_qixis.h
deleted file mode 100644
index 4d5d6a2..0000000
--- a/board/freescale/p3060qds/p3060qds_qixis.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __P3060QDS_QIXIS_H__
-#define __P3060QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for P3060QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EC_MODE_MASK 0x0F
-#define BRDCFG4_EC2_MII_EC1_MII 0x00
-#define BRDCFG4_EC2_MII_EC1_USB 0x03
-#define BRDCFG4_EC2_USB_EC1_MII 0x0C
-#define BRDCFG4_EC2_USB_EC1_USB 0x0F
-#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E
-#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B
-#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A
-#define BRDCFG4_EMISEL_MASK 0xF0
-
-#define BRDCFG5_ECLKS_MASK 0x80
-#define BRDCFG5_USB1ID_MASK 0x40
-#define BRDCFG5_USB2ID_MASK 0x20
-#define BRDCFG5_GC2MX_MASK 0x0C
-#define BRDCFG5_T15MX_MASK 0x03
-#define BRDCFG5_ECLKS_IEEE1588_CM 0x80
-#define BRDCFG5_USB1ID_CTRL 0x40
-#define BRDCFG5_USB2ID_CTRL 0x20
-
-#define BRDCFG6_SD1MX_A 0x01
-#define BRDCFG6_SD1MX_B 0x00
-#define BRDCFG6_SD2MX_A 0x02
-#define BRDCFG6_SD2MX_B 0x00
-#define BRDCFG6_SD3MX_A 0x04
-#define BRDCFG6_SD3MX_B 0x00
-#define BRDCFG6_SD4MX_A 0x08
-#define BRDCFG6_SD4MX_B 0x00
-
-#define BRDCFG7_JTAGMX_MASK 0xC0
-#define BRDCFG7_IQ1MX_MASK 0x20
-#define BRDCFG7_G1MX_MASK 0x10
-#define BRDCFG7_D1MX_MASK 0x0C
-#define BRDCFG7_I3MX_MASK 0x03
-#define BRDCFG7_JTAGMX_AURORA 0x00
-#define BRDCFG7_JTAGMX_FPGA 0x80
-#define BRDCFG7_JTAGMX_COP_JTAG 0xC0
-#define BRDCFG7_IQ1MX_IRQ_EVT 0x00
-#define BRDCFG7_IQ1MX_USB2 0x20
-#define BRDCFG7_G1MX_USB1 0x00
-#define BRDCFG7_G1MX_TSEC3 0x10
-#define BRDCFG7_D1MX_DMA 0x00
-#define BRDCFG7_D1MX_TSEC3USB 0x04
-#define BRDCFG7_D1MX_HDLC2 0x08
-#define BRDCFG7_I3MX_UART2_I2C34 0x00
-#define BRDCFG7_I3MX_GPIO_EVT 0x01
-#define BRDCFG7_I3MX_USB1 0x02
-#define BRDCFG7_I3MX_TSEC3 0x03
-
-#endif
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
index d8f754c..893f4b7 100644
--- a/board/mcc200/lcd.c
+++ b/board/mcc200/lcd.c
@@ -21,6 +21,7 @@
#include <common.h>
#include <lcd.h>
#include <mpc5xxx.h>
+#include <malloc.h>
#ifdef CONFIG_LCD
@@ -210,4 +211,23 @@ void show_progress (int size, int tot)
}
#endif
+
+int bmp_display(ulong addr, int x, int y)
+{
+ int ret;
+ bmp_image_t *bmp = (bmp_image_t *)addr;
+
+ if (!bmp) {
+ printf("There is no valid bmp file at the given address\n");
+ return 1;
+ }
+
+ ret = lcd_display_bitmap((ulong)bmp, x, y);
+
+ if ((unsigned long)bmp != addr)
+ free(bmp);
+
+ return ret;
+}
+
#endif /* CONFIG_LCD */
diff --git a/board/overo/overo.c b/board/overo/overo.c
index f973870..c6d50a0 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -101,16 +101,6 @@ int board_init(void)
}
/*
- * Routine: omap_rev_string
- * Description: For SPL builds output board rev
- */
-#ifdef CONFIG_SPL_BUILD
-void omap_rev_string(void)
-{
-}
-#endif
-
-/*
* Routine: get_board_revision
* Description: Returns the board revision
*/
diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
index 3583d01..d975209 100644
--- a/board/qi/qi_lb60/qi_lb60.c
+++ b/board/qi/qi_lb60/qi_lb60.c
@@ -69,7 +69,7 @@ static void gpio_init(void)
static void cpm_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- uint32_t reg = readw(&cpm->clkgr);
+ uint32_t reg = readl(&cpm->clkgr);
reg |= CPM_CLKGR_IPU |
CPM_CLKGR_CIM |
@@ -81,7 +81,7 @@ static void cpm_init(void)
CPM_CLKGR_UDC |
CPM_CLKGR_AIC1;
- writew(reg, &cpm->clkgr);
+ writel(reg, &cpm->clkgr);
}
int board_early_init_f(void)
diff --git a/board/freescale/p3060qds/Makefile b/board/samsung/common/Makefile
index ae136f4..0bcd594 100644
--- a/board/freescale/p3060qds/Makefile
+++ b/board/samsung/common/Makefile
@@ -1,7 +1,6 @@
#
-# Copyright 2011 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2012 Samsung Electronics
+# Lukasz Majewski <l.majewski@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -24,26 +23,16 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libsamsung.o
-COBJS-y += $(BOARD).o
-COBJS-y += ddr.o
-COBJS-y += eth.o
-COBJS-y += fixed_ddr.o
+COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
#########################################################################
# defines $(obj).depend target
diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c
new file mode 100644
index 0000000..d6c3d37
--- /dev/null
+++ b/board/samsung/common/multi_i2c.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+/* Handle multiple I2C buses instances */
+int get_multi_scl_pin(void)
+{
+ unsigned int bus = I2C_GET_BUS();
+
+ switch (bus) {
+ case I2C_0: /* I2C_0 definition - compatibility layer */
+ case I2C_5:
+ return CONFIG_SOFT_I2C_I2C5_SCL;
+ case I2C_9:
+ return CONFIG_SOFT_I2C_I2C9_SCL;
+ default:
+ printf("I2C_%d not supported!\n", bus);
+ };
+
+ return 0;
+}
+
+int get_multi_sda_pin(void)
+{
+ unsigned int bus = I2C_GET_BUS();
+
+ switch (bus) {
+ case I2C_0: /* I2C_0 definition - compatibility layer */
+ case I2C_5:
+ return CONFIG_SOFT_I2C_I2C5_SDA;
+ case I2C_9:
+ return CONFIG_SOFT_I2C_I2C9_SDA;
+ default:
+ printf("I2C_%d not supported!\n", bus);
+ };
+
+ return 0;
+}
+
+int multi_i2c_init(void)
+{
+ return 0;
+}
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
index 30a5835..1effc9c 100644
--- a/board/samsung/goni/lowlevel_init.S
+++ b/board/samsung/goni/lowlevel_init.S
@@ -79,11 +79,7 @@ skip_check_didle:
str r1, [r0, #0x0] @ GPIO_CON_OFFSET
ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
-#ifdef CONFIG_ONENAND_IPL
- orr r1, r1, #(1 << 1) @ 1 * 1-bit
-#else
bic r1, r1, #(1 << 1)
-#endif
str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
/* Don't setup at s5pc100 */
@@ -182,7 +178,6 @@ skip_check_didle:
/* Do not release retention here for S5PC110 */
streq r1, [r0]
-#ifndef CONFIG_ONENAND_IPL
/* Disable Watchdog */
ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
@@ -193,7 +188,6 @@ skip_check_didle:
ldrne r0, =S5PC110_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
-#endif
/* S5PC100 has 3 groups of interrupt sources */
ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
@@ -207,7 +201,6 @@ skip_check_didle:
str r3, [r1, #0x14] @ INTENCLEAR
str r3, [r2, #0x14] @ INTENCLEAR
-#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @ INTSELECT
str r5, [r1, #0xc] @ INTSELECT
@@ -217,120 +210,12 @@ skip_check_didle:
str r5, [r0, #0xf00] @ INTADDRESS
str r5, [r1, #0xf00] @ INTADDRESS
str r5, [r2, #0xf00] @ INTADDRESS
-#endif
-#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
bl internal_ram_init
-#endif
-
-#ifdef CONFIG_ONENAND_IPL
- /* init system clock */
- bl system_clock_init
-
- /* OneNAND Sync Read Support at S5PC110 only
- * RM[15] : Sync Read
- * BRWL[14:12] : 7 CLK
- * BL[11:9] : Continuous
- * VHF[3] : Very High Frequency Enable (Over 83MHz)
- * HF[2] : High Frequency Enable (Over 66MHz)
- * WM[1] : Sync Write
- */
- cmp r7, r8
- ldrne r1, =0xE006
- ldrne r0, =0xB001E442
- strneh r1, [r0]
-
- /*
- * GCE[26] : Gated Clock Enable
- * RPE[17] : Enables Read Prefetch
- */
- ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
- ldrne r0, =0xB0600000
- strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
- ldrne r1, =0x1212
- strne r1, [r0, #0x108]
-
- /* Board detection to set proper memory configuration */
- cmp r7, r8
- moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
- movne r9, #2 /* r9 has 2Gib default at s5pc110 */
-
- ldr r2, =0xE0200200
- ldr r4, [r2, #0x48]
-
- bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
- bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
- bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
- str r1, [r2, #0x48]
- /* For write completion */
- nop
- nop
-
- ldr r3, [r2, #0x44]
- and r1, r3, #(0x7 << 2)
- mov r1, r1, lsr #2
- cmp r1, #0x5
- moveq r9, #3
- cmp r1, #0x6
- moveq r9, #1
- cmp r1, #0x7
- moveq r9, #2
- and r0, r3, #(0x1 << 1)
- mov r0, r0, lsr #1
- orr r1, r1, r0, lsl #3
- cmp r1, #0x8
- moveq r9, #3
- and r1, r3, #(0x7 << 2)
- mov r1, r1, lsr #2
- and r0, r3, #(0x1 << 7)
- mov r0, r0, lsr #7
- orr r1, r1, r0, lsl #3
- cmp r1, #0x9
- moveq r9, #3
- str r4, [r2, #0x48] /* Restore PULLUP configuration */
-
- bl mem_ctrl_asm_init
-
- /* Wakeup support. Don't know if it's going to be used, untested. */
- ldreq r0, =S5PC100_RST_STAT
- ldrne r0, =S5PC110_RST_STAT
- ldr r1, [r0]
- biceq r1, r1, #0xfffffff7
- moveq r2, #(1 << 3)
- bicne r1, r1, #0xfffeffff
- movne r2, #(1 << 16)
- cmp r1, r2
- bne 1f
-wakeup:
- /* turn off L2 cache */
- bl l2_cache_disable
-
- cmp r7, r8
- ldreq r0, =0xC100
- ldrne r0, =0xC110
-
- /* invalidate L2 cache also */
- bl invalidate_dcache
-
- /* turn on L2 cache */
- bl l2_cache_enable
-
- cmp r7, r8
- /* Load return address and jump to kernel */
- ldreq r0, =S5PC100_INFORM0
- ldrne r0, =S5PC110_INFORM0
-
- /* r1 = physical address of s5pc1xx_cpu_resume function */
- ldr r1, [r0]
- /* Jump to kernel (sleep-s5pc1xx.S) */
- mov pc, r1
- nop
- nop
-#else
cmp r7, r8
/* Clear wakeup status register */
ldreq r0, =S5PC100_WAKEUP_STAT
@@ -347,7 +232,6 @@ wakeup:
orr r1, r1, r2
str r1, [r0]
-#endif
b 1f
didle_wakeup:
@@ -517,7 +401,6 @@ system_clock_init:
mov pc, lr
-#ifndef CONFIG_ONENAND_IPL
internal_ram_init:
ldreq r0, =0xE3800000
ldrne r0, =0xF1500000
@@ -525,9 +408,7 @@ internal_ram_init:
str r1, [r0]
mov pc, lr
-#endif
-#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
@@ -582,4 +463,3 @@ uart_asm_init:
str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
200:
mov pc, lr
-#endif
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
index 6d18835..6f9a554 100644
--- a/board/samsung/smdkc100/lowlevel_init.S
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -50,12 +50,10 @@ lowlevel_init:
orr r0, r0, #0x0
str r5, [r0]
-#ifndef CONFIG_ONENAND_IPL
/* setting SRAM */
ldr r0, =S5PC100_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
-#endif
/* S5PC100 has 3 groups of interrupt sources */
ldr r0, =S5PC100_VIC0_BASE @0xE4000000
@@ -68,7 +66,6 @@ lowlevel_init:
str r3, [r1, #0x14] @INTENCLEAR
str r3, [r2, #0x14] @INTENCLEAR
-#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @INTSELECT
str r5, [r1, #0xc] @INTSELECT
@@ -78,54 +75,17 @@ lowlevel_init:
str r5, [r0, #0xf00] @INTADDRESS
str r5, [r1, #0xf00] @INTADDRESS
str r5, [r2, #0xf00] @INTADDRESS
-#endif
-#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
/* for TZPC */
bl tzpc_asm_init
-#endif
-
-#ifdef CONFIG_ONENAND_IPL
- /* init system clock */
- bl system_clock_init
-
- bl mem_ctrl_asm_init
-
- /* Wakeup support. Don't know if it's going to be used, untested. */
- ldr r0, =S5PC100_RST_STAT
- ldr r1, [r0]
- bic r1, r1, #0xfffffff7
- cmp r1, #0x8
- beq wakeup_reset
-#endif
1:
mov lr, r9
mov pc, lr
-#ifdef CONFIG_ONENAND_IPL
-wakeup_reset:
-
- /* Clear wakeup status register */
- ldr r0, =S5PC100_WAKEUP_STAT
- ldr r1, [r0]
- str r1, [r0]
-
- /* Load return address and jump to kernel */
- ldr r0, =S5PC100_INFORM0
-
- /* r1 = physical address of s5pc100_cpu_resume function */
- ldr r1, [r0]
-
- /* Jump to kernel (sleep.S) */
- mov pc, r1
- nop
- nop
-#endif
-
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
@@ -178,7 +138,6 @@ system_clock_init:
mov pc, lr
-#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
@@ -212,4 +171,3 @@ tzpc_asm_init:
str r1, [r0, #0x810]
mov pc, lr
-#endif
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index a8b2b11..e11a892 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -59,6 +59,8 @@ static int hwrevision(int rev)
return (board_rev & 0xf) == rev;
}
+struct s3c_plat_otg_data s5pc210_otg_data;
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -73,6 +75,21 @@ int board_init(void)
return 0;
}
+void i2c_init_board(void)
+{
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct exynos4_gpio_part2 *gpio2 =
+ (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+ /* I2C_5 -> PMIC */
+ s5p_gpio_direction_output(&gpio1->b, 7, 1);
+ s5p_gpio_direction_output(&gpio1->b, 6, 1);
+ /* I2C_9 -> FG */
+ s5p_gpio_direction_output(&gpio2->y4, 0, 1);
+ s5p_gpio_direction_output(&gpio2->y4, 1, 1);
+}
+
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
@@ -259,6 +276,12 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
+
+void board_usb_init(void)
+{
+ debug("USB_udc_probe\n");
+ s3c_udc_probe(&s5pc210_otg_data);
+}
#endif
static void pmic_reset(void)
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index a1e2bfe..b75e62c 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -28,6 +28,7 @@
#include <common.h>
#include <config.h>
#include <netdev.h>
+#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
@@ -69,6 +70,14 @@ int fsl_init2 (void) {
}
#endif
+void board_init(void)
+{
+ gpio_init();
+#ifdef CONFIG_SYS_FSL_2
+ fsl_init2();
+#endif
+}
+
int board_eth_init(bd_t *bis)
{
int ret = 0;