Merge branch 'master' of git://git.denx.de/u-boot-arm into HEAD

Quick manual fixup to merge the USB boot related defines and TPM related
defines.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>

6 files changed, 135 insertions, 14 deletions

diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi
index 86c7bab..f379622 100644
--- a/board/avionic-design/dts/tegra20-tamonten.dtsi
+++ b/board/avionic-design/dts/tegra20-tamonten.dtsi
@@ -279,6 +279,17 @@
 		status = "okay";
 	};
 
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
 	i2c@7000c000 {
 		clock-frequency = <400000>;
 		status = "okay";
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 1d7cf89..4c1b08d 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -32,17 +32,6 @@
 		clock-frequency = <216000000>;
 	};
 
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
-	};
-
 	i2c@7000c000 {
 		status = "disabled";
 	};
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c
index 26b6ec7..87d7aa2 100644
--- a/board/nvidia/common/emc.c
+++ b/board/nvidia/common/emc.c
@@ -40,7 +40,7 @@ int board_emc_init(void)
 {
 	unsigned rate;
 
-	switch (tegra_get_chip_type()) {
+	switch (tegra_get_chip_sku()) {
 	default:
 	case TEGRA_SOC_T20:
 		rate  = EMC_SDRAM_RATE_T20;
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
new file mode 100644
index 0000000..836169f
--- /dev/null
+++ b/board/nvidia/dts/tegra30-beaver.dts
@@ -0,0 +1,71 @@
+/dts-v1/;
+
+#include "tegra30.dtsi"
+
+/ {
+	model = "NVIDIA Beaver";
+	compatible = "nvidia,beaver", "nvidia,tegra30";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x7ff00000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+		spi-flash@1 {
+			compatible = "winbond,w25q32";
+			reg = <1>;
+			spi-max-frequency = <20000000>;
+		};
+	};
+
+	sdhci@78000000 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		bus-width = <4>;
+	};
+
+	sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+};
diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts
index 8b303bf..24658c1 100644
--- a/board/samsung/dts/exynos5250-snow.dts
+++ b/board/samsung/dts/exynos5250-snow.dts
@@ -55,4 +55,18 @@
 			compatible = "maxim,max77686_pmic";
 		};
 	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
 };
diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c
index d8f3c1e..c0bcf46 100644
--- a/board/samsung/smdk5250/spl_boot.c
+++ b/board/samsung/smdk5250/spl_boot.c
@@ -32,6 +32,21 @@ enum boot_mode {
 };
 
 	typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
+	typedef u32 (*usb_copy_func_t)(void);
+
+/*
+ * Set/clear program flow prediction and return the previous state.
+ */
+static int config_branch_prediction(int set_cr_z)
+{
+	unsigned int cr;
+
+	/* System Control Register: 11th bit Z Branch prediction enable */
+	cr = get_cr();
+	set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
+
+	return cr & CR_Z;
+}
 
 /*
 * Copy U-boot from mmc to RAM:
@@ -41,10 +56,20 @@ enum boot_mode {
 void copy_uboot_to_ram(void)
 {
 	spi_copy_func_t spi_copy;
-	enum boot_mode bootmode;
+	usb_copy_func_t usb_copy;
+
+	int is_cr_z_set;
+	unsigned int sec_boot_check;
+	enum boot_mode bootmode = BOOT_MODE_OM;
 	u32 (*copy_bl2)(u32, u32, u32);
 
-	bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
+	/* Read iRAM location to check for secondary USB boot mode */
+	sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
+	if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
+		bootmode = BOOT_MODE_USB;
+
+	if (bootmode == BOOT_MODE_OM)
+		bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
 
 	switch (bootmode) {
 	case BOOT_MODE_SERIAL:
@@ -57,6 +82,17 @@ void copy_uboot_to_ram(void)
 		copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
 						CONFIG_SYS_TEXT_BASE);
 		break;
+	case BOOT_MODE_USB:
+		/*
+		 * iROM needs program flow prediction to be disabled
+		 * before copy from USB device to RAM
+		 */
+		is_cr_z_set = config_branch_prediction(0);
+		usb_copy = *(usb_copy_func_t *)
+				EXYNOS_COPY_USB_FNPTR_ADDR;
+		usb_copy();
+		config_branch_prediction(is_cr_z_set);
+		break;
 	default:
 		break;
 	}