Merge branch 'master' of git://git.denx.de/u-boot-arm

17 files changed, 1422 insertions, 193 deletions

diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index c028a53..4df4e9b 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -108,17 +108,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-	}
-	return 0;
-}
-
 #ifdef CONFIG_RESET_PHY_R
 void mv_phy_88e1121_init(char *name)
 {
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index c959bf8..93d1400 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -110,17 +110,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-	}
-	return 0;
-}
-
 #ifdef CONFIG_MV88E61XX_SWITCH
 void reset_phy(void)
 {
diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c
index c00a08a..d006b2d 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd_base/openrd_base.c
@@ -113,17 +113,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-	}
-	return 0;
-}
-
 #ifdef CONFIG_RESET_PHY_R
 /* Configure and enable MV88E1116 PHY */
 void reset_phy(void)
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index 8713a3c..0d76146 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -109,17 +109,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-	}
-	return 0;
-}
-
 void mv_phy_88e1116_init(char *name)
 {
 	u16 reg;
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 547126a..173a7b8 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -108,17 +108,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-	}
-	return 0;
-}
-
 #ifdef CONFIG_RESET_PHY_R
 /* Configure and enable MV88E1116 PHY */
 void reset_phy(void)
diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh
index 702b436..d869dd2 100755
--- a/board/armltd/integrator/split_by_variant.sh
+++ b/board/armltd/integrator/split_by_variant.sh
@@ -10,12 +10,12 @@ then
 # ---------------------------------------------------------
 # Set the platform defines
 # ---------------------------------------------------------
-echo -n	"/* Integrator configuration implied "	 > ${config_file}
-echo	" by Makefile target */"		>> ${config_file}
-echo -n	"#define CONFIG_INTEGRATOR"		>> ${config_file}
-echo	" /* Integrator board */"		>> ${config_file}
-echo -n	"#define CONFIG_ARCH_INTEGRATOR"	>> ${config_file}
-echo	" 1 /* Integrator/AP	 */"		>> ${config_file}
+cat > ${config_file} << _EOF
+/* Integrator configuration implied by Makefile target */
+#define CONFIG_INTEGRATOR /* Integrator board */
+#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */
+_EOF
+
 # ---------------------------------------------------------
 #	Set the core module defines according to Core Module
 # ---------------------------------------------------------
@@ -50,37 +50,37 @@ else
 
 	ap720t_config)
 	cpu="arm720t"
-	echo -n	"#define CONFIG_CM720T"			>> ${config_file}
-	echo	" 1 /* CPU core is ARM720T */ "		>> ${config_file}
+	echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \
+		>> ${config_file}
 	variant="Core module CM720T"
 	;;
 
 	ap922_XA10_config)
 	cpu="arm_intcm"
 	variant="unported core module CM922T_XA10"
-	echo -n	"#define CONFIG_CM922T_XA10"		>> ${config_file}
-	echo	" 1 /* CPU core is ARM922T_XA10 */"	>> ${config_file}
+	echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
+		>> ${config_file}
 	;;
 
 	ap920t_config)
 	cpu="arm920t"
 	variant="Core module CM920T"
-	echo -n	"#define CONFIG_CM920T"			>> ${config_file}
-	echo	" 1 /* CPU core is ARM920T */"		>> ${config_file}
+	echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
+		>> ${config_file}
 	;;
 
 	ap926ejs_config)
 	cpu="arm926ejs"
 	variant="Core module CM926EJ-S"
-	echo -n	"#define CONFIG_CM926EJ_S"		>> ${config_file}
-	echo	" 1 /* CPU core is ARM926EJ-S */ "	>> ${config_file}
+	echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
+		>> ${config_file}
 	;;
 
 	ap946es_config)
 	cpu="arm946es"
 	variant="Core module CM946E-S"
-	echo -n	"#define CONFIG_CM946E_S"		>> ${config_file}
-	echo	" 1 /* CPU core is ARM946E-S */ "	>> ${config_file}
+	echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
+		>> ${config_file}
 	;;
 
 	*)
@@ -94,33 +94,26 @@ fi
 
 case "$cpu" in
 	arm_intcm)
-	echo "/* Core module undefined/not ported */"	>> ${config_file}
-	echo "#define CONFIG_ARM_INTCM 1"		>> ${config_file}
-	echo -n	"#undef CONFIG_CM_MULTIPLE_SSRAM"	>> ${config_file}
-	echo -n	"	/* CM may not have "		>> ${config_file}
-	echo	"multiple SSRAM mapping */"		>> ${config_file}
-	echo -n	"#undef CONFIG_CM_SPD_DETECT "		>> ${config_file}
-	echo -n	" /* CM may not support SPD "		>> ${config_file}
-	echo	"query */"				>> ${config_file}
-	echo -n	"#undef CONFIG_CM_REMAP	"		>> ${config_file}
-	echo -n	" /* CM may not support "		>> ${config_file}
-	echo	"remapping */"				>> ${config_file}
-	echo -n	"#undef CONFIG_CM_INIT	"		>> ${config_file}
-	echo -n	" /* CM may not have	"		>> ${config_file}
-	echo	"initialization reg */"			>> ${config_file}
-	echo -n	"#undef CONFIG_CM_TCRAM	"		>> ${config_file}
-	echo	" /* CM may not have TCRAM */"		>> ${config_file}
-	echo -n	" /* May not be processor "		>> ${config_file}
-	echo	"without cache support */"		>> ${config_file}
-	echo	"#define CONFIG_SYS_NO_ICACHE 1"	>> ${config_file}
-	echo	"#define CONFIG_SYS_NO_DCACHE 1"	>> ${config_file}
+	cat >> ${config_file} << _EOF
+/* Core module undefined/not ported */
+#define CONFIG_ARM_INTCM 1
+#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
+#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
+#undef CONFIG_CM_REMAP /* CM may not support remapping */
+#undef CONFIG_CM_INIT  /* CM may not have initialization reg */
+#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
+/* May not be processor without cache support */
+#define CONFIG_SYS_NO_ICACHE 1
+#define CONFIG_SYS_NO_DCACHE 1
+_EOF
 	;;
 
 	arm720t)
-	echo -n	" /* May not be processor "		>> ${config_file}
-	echo	"without cache support */"		>> ${config_file}
-	echo	"#define CONFIG_SYS_NO_ICACHE 1"	>> ${config_file}
-	echo	"#define CONFIG_SYS_NO_DCACHE 1"	>> ${config_file}
+	cat >> ${config_file} << _EOF
+/* May not be processor without cache support */
+#define CONFIG_SYS_NO_ICACHE 1
+#define CONFIG_SYS_NO_DCACHE 1
+_EOF
 	;;
 esac
 
@@ -129,12 +122,11 @@ else
 # ---------------------------------------------------------
 # Set the platform defines
 # ---------------------------------------------------------
-echo -n "/* Integrator configuration implied "   > ${config_file}
-echo    " by Makefile target */"		>> ${config_file}
-echo -n "#define CONFIG_INTEGRATOR"		>> ${config_file}
-echo	 " /* Integrator board */"		>> ${config_file}
-echo -n "#define CONFIG_ARCH_CINTEGRATOR"	>> ${config_file}
-echo     " 1 /* Integrator/CP   */"		>> ${config_file}
+cat >> ${config_file} << _EOF
+/* Integrator configuration implied by Makefile target */
+#define CONFIG_INTEGRATOR /* Integrator board */
+#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP   */
+_EOF
 
 cpu="arm_intcm"
 variant="unknown core module"
@@ -163,37 +155,37 @@ else
 	cp922_XA10_config)
 	cpu="arm_intcm"
 	variant="unported core module CM922T_XA10"
-	echo -n "#define CONFIG_CM922T_XA10"		>> ${config_file}
-	echo    " 1 /* CPU core is ARM922T_XA10 */"	>> ${config_file}
+	echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
+		>> ${config_file}
 	;;
 
 	cp920t_config)
 	cpu="arm920t"
 	variant="Core module CM920T"
-	echo -n "#define CONFIG_CM920T"			>> ${config_file}
-	echo    " 1 /* CPU core is ARM920T */"		>> ${config_file}
+	echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
+		>> ${config_file}
 	;;
 
 	cp926ejs_config)
 	cpu="arm926ejs"
 	variant="Core module CM926EJ-S"
-	echo -n "#define CONFIG_CM926EJ_S"		>> ${config_file}
-	echo    " 1 /* CPU core is ARM926EJ-S */ "	>> ${config_file}
+	echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
+		>> ${config_file}
 	;;
 
 
 	cp946es_config)
 	cpu="arm946es"
 	variant="Core module CM946E-S"
-	echo -n "#define CONFIG_CM946E_S"		>> ${config_file}
-	echo    " 1 /* CPU core is ARM946E-S */ "	>> ${config_file}
+	echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
+		>> ${config_file}
 	;;
 
 	cp1136_config)
 	cpu="arm1136"
 	variant="Core module CM1136EJF-S"
-	echo -n "#define CONFIG_CM1136EJF_S"		>> ${config_file}
-	echo    " 1 /* CPU core is ARM1136JF-S */ "	>> ${config_file}
+	echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \
+		>> ${config_file}
 	;;
 
 	*)
@@ -208,22 +200,15 @@ fi
 
 if [ "$cpu" = "arm_intcm" ]
 then
-	echo "/* Core module undefined/not ported */"	>> ${config_file}
-	echo "#define CONFIG_ARM_INTCM 1"		>> ${config_file}
-	echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"	>> ${config_file}
-	echo -n "  /* CM may not have "			>> ${config_file}
-	echo    "multiple SSRAM mapping */"		>> ${config_file}
-	echo -n "#undef CONFIG_CM_SPD_DETECT "		>> ${config_file}
-	echo -n " /* CM may not support SPD "		>> ${config_file}
-	echo    "query */"				>> ${config_file}
-	echo -n "#undef CONFIG_CM_REMAP  "		>> ${config_file}
-	echo -n " /* CM may not support "		>> ${config_file}
-	echo    "remapping */"				>> ${config_file}
-	echo -n "#undef CONFIG_CM_INIT  "		>> ${config_file}
-	echo -n " /* CM may not have  "			>> ${config_file}
-	echo    "initialization reg */"			>> ${config_file}
-	echo -n "#undef CONFIG_CM_TCRAM  "		>> ${config_file}
-	echo    " /* CM may not have TCRAM */"		>> ${config_file}
+	cat >> ${config_file} << _EOF
+/* Core module undefined/not ported */
+#define CONFIG_ARM_INTCM 1
+#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
+#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
+#undef CONFIG_CM_REMAP /* CM may not support remapping */
+#undef CONFIG_CM_INIT /* CM may not have initialization reg */
+#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
+_EOF
 fi
 
 fi # ap
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
new file mode 100644
index 0000000..ee5c0d8
--- /dev/null
+++ b/board/armltd/vexpress/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= ca9x4_ct_vxp.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c
new file mode 100644
index 0000000..48dfc8c
--- /dev/null
+++ b/board/armltd/vexpress/ca9x4_ct_vxp.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/systimer.h>
+#include <asm/arch/sysctrl.h>
+#include <asm/arch/wdt.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
+
+static void flash__init(void);
+static void vexpress_timer_init(void);
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(ulong loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+	gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
+	gd->flags = 0;
+
+	icache_enable();
+	flash__init();
+	vexpress_timer_init();
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+static void flash__init(void)
+{
+	/* Setup the sytem control register to allow writing to flash */
+	writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
+	       &sysctrl_base->scflashctrl);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+/*
+ * Start timer:
+ *    Setup a 32 bit timer, running at 1KHz
+ *    Versatile Express Motherboard provides 1 MHz timer
+ */
+static void vexpress_timer_init(void)
+{
+	/*
+	 * Set clock frequency in system controller:
+	 *   VEXPRESS_REFCLK is 32KHz
+	 *   VEXPRESS_TIMCLK is 1MHz
+	 */
+	writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
+	       SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
+	       readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
+
+	/*
+	 * Set Timer0 to be:
+	 *   Enabled, free running, no interrupt, 32-bit, wrapping
+	 */
+	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+	writel(SYSTIMER_EN | SYSTIMER_32BIT | \
+	       readl(&systimer_base->timer0control), \
+	       &systimer_base->timer0control);
+
+	reset_timer_masked();
+}
+
+/* Use the ARM Watchdog System to cause reset */
+void reset_cpu(ulong addr)
+{
+	writeb(WDT_EN, &wdt_base->wdogcontrol);
+	writel(WDT_RESET_LOAD, &wdt_base->wdogload);
+	while (1)
+		;
+}
+
+/*
+ * Delay x useconds AND perserve advance timstamp value
+ *     assumes timer is ticking at 1 msec
+ */
+void udelay(ulong usec)
+{
+	ulong tmo, tmp;
+
+	tmo = usec / 1000;
+	tmp = get_timer(0);	/* get current timestamp */
+
+	/*
+	 * If setting this forward will roll time stamp	then
+	 * reset "advancing" timestamp to 0 and set lastdec value
+	 * otherwise set the advancing stamp to the wake up time
+	 */
+	if ((tmo + tmp + 1) < tmp)
+		reset_timer_masked();
+	else
+		tmo += tmp;
+
+	while (get_timer_masked() < tmo)
+		; /* loop till wakeup event */
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+	lastdec = readl(&systimer_base->timer0value) / 1000;
+	timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = readl(&systimer_base->timer0value) / 1000;
+
+	if (lastdec >= now) {	/* normal mode (non roll) */
+		timestamp += lastdec - now;
+	} else {		/* count down timer overflowed */
+		/*
+		 * nts = ts + ld - now
+		 * ts = old stamp, ld = time before passing through - 1
+		 * now = amount of time after passing though - 1
+		 * nts = new "advancing time stamp"
+		 */
+		timestamp += lastdec + SYSTIMER_RELOAD - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void lowlevel_init(void)
+{
+}
+
+ulong get_board_rev(void){
+	return readl((u32 *)SYS_ID);
+}
diff --git a/board/armltd/vexpress/config.mk b/board/armltd/vexpress/config.mk
new file mode 100644
index 0000000..2d797d7
--- /dev/null
+++ b/board/armltd/vexpress/config.mk
@@ -0,0 +1,23 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Linux-Kernel is expected to be at 0x60008000
+#
+TEXT_BASE = 0x60800000
+LDSCRIPT := $(SRCTREE)/board/armltd/vexpress/u-boot.lds
diff --git a/board/armltd/vexpress/u-boot.lds b/board/armltd/vexpress/u-boot.lds
new file mode 100644
index 0000000..5ac62f2
--- /dev/null
+++ b/board/armltd/vexpress/u-boot.lds
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) }
+
+	. = ALIGN(4);
+	.data : { *(.data)
+	__datarel_start = .;
+		*(.data.rel)
+	__datarelrolocal_start = .;
+		*(.data.rel.ro.local)
+	__datarellocal_start = .;
+		*(.data.rel.local)
+	__datarelro_start = .;
+		*(.data.rel.ro)
+	}
+
+	__got_start = .;
+	. = ALIGN(4);
+	.got : { *(.got) }
+	__got_end = .;
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index e509383..9abc29c 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -27,6 +27,7 @@
 #include <asm/arch/mx31-regs.h>
 #include <nand.h>
 #include <fsl_pmic.h>
+#include <mxc_gpio.h>
 #include "qong_fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -41,9 +42,9 @@ int dram_init (void)
 
 static void qong_fpga_reset(void)
 {
-	mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
 	udelay(30);
-	mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
 
 	udelay(300);
 }
@@ -66,11 +67,11 @@ int board_early_init_f (void)
 
 	/* FPGA reset  Pin */
 	/* rstn = 0 */
-	mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
-	mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+	mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
 
 	/* set interrupt pin as input */
-	mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
+	mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
 
 #endif
 
@@ -206,27 +207,27 @@ static void board_nand_setup(void)
 	qong_fpga_reset();
 
 	/* Enable NAND flash */
-	mx31_gpio_set(15, 1);
-	mx31_gpio_set(14, 1);
-	mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT);
-	mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN);
-	mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN);
-	mx31_gpio_set(15, 0);
+	mxc_gpio_set(15, 1);
+	mxc_gpio_set(14, 1);
+	mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_set(15, 0);
 
 }
 
 int qong_nand_rdy(void *chip)
 {
 	udelay(1);
-	return mx31_gpio_get(16);
+	return mxc_gpio_get(16);
 }
 
 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
 {
 	if (chip >= 0)
-		mx31_gpio_set(15, 0);
+		mxc_gpio_set(15, 0);
 	else
-		mx31_gpio_set(15, 1);
+		mxc_gpio_set(15, 1);
 
 }
 
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 75d642b..84386e6 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -33,12 +33,10 @@
 #include <fsl_esdhc.h>
 #include <fsl_pmic.h>
 #include <mc13892.h>
-#include "mx51evk.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static u32 system_rev;
-struct io_board_ctrl *mx51_io_board;
 
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h
deleted file mode 100644
index 2854e71..0000000
--- a/board/freescale/mx51evk/mx51evk.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BOARD_FREESCALE_MX51_EVK_H__
-#define __BOARD_FREESCALE_MX51_EVK_H__
-
-#ifndef __ASSEMBLY__
-struct io_board_ctrl {
-	u16 led_ctrl;		/* 0x00 */
-	u16 resv1[0x03];
-	u16 sb_stat;		/* 0x08 */
-	u16 resv2[0x03];
-	u16 int_stat;		/* 0x10 */
-	u16 resv3[0x07];
-	u16 int_rest;		/* 0x20 */
-	u16 resv4[0x0B];
-	u16 int_mask;		/* 0x38 */
-	u16 resv5[0x03];
-	u16 id1;		/* 0x40 */
-	u16 resv6[0x03];
-	u16 id2;		/* 0x48 */
-	u16 resv7[0x03];
-	u16 version;		/* 0x50 */
-	u16 resv8[0x03];
-	u16 id3;		/* 0x58 */
-	u16 resv9[0x03];
-	u16 sw_reset;		/* 0x60 */
-};
-#endif
-
-#endif
diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile
new file mode 100644
index 0000000..309e3a3
--- /dev/null
+++ b/board/ttcontrol/vision2/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= vision2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ttcontrol/vision2/config.mk b/board/ttcontrol/vision2/config.mk
new file mode 100644
index 0000000..59f3367
--- /dev/null
+++ b/board/ttcontrol/vision2/config.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
+TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
new file mode 100644
index 0000000..ed531db
--- /dev/null
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -0,0 +1,209 @@
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# (C) Copyright 2010
+# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, nand, onenand, sd
+
+BOOT_FROM	spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+#######################
+### Disable WDOG ###
+#######################
+DATA 2 0x73f98000 0x30
+
+#######################
+### SET DDR Clk     ###
+#######################
+
+# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+DATA 4 0x73FD4018 0x000024C0
+
+# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+DATA 4 0x73FD4038 0x2010241
+
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8600 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8604 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8608 0x00000187
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa860c 0x00000187
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8614 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+DATA 4 0x73fa86a8 0x00000187
+
+#######################
+### Settings IOMUXC ###
+#######################
+
+# DDR IOMUX configuration
+# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+DATA 4 0x73fa84b8 0x000000e7
+# PVTC MAX (at GPC, PGR reg)
+#DATA 4 0x73FD8004 0x1fc00000
+
+#DQM0 DS high slew rate slow
+DATA 4 0x73fa84d4 0x000000e4
+#DQM1 DS high slew rate slow
+DATA 4 0x73fa84d8 0x000000e4
+#DQM2 DS high slew rate slow
+DATA 4 0x73fa84dc 0x000000e4
+#DQM3 DS high slew rate slow
+DATA 4 0x73fa84e0 0x000000e4
+
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+DATA 4 0x73fa84bc 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+DATA 4 0x73fa84c0 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+DATA 4 0x73fa84c4 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+DATA 4 0x73fa84c8 0x000000c4
+
+#DRAM_DATA B0
+DATA 4 0x73fa88a4 0x00000004
+#DRAM_DATA B1
+DATA 4 0x73fa88ac 0x00000004
+#DRAM_DATA B2
+DATA 4 0x73fa88b8 0x00000004
+#DRAM_DATA B3
+DATA 4 0x73fa882c 0x00000004
+
+#DRAM_DATA B0 slew rate
+DATA 4 0x73fa8878 0x00000000
+#DRAM_DATA B1 slew rate
+DATA 4 0x73fa8880 0x00000000
+#DRAM_DATA B2 slew rate
+DATA 4 0x73fa888c 0x00000000
+#DRAM_DATA B3 slew rate
+DATA 4 0x73fa889c 0x00000000
+
+#######################
+### Configure SDRAM ###
+#######################
+
+# Configure CS0
+#######################
+
+# ESDCTL0: Enable controller
+DATA 4 0x83fd9000 0x83220000
+
+# Init DRAM on CS0
+# ESDSCR: Precharge command
+DATA 4 0x83fd9014 0x04008008
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008010
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008010
+# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DATA 4 0x83fd9014 0x00338018
+# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+DATA 4 0x83fd9014 0x0020801a
+# ESDSCR
+DATA 4 0x83fd9014 0x00008000
+
+# ESDSCR: EMR with full Drive strength
+#DATA 4 0x83fd9014 0x0000801a
+
+# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+DATA 4 0x83fd9000 0xC3220000
+
+# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+#          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+#DATA 4 0x83fd9004 0xC33574AA
+
+#micron mDDR
+# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+#DATA 4 0x83FD9004 0x101564a8
+
+#hynix mDDR
+# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+DATA 4 0x83FD9004 0x704564a8
+
+# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+DATA 4 0x83fd9010 0x000a1700
+
+# Configure CS1
+#######################
+
+# ESDCTL1: Enable controller
+DATA 4 0x83fd9008 0x83220000
+
+# Init DRAM on CS1
+# ESDSCR: Precharge command
+DATA 4 0x83fd9014 0x0400800c
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008014
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008014
+# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DATA 4 0x83fd9014 0x0033801c
+# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+DATA 4 0x83fd9014 0x0020801e
+# ESDSCR
+DATA 4 0x83fd9014 0x00008004
+
+# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+DATA 4 0x83fd9008 0xC3220000
+
+# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+#          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+#DATA 4 0x83fd900c 0xC33574AA
+
+#micron mDDR
+# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+#DATA 4 0x83FD900C 0x101564a8
+
+#hynix mDDR
+# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+DATA 4 0x83FD900C 0x704564a8
+
+# ESDSCR (mDRAM configuration finished)
+DATA 4 0x83FD9014 0x00000004
+
+# ESDSCR - clear "configuration request" bit
+DATA 4 0x83fd9014 0x00000000
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
new file mode 100644
index 0000000..c991ee2
--- /dev/null
+++ b/board/ttcontrol/vision2/vision2.c
@@ -0,0 +1,711 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <mxc_gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+void hw_watchdog_reset(void)
+{
+	int val;
+
+	/* toggle watchdog trigger pin */
+	val = mxc_gpio_get(66);
+	val = val ? 0 : 1;
+	mxc_gpio_set(66, val);
+}
+#endif
+
+static void init_drive_strength(void)
+{
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
+	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+
+	/* Setting pad options */
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+
+u32 get_board_rev(void)
+{
+	system_rev = get_cpu_rev();
+
+	return system_rev;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+#if (CONFIG_NR_DRAM_BANKS > 1)
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+		PHYS_SDRAM_2_SIZE);
+#endif
+#else
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+#endif
+
+	return 0;
+}
+
+static void setup_weim(void)
+{
+	struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
+
+	pweim->csgcr1 = 0x004100b9;
+	pweim->csgcr2 = 0x00000001;
+	pweim->csrcr1 = 0x0a018000;
+	pweim->csrcr2 = 0;
+	pweim->cswcr1 = 0x0704a240;
+}
+
+static void setup_uart(void)
+{
+	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+			 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+	/* console RX on Pin EIM_D25 */
+	mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
+	/* console TX on Pin EIM_D26 */
+	mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
+}
+
+#ifdef CONFIG_MXC_SPI
+void spi_io_init(void)
+{
+	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/*
+	 * SS1 will be used as GPIO because of uninterrupted
+	 * long SPI transmissions (GPIO4_25)
+	 */
+	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
+	mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+}
+
+static void reset_peripherals(int reset)
+{
+	if (reset) {
+
+		/* reset_n is on NANDF_D15 */
+		mxc_gpio_set(89, 0);
+		mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
+
+#ifdef CONFIG_VISION2_HW_1_0
+		/*
+		 * set FEC Configuration lines
+		 * set levels of FEC config lines
+		 */
+		mxc_gpio_set(75, 0);
+		mxc_gpio_set(74, 1);
+		mxc_gpio_set(95, 1);
+		mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
+
+		/* set direction of FEC config lines */
+		mxc_gpio_set(59, 0);
+		mxc_gpio_set(60, 0);
+		mxc_gpio_set(61, 0);
+		mxc_gpio_set(55, 1);
+		mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
+		mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
+
+		/* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
+		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
+		/* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
+		/* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
+		/* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
+		/* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
+		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
+		/* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
+		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
+		/* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
+		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
+#endif
+
+		/*
+		 * activate reset_n pin
+		 * Select mux mode: ALT3 mux port: NAND D15
+		 */
+		mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
+			PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
+	} else {
+		/* set FEC Control lines */
+		mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
+		udelay(500);
+
+#ifdef CONFIG_VISION2_HW_1_0
+		/* FEC RDATA[3] */
+		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+		/* FEC RDATA[2] */
+		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+		/* FEC RDATA[1] */
+		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+		/* FEC RDATA[0] */
+		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+		/* FEC RX_CLK */
+		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+		/* FEC RX_ER */
+		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+		/* FEC COL */
+		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+		mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+#endif
+	}
+}
+
+static void power_init_mx51(void)
+{
+	unsigned int val;
+
+	/* Write needed to Power Gate 2 register */
+	val = pmic_reg_read(REG_POWER_MISC);
+
+	/* enable VCAM with 2.775V to enable read from PMIC */
+	val = VCAMCONFIG | VCAMEN;
+	pmic_reg_write(REG_MODE_1, val);
+
+	/*
+	 * Set switchers in Auto in NORMAL mode & STANDBY mode
+	 * Setup the switcher mode for SW1 & SW2
+	 */
+	val = pmic_reg_read(REG_SW_4);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	pmic_reg_write(REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	val = pmic_reg_read(REG_SW_5);
+	val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+		(SWMODE_MASK << SWMODE3_SHIFT));
+	val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+	pmic_reg_write(REG_SW_5, val);
+
+
+	/* Set VGEN3 to 1.8V, VCAM to 3.0V */
+	val = pmic_reg_read(REG_SETTING_0);
+	val &= ~(VCAM_MASK | VGEN3_MASK);
+	val |= VCAM_3_0;
+	pmic_reg_write(REG_SETTING_0, val);
+
+	/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
+	val = pmic_reg_read(REG_SETTING_1);
+	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+	val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
+	pmic_reg_write(REG_SETTING_1, val);
+
+	/* Configure VGEN3 and VCAM regulators to use external PNP */
+	val = VGEN3CONFIG | VCAMCONFIG;
+	pmic_reg_write(REG_MODE_1, val);
+	udelay(200);
+
+	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+		VVIDEOEN | VAUDIOEN  | VSDEN;
+	pmic_reg_write(REG_MODE_1, val);
+
+	val = pmic_reg_read(REG_POWER_CTL2);
+	val |= WDIRESET;
+	pmic_reg_write(REG_POWER_CTL2, val);
+
+	udelay(2500);
+
+}
+#endif
+
+static void setup_gpios(void)
+{
+	unsigned int i;
+
+	/* CAM_SUP_DISn, GPIO1_7 */
+	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
+
+	/* DAB Display EN, GPIO3_1 */
+	mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
+
+	/* WDOG_TRIGGER, GPIO3_2 */
+	mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
+
+	/* Now we need to trigger the watchdog */
+	WATCHDOG_RESET();
+
+	/* Display2 TxEN, GPIO3_3 */
+	mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
+
+	/* DAB Light EN, GPIO3_4 */
+	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
+
+	/* AUDIO_MUTE, GPIO3_5 */
+	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
+
+	/* SPARE_OUT, GPIO3_6 */
+	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
+	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
+
+	/* BEEPER_EN, GPIO3_26 */
+	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
+
+	/* POWER_OFF, GPIO3_27 */
+	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
+
+	/* FRAM_WE, GPIO3_30 */
+	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
+
+	/* EXPANSION_EN, GPIO4_26 */
+	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
+
+	/*
+	 * Set GPIO1_4 to high and output; it is used to reset
+	 * the system on reboot
+	 */
+	mxc_gpio_set(4, 1);
+	mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(7, 0);
+	mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
+	for (i = 65; i < 71; i++) {
+		mxc_gpio_set(i, 0);
+		mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
+	}
+
+	mxc_gpio_set(94, 0);
+	mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
+
+	/* Set POWER_OFF high */
+	mxc_gpio_set(91, 1);
+	mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(90, 0);
+	mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(122, 0);
+	mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
+
+	mxc_gpio_set(121, 1);
+	mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
+
+	WATCHDOG_RESET();
+}
+
+static void setup_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
+
+	/* FEC RDATA[3] */
+	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+	/* FEC RDATA[2] */
+	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+	/* FEC RDATA[1] */
+	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+	/* FEC RDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+	/* FEC TDATA[3] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
+
+	/* FEC TDATA[2] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
+
+	/* FEC TDATA[1] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
+
+	/* FEC TDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
+
+	/* FEC TX_ER */
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
+
+	/* FEC TX_COL */
+	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+
+	/* FEC RX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+	/* FEC RX_CRS */
+	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+	/* FEC RX_DV */
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+}
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+};
+
+int get_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = mxc_gpio_get(0);
+	else
+		*cd = 0;
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bis)
+{
+	mxc_request_iomux(MX51_PIN_SD1_CMD,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_CLK,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA0,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA1,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA2,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_request_iomux(MX51_PIN_SD1_DATA3,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_GPIO1_0,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+		PAD_CTL_HYS_ENABLE);
+	mxc_request_iomux(MX51_PIN_GPIO1_1,
+		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+		PAD_CTL_HYS_ENABLE);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+
+
+	init_drive_strength();
+
+	/* Setup debug led */
+	mxc_gpio_set(6, 0);
+	mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
+	mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+	/* wait a little while to give the pll time to settle */
+	sdelay(100000);
+
+	setup_weim();
+	setup_uart();
+	setup_fec();
+	setup_gpios();
+
+	spi_io_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
+	board_early_init_f();
+#endif
+	gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2;	/* board id for linux */
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	power_init_mx51();
+
+	reset_peripherals(1);
+	udelay(2000);
+	reset_peripherals(0);
+	udelay(2000);
+
+	/* Early revisions require a second reset */
+#ifdef CONFIG_VISION2_HW_1_0
+	reset_peripherals(1);
+	udelay(2000);
+	reset_peripherals(0);
+	udelay(2000);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 system_rev = get_cpu_rev();
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	puts("Board: TTControl Vision II CPU V");
+
+	switch (system_rev & 0xff) {
+	case CHIP_REV_3_0:
+		puts("3.0 [");
+		break;
+	case CHIP_REV_2_5:
+		puts("2.5 [");
+		break;
+	case CHIP_REV_2_0:
+		puts("2.0 [");
+		break;
+	case CHIP_REV_1_1:
+		puts("1.1 [");
+		break;
+	case CHIP_REV_1_0:
+	default:
+		puts("1.0 [");
+		break;
+	}
+
+	cause = src_regs->srsr;
+	switch (cause) {
+	case 0x0001:
+		puts("POR");
+		break;
+	case 0x0009:
+		puts("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		puts("WDOG");
+		break;
+	default:
+		printf("unknown 0x%x", cause);
+	}
+	puts("]\n");
+
+	return 0;
+}
+