ENGR00328278: Add support for i.MX6DQ/DL arm2 LPDDR2 boards

Add support for i.MX6DQ/DL arm2 LPDDR2 boards.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

4 files changed, 984 insertions, 5 deletions

diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index 9a13ebc..38c674b 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -44,6 +44,185 @@ CSF 0x2000
  *	Address	  absolute address of the register
  *	value	  value to be stored in the register
  */
+#ifdef CONFIG_MX6DQ_LPDDR2
+/* DCD */
+DATA 4 0x020C4018 0x60324
+
+DATA 4 0x020E05a8 0x00003038
+DATA 4 0x020E05b0 0x00003038
+DATA 4 0x020E0524 0x00003038
+DATA 4 0x020E051c 0x00003038
+
+DATA 4 0x020E0518 0x00003038
+DATA 4 0x020E050c 0x00003038
+DATA 4 0x020E05b8 0x00003038
+DATA 4 0x020E05c0 0x00003038
+
+DATA 4 0x020E05ac 0x00000038
+DATA 4 0x020E05b4 0x00000038
+DATA 4 0x020E0528 0x00000038
+DATA 4 0x020E0520 0x00000038
+
+DATA 4 0x020E0514 0x00000038
+DATA 4 0x020E0510 0x00000038
+DATA 4 0x020E05bc 0x00000038
+DATA 4 0x020E05c4 0x00000038
+
+DATA 4 0x020E056c 0x00000038
+DATA 4 0x020E0578 0x00000038
+DATA 4 0x020E0588 0x00000038
+DATA 4 0x020E0594 0x00000038
+
+DATA 4 0x020E057c 0x00000038
+DATA 4 0x020E0590 0x00000038
+DATA 4 0x020E0598 0x00000038
+DATA 4 0x020E058c 0x00000000
+
+DATA 4 0x020E059c 0x00000038
+DATA 4 0x020E05a0 0x00000038
+DATA 4 0x020E0784 0x00000038
+DATA 4 0x020E0788 0x00000038
+
+DATA 4 0x020E0794 0x00000038
+DATA 4 0x020E079c 0x00000038
+DATA 4 0x020E07a0 0x00000038
+DATA 4 0x020E07a4 0x00000038
+
+DATA 4 0x020E07a8 0x00000038
+DATA 4 0x020E0748 0x00000038
+DATA 4 0x020E074c 0x00000038
+DATA 4 0x020E0750 0x00020000
+
+DATA 4 0x020E0758 0x00000000
+DATA 4 0x020E0774 0x00020000
+DATA 4 0x020E078c 0x00000038
+DATA 4 0x020E0798 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b401c 0x00008000
+
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+DATA 4 0x021b0800 0xa1390000
+DATA 4 0x021b4800 0xa1390000
+
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b4890 0x00400000
+
+DATA 4 0x021b48bc 0x00055555
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b482c 0xf3333333
+DATA 4 0x021b4830 0xf3333333
+DATA 4 0x021b4834 0xf3333333
+DATA 4 0x021b4838 0xf3333333
+
+DATA 4 0x021b0848 0x49383b39
+DATA 4 0x021b0850 0x30364738
+DATA 4 0x021b4848 0x3e3c3846
+DATA 4 0x021b4850 0x4c294b35
+
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x0
+
+DATA 4 0x021b0858 0xf00
+DATA 4 0x021b4858 0xf00
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b000c 0x555a61a5
+DATA 4 0x021b0004 0x20036
+DATA 4 0x021b0010 0x160e83
+DATA 4 0x021b0014 0xdd
+DATA 4 0x021b0018 0x8174c
+DATA 4 0x021b002c 0xf9f26d2
+DATA 4 0x021b0030 0x20e
+DATA 4 0x021b0038 0x200aac
+DATA 4 0x021b0008 0x0
+
+DATA 4 0x021b0040 0x5f
+
+DATA 4 0x021b0000 0xc3010000
+
+DATA 4 0x021b400c 0x555a61a5
+DATA 4 0x021b4004 0x20036
+DATA 4 0x021b4010 0x160e83
+DATA 4 0x021b4014 0xdd
+DATA 4 0x021b4018 0x8174c
+DATA 4 0x021b402c 0xf9f26d2
+DATA 4 0x021b4030 0x20e
+DATA 4 0x021b4038 0x200aac
+DATA 4 0x021b4008 0x0
+
+DATA 4 0x021b4040 0x3f
+DATA 4 0x021b4000 0xc3010000
+
+DATA 4 0x021b001c 0x3f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0xc2018030
+DATA 4 0x021b001c 0x6028030
+DATA 4 0x021b001c 0x2038030
+
+DATA 4 0x021b401c 0x3f8030
+DATA 4 0x021b401c 0xff0a8030
+DATA 4 0x021b401c 0xc2018030
+DATA 4 0x021b401c 0x6028030
+DATA 4 0x021b401c 0x2038030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b0020 0x7800
+DATA 4 0x021b4020 0x7800
+
+DATA 4 0x021b0818 0x0
+DATA 4 0x021b4818 0x0
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b001c 0x0
+DATA 4 0x021b401c 0x0
+
+DATA 4 0x021b0404 0x00011006
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#else
 DATA 4 0x020e05a8 0x00000030
 DATA 4 0x020e05b0 0x00000030
 DATA 4 0x020e0524 0x00000030
@@ -156,10 +335,6 @@ DATA 4 0x021b48b8 0x00000800
 DATA 4 0x021b001c 0x00000000
 DATA 4 0x021b0404 0x00011006
 
-DATA 4 0x020e0010 0xF00000FF
-DATA 4 0x020e0018 0x00070007
-DATA 4 0x020e001c 0x00070007
-
 DATA 4 0x020c4068 0x00C03F3F
 DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
@@ -173,4 +348,6 @@ DATA 4 0x020e0010 0xF00000CF
 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
+
+#endif /* CONFIG_MX6DQ_LPDDR2 */
 #endif
diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
index bb9ae4c..0e15da4 100644
--- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg
+++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
@@ -60,6 +60,324 @@ CSF 0x2000
  *	Address	  absolute address of the register
  *	value	  value to be stored in the register
  */
+
+
+
+#ifdef CONFIG_MX6DL_LPDDR2
+
+/* IOMUX SETTINGS */
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
+DATA 4 0x020E04bc 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
+DATA 4 0x020E04c0 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
+DATA 4 0x020E04c4 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
+DATA 4 0x020E04c8 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
+DATA 4 0x020E04cc 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
+DATA 4 0x020E04d0 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
+DATA 4 0x020E04d4 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
+DATA 4 0x020E04d8 0x00003028
+
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+DATA 4 0x020E0470 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+DATA 4 0x020E0474 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
+DATA 4 0x020E0478 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
+DATA 4 0x020E047c 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
+DATA 4 0x020E0480 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
+DATA 4 0x020E0484 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
+DATA 4 0x020E0488 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
+DATA 4 0x020E048c 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+DATA 4 0x020E0464 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+DATA 4 0x020E0490 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
+DATA 4 0x020E04ac 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
+DATA 4 0x020E04b0 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+DATA 4 0x020E0494 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
+DATA 4 0x020E04a4 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
+DATA 4 0x020E04a8 0x00000038
+/*
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+ * DSE can be configured using Group Control Register:
+ * IOMUXC_SW_PAD_CTL_GRP_CTLDS
+ */
+DATA 4 0x020E04a0 0x00000000
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
+DATA 4 0x020E04b4 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
+DATA 4 0x020E04b8 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+DATA 4 0x020E0764 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+DATA 4 0x020E0770 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
+DATA 4 0x020E0778 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
+DATA 4 0x020E077c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
+DATA 4 0x020E0780 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
+DATA 4 0x020E0784 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
+DATA 4 0x020E078c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
+DATA 4 0x020E0748 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+DATA 4 0x020E074c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+DATA 4 0x020E076c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+DATA 4 0x020E0750 0x00020000
+/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+DATA 4 0x020E0754 0x00000000
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+DATA 4 0x020E0760 0x00020000
+/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+DATA 4 0x020E0774 0x00080000
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer:	Mocron
+ * Device Part Number:	MT42L64M64D2KH-18
+ * Clock Freq.: 	528MHz
+ * MMDC channels: Both MMDC0, MMDC1
+ *Density per CS in Gb: 	256M
+ * Chip Selects used:	2
+ * Number of Banks:	8
+ * Row address:    	14
+ * Column address: 	9
+ * Data bus width	32
+ */
+
+/* MMDC_P0_BASE_ADDR = 0x021b0000 */
+/* MMDC_P1_BASE_ADDR = 0x021b4000 */
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+DATA 4 0x021b001c 0x00008000
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+DATA 4 0x021b401c 0x00008000
+
+/*LPDDR2 ZQ params */
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+/* Calibration setup. */
+/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
+DATA 4 0x021b0800 0xa1390003
+
+/*ca bus abs delay */
+DATA 4 0x021b0890 0x00400000
+/*ca bus abs delay */
+DATA 4 0x021b4890 0x00400000
+/* values of 20,40,50,60,7f tried. no difference seen */
+
+/* DDR_PHY_P1_MPWRCADL */
+DATA 4 0x021b48bc 0x00055555
+
+/*frc_msr.*/
+DATA 4 0x021b08b8 0x00000800
+/*frc_msr.*/
+DATA 4 0x021b48b8 0x00000800
+
+/* DDR_PHY_P0_MPREDQBY0DL3 */
+DATA 4 0x021b081c 0x33333333
+/* DDR_PHY_P0_MPREDQBY1DL3 */
+DATA 4 0x021b0820 0x33333333
+/* DDR_PHY_P0_MPREDQBY2DL3 */
+DATA 4 0x021b0824 0x33333333
+/* DDR_PHY_P0_MPREDQBY3DL3 */
+DATA 4 0x021b0828 0x33333333
+/* DDR_PHY_P1_MPREDQBY0DL3 */
+DATA 4 0x021b481c 0x33333333
+/* DDR_PHY_P1_MPREDQBY1DL3 */
+DATA 4 0x021b4820 0x33333333
+/* DDR_PHY_P1_MPREDQBY2DL3 */
+DATA 4 0x021b4824 0x33333333
+/* DDR_PHY_P1_MPREDQBY3DL3 */
+DATA 4 0x021b4828 0x33333333
+
+/*
+ * Read and write data delay, per byte.
+ * For optimized DDR operation it is recommended to run mmdc_calibration
+ * on your board, and replace 4 delay register assigns with resulted values
+ * Note:
+ * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
+ *    should be skipped, or the write/read calibration comming after that
+ *    will stall
+ * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
+ */
+
+DATA 4 0x021b0848 0x4b4b524f
+DATA 4 0x021b4848 0x494f4c44
+
+DATA 4 0x021b0850 0x3c3d303c
+DATA 4 0x021b4850 0x3c343d38
+
+/*dqs gating dis */
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x0
+
+/*clk delay */
+DATA 4 0x021b0858 0xa00
+/*clk delay */
+DATA 4 0x021b4858 0xa00
+
+/*frc_msr */
+DATA 4 0x021b08b8 0x00000800
+/*frc_msr */
+DATA 4 0x021b48b8 0x00000800
+/* Calibration setup end */
+
+/* Channel0 - startng address 0x80000000 */
+/* MMDC0_MDCFG0 */
+DATA 4 0x021b000c 0x34386145
+
+/* MMDC0_MDPDC */
+DATA 4 0x021b0004 0x00020036
+/* MMDC0_MDCFG1 */
+DATA 4 0x021b0010 0x00100c83
+/* MMDC0_MDCFG2 */
+DATA 4 0x021b0014 0x000000Dc
+/* MMDC0_MDMISC */
+DATA 4 0x021b0018 0x0000174C
+/* MMDC0_MDRWD;*/
+DATA 4 0x021b002c 0x0f9f26d2
+/* MMDC0_MDOR */
+DATA 4 0x021b0030 0x0000020e
+/* MMDC0_MDCFG3LP */
+DATA 4 0x021b0038 0x00190778
+/* MMDC0_MDOTC */
+DATA 4 0x021b0008 0x00000000
+
+/* CS0_END */
+DATA 4 0x021b0040 0x0000005f
+/* ROC */
+DATA 4 0x021b0404 0x0000000f
+
+/* MMDC0_MDCTL */
+DATA 4 0x021b0000 0xc3010000
+
+/* Channel1 - starting address 0x10000000 */
+/* MMDC1_MDCFG0 */
+DATA 4 0x021b400c 0x34386145
+
+/* MMDC1_MDPDC */
+DATA 4 0x021b4004 0x00020036
+/* MMDC1_MDCFG1 */
+DATA 4 0x021b4010 0x00100c83
+/* MMDC1_MDCFG2 */
+DATA 4 0x021b4014 0x000000Dc
+/* MMDC1_MDMISC */
+DATA 4 0x021b4018 0x0000174C
+/* MMDC1_MDRWD;*/
+DATA 4 0x021b402c 0x0f9f26d2
+/* MMDC1_MDOR */
+DATA 4 0x021b4030 0x0000020e
+/* MMDC1_MDCFG3LP */
+DATA 4 0x021b4038 0x00190778
+/* MMDC1_MDOTC */
+DATA 4 0x021b4008 0x00000000
+
+/* CS0_END */
+DATA 4 0x021b4040 0x0000003f
+
+/* MMDC1_MDCTL */
+DATA 4 0x021b4000 0xc3010000
+
+/* Channel0 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+DATA 4 0x021b001c 0x003f8030
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+DATA 4 0x021b001c 0xff0a8030
+/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
+DATA 4 0x021b001c 0xa2018030
+/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
+DATA 4 0x021b001c 0x06028030
+/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
+DATA 4 0x021b001c 0x01038030
+
+/* Channel1 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+DATA 4 0x021b401c 0x003f8030
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+DATA 4 0x021b401c 0xff0a8030
+/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
+DATA 4 0x021b401c 0xa2018030
+/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
+DATA 4 0x021b401c 0x06028030
+/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
+DATA 4 0x021b401c 0x01038030
+
+/* MMDC0_MDREF */
+DATA 4 0x021b0020 0x00005800
+/* MMDC1_MDREF */
+DATA 4 0x021b4020 0x00005800
+
+/* DDR_PHY_P0_MPODTCTRL */
+DATA 4 0x021b0818 0x0
+/* DDR_PHY_P1_MPODTCTRL */
+DATA 4 0x021b4818 0x0
+
+/*
+ * calibration values based on calibration compare of 0x00ffff00:
+ * Note, these calibration values are based on Freescale's board
+ * May need to run calibration on target board to fine tune these
+ */
+
+/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
+DATA 4 0x021b0800 0xa1310003
+
+/* DDR_PHY_P0_MPMUR0, frc_msr */
+DATA 4 0x021b08b8 0x00000800
+/* DDR_PHY_P1_MPMUR0, frc_msr */
+DATA 4 0x021b48b8 0x00000800
+
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+DATA 4 0x021b001c 0x00000000
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+DATA 4 0x021b401c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+DATA 4 0x020e0010 0xF00000CF
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#else /* CONFIG_MX6DL_LPDDR2 */
+
 DATA 4 0x020e0798 0x000c0000
 DATA 4 0x020e0758 0x00000000
 DATA 4 0x020e0588 0x00000030
@@ -171,4 +489,5 @@ DATA 4 0x020c4080 0x000003FF
 DATA 4 0x020e0010 0xF00000CF
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
+#endif /* CONFIG_MX6DL_LPDDR2 */
 #endif
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 9ae8aef..6f8c9b2 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -295,7 +295,11 @@ int board_late_init(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_MX6DL
+	puts("Board: MX6DL-Armadillo2\n");
+#else
 	puts("Board: MX6Q-Armadillo2\n");
+#endif
 
 	return 0;
 }
diff --git a/board/freescale/mx6qarm2/plugin.S b/board/freescale/mx6qarm2/plugin.S
index e553d7e..dded80a 100644
--- a/board/freescale/mx6qarm2/plugin.S
+++ b/board/freescale/mx6qarm2/plugin.S
@@ -444,9 +444,488 @@
 	str r2, [r0, #0x01c]
 .endm
 
+.macro imx6dlarm2_lpddr2_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x06c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x070]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x074]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x078]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x07c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x080]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x084]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00003028
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+	str r1, [r0, #0x4cc]
+	str r1, [r0, #0x4d0]
+	str r1, [r0, #0x4d4]
+	str r1, [r0, #0x4d8]
+
+	ldr r1, =0x00000038
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+	str r1, [r0, #0x480]
+	str r1, [r0, #0x484]
+	str r1, [r0, #0x488]
+	str r1, [r0, #0x48c]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x494]
+	str r1, [r0, #0x4a4]
+	str r1, [r0, #0x4a8]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+	ldr r1, =0x00000038
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x780]
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x78c]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x76c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+	ldr r1, =0x00080000
+	str r1, [r0, #0x774]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+	ldr r2, =0x1b5f01ff
+	str r2, [r0, #0x85c]
+	str r2, [r1, #0x85c]
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00400000
+	str r2, [r0, #0x890]
+	str r2, [r1, #0x890]
+	ldr r2, =0x00055555
+	str r2, [r1, #0x8bc]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x4b4b524f
+	str r2, [r0, #0x848]
+	ldr r2, =0x494f4c44
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x3c3d303c
+	str r2, [r0, #0x850]
+	ldr r2, =0x3c343d38
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	str r2, [r1, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x00000a00
+	str r2, [r0, #0x858]
+	str r2, [r1, #0x858]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x34386145
+	str r2, [r0, #0xc]
+	ldr r2, =0x00020036
+	str r2, [r0, #0x4]
+	ldr r2, =0x00100c83
+	str r2, [r0, #0x10]
+	ldr r2, =0x000000Dc
+	str r2, [r0, #0x14]
+	ldr r2, =0x0000174C
+	str r2, [r0, #0x18]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x2c]
+	ldr r2, =0x0000020e
+	str r2, [r0, #0x30]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x38]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x8]
+
+	ldr r2, =0x0000005f
+	str r2, [r0, #0x40]
+	ldr r2, =0x0000000f
+	str r2, [r0, #0x404]
+
+	ldr r2, =0xc3010000
+	str r2, [r0, #0x0]
+
+	ldr r2, =0x34386145
+	str r2, [r1, #0xc]
+
+	ldr r2, =0x00020036
+	str r2, [r1, #0x4]
+	ldr r2, =0x00100c83
+	str r2, [r1, #0x10]
+	ldr r2, =0x000000Dc
+	str r2, [r1, #0x14]
+	ldr r2, =0x0000174C
+	str r2, [r1, #0x18]
+	ldr r2, =0x0f9f26d2
+	str r2, [r1, #0x2c]
+	ldr r2, =0x0000020e
+	str r2, [r1, #0x30]
+	ldr r2, =0x00190778
+	str r2, [r1, #0x38]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x8]
+
+	ldr r2, =0x0000003f
+	str r2, [r1, #0x40]
+
+	ldr r2, =0xc3010000
+	str r2, [r1, #0x0]
+
+	ldr r2, =0x003f8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xff0a8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xa2018030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x06028030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x01038030
+	str r2, [r0, #0x1c]
+
+	ldr r2, =0x003f8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xff0a8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xa2018030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x06028030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x01038030
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x20]
+	str r2, [r1, #0x20]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+
+	ldr r2, =0xa1310003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x1c]
+.endm
+
+.macro imx6dqarm2_lpddr2_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x60324
+	str r1, [r0, #0x18]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x06c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x070]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x074]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x078]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x07c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x080]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x084]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00003038
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00000038
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x57c]
+	str r1, [r0, #0x590]
+	str r1, [r0, #0x598]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+	ldr r1, =0x00000038
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x74c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000038
+	str r1, [r0, #0x78c]
+	ldr r1, =0x00080000
+	str r1, [r0, #0x798]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+	ldr r2, =0x1b5f01ff
+	str r2, [r0, #0x85c]
+	str r2, [r1, #0x85c]
+	ldr r2, =0xa1390000
+	str r2, [r0, #0x800]
+	str r2, [r1, #0x800]
+	ldr r2, =0x00400000
+	str r2, [r0, #0x890]
+	str r2, [r1, #0x890]
+	ldr r2, =0x00055555
+	str r2, [r1, #0x8bc]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0xf3333333
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+	str r2, [r1, #0x82c]
+	str r2, [r1, #0x830]
+	str r2, [r1, #0x834]
+	str r2, [r1, #0x838]
+
+	ldr r2, =0x49383b39
+	str r2, [r0, #0x848]
+	ldr r2, =0x30364738
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x3e3c3846
+	str r2, [r1, #0x848]
+	ldr r2, =0x4c294b35
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	str r2, [r1, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x00000f00
+	str r2, [r0, #0x858]
+	str r2, [r1, #0x858]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x555a61a5
+	str r2, [r0, #0xc]
+	ldr r2, =0x00020036
+	str r2, [r0, #0x4]
+	ldr r2, =0x00160e83
+	str r2, [r0, #0x10]
+	ldr r2, =0x000000dd
+	str r2, [r0, #0x14]
+	ldr r2, =0x0008174C
+	str r2, [r0, #0x18]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x2c]
+	ldr r2, =0x0000020e
+	str r2, [r0, #0x30]
+	ldr r2, =0x200aac
+	str r2, [r0, #0x38]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x8]
+
+	ldr r2, =0x0000005f
+	str r2, [r0, #0x40]
+
+	ldr r2, =0xc3010000
+	str r2, [r0, #0x0]
+
+	ldr r2, =0x555a61a5
+	str r2, [r1, #0xc]
+	ldr r2, =0x00020036
+	str r2, [r1, #0x4]
+	ldr r2, =0x00160e83
+	str r2, [r1, #0x10]
+	ldr r2, =0x000000dd
+	str r2, [r1, #0x14]
+	ldr r2, =0x0008174C
+	str r2, [r1, #0x18]
+	ldr r2, =0x0f9f26d2
+	str r2, [r1, #0x2c]
+	ldr r2, =0x0000020e
+	str r2, [r1, #0x30]
+	ldr r2, =0x00200aac
+	str r2, [r1, #0x38]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x8]
+
+	ldr r2, =0x0000003f
+	str r2, [r1, #0x40]
+
+	ldr r2, =0xc3010000
+	str r2, [r1, #0x0]
+
+	ldr r2, =0x003f8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xff0a8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xc2018030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x06028030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x02038030
+	str r2, [r0, #0x1c]
+
+	ldr r2, =0x003f8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xff0a8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xc2018030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x06028030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x02038030
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	str r2, [r1, #0x800]
+
+	ldr r2, =0x00007800
+	str r2, [r0, #0x20]
+	str r2, [r1, #0x20]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+
+	ldr r2, =0xa1310003
+	str r2, [r0, #0x800]
+	str r2, [r1, #0x800]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x1c]
+.endm
+
 .macro imx6_ddr_setting
-	#if defined (CONFIG_MX6Q)
+	#if defined (CONFIG_MX6DQ_LPDDR2)
+	imx6dqarm2_lpddr2_setting
+	#elif defined (CONFIG_MX6Q)
 	imx6dqarm2_ddr_setting
+	#elif defined (CONFIG_MX6DL_LPDDR2)
+	imx6dlarm2_lpddr2_setting
 	#elif defined (CONFIG_MX6DL)
 	imx6dlarm2_ddr_setting
 	#else