MLK-10134 imx: mx6dqarm2: Add MX6DQ PoP validation board support

The MX6DQ PoP validation board is similar as MX6DQ ARM2 board. So
reuse the ARM2 BSP codes with new DDR script used.

The build target for MX6DQ PoP validation board is:
mx6qarm2_pop_lpddr2_config

Signed-off-by: Ye.Li <B37916@freescale.com>

2 files changed, 402 insertions, 4 deletions

diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index 38c674b..8fba8aa 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
  * Jason Liu <r64343@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -44,7 +44,172 @@ CSF 0x2000
  *	Address	  absolute address of the register
  *	value	  value to be stored in the register
  */
-#ifdef CONFIG_MX6DQ_LPDDR2
+#ifdef CONFIG_MX6DQ_POP_LPDDR2
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* DCD */
+DATA 4 0x020e0798 0x00080000
+DATA 4 0x020e0758 0x00000000
+
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00003030
+DATA 4 0x020e05b0 0x00003030
+DATA 4 0x020e0524 0x00003030
+DATA 4 0x020e051c 0x00003030
+DATA 4 0x020e0518 0x00003030
+DATA 4 0x020e050c 0x00003030
+DATA 4 0x020e05b8 0x00003030
+DATA 4 0x020e05c0 0x00003030
+
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b401c 0x00008000
+
+DATA 4 0x021b085c 0x1B5F0107
+DATA 4 0x021b485c 0x1B5F0107
+
+DATA 4 0x021b0800 0xA1390003
+
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b4890 0x00400000
+
+DATA 4 0x021b0848 0x3C3A3A44
+DATA 4 0x021b4848 0x3C3A3A44
+
+DATA 4 0x021b0850 0x4238423A
+DATA 4 0x021b4850 0x4238423A
+
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x00000000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b482c 0xf3333333
+DATA 4 0x021b4830 0xf3333333
+DATA 4 0x021b4834 0xf3333333
+DATA 4 0x021b4838 0xf3333333
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b000c 0x444961A5
+DATA 4 0x021b0010 0x00160E83
+DATA 4 0x021b0014 0x000000DD
+
+DATA 4 0x021b0018 0x0000174C
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x149F26D2
+DATA 4 0x021b0030 0x00000010
+DATA 4 0x021b0038 0x0021099B
+DATA 4 0x021b0040 0x0000004F
+DATA 4 0x021b0400 0x11420000
+DATA 4 0x021b0000 0x83110000
+
+DATA 4 0x021b4004 0x00020036
+DATA 4 0x021b4008 0x00000000
+DATA 4 0x021b400c 0x444961A5
+DATA 4 0x021b4010 0x00160E83
+DATA 4 0x021b4014 0x000000DD
+
+DATA 4 0x021b4018 0x0000174C
+DATA 4 0x021b401c 0x00008000
+DATA 4 0x021b402c 0x149F26D2
+DATA 4 0x021b4030 0x00000010
+DATA 4 0x021b4038 0x0021099B
+DATA 4 0x021b4040 0x00000017
+DATA 4 0x021b4400 0x11420000
+DATA 4 0x021b4000 0x83110000
+
+DATA 4 0x021b001c 0x003F8030
+DATA 4 0x021b001c 0xFF0A8030
+DATA 4 0x021b001c 0xC2018030
+DATA 4 0x021b001c 0x06028030
+DATA 4 0x021b001c 0x02038030
+
+DATA 4 0x021b401c 0x003F8030
+DATA 4 0x021b401c 0xFF0A8030
+DATA 4 0x021b401c 0xC2018030
+DATA 4 0x021b401c 0x06028030
+DATA 4 0x021b401c 0x02038030
+
+DATA 4 0x021b0800 0xA1390003
+
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b4020 0x00001800
+
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b4818 0x00000000
+
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b4004 0x00025576
+
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b4404 0x00011006
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b401c 0x00000000
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+#elif defined(CONFIG_MX6DQ_LPDDR2)
 /* DCD */
 DATA 4 0x020C4018 0x60324
 
diff --git a/board/freescale/mx6qarm2/plugin.S b/board/freescale/mx6qarm2/plugin.S
index dded80a..82b4c81 100644
--- a/board/freescale/mx6qarm2/plugin.S
+++ b/board/freescale/mx6qarm2/plugin.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
@@ -919,8 +919,241 @@
 	str r1, [r0, #0x1c]
 .endm
 
+.macro imx6dq_pop_arm2_lpddr2_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x06c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x070]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x074]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x078]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x07c]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x080]
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x084]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+	str r1, [r0, #0x58c]
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+	ldr r2, =0x1B5F0107
+	str r2, [r0, #0x85c]
+	str r2, [r1, #0x85c]
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00400000
+	str r2, [r0, #0x890]
+	str r2, [r1, #0x890]
+	ldr r2, =0x3C3A3A44
+	str r2, [r0, #0x848]
+	str r2, [r1, #0x848]
+	ldr r2, =0x4238423A
+	str r2, [r0, #0x850]
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	ldr r2, =0x20000000
+	str r2, [r1, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0xf3333333
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+	str r2, [r1, #0x82c]
+	str r2, [r1, #0x830]
+	str r2, [r1, #0x834]
+	str r2, [r1, #0x838]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x8]
+	ldr r2, =0x444961A5
+	str r2, [r0, #0xc]
+	ldr r2, =0x00160E83
+	str r2, [r0, #0x10]
+	ldr r2, =0x000000DD
+	str r2, [r0, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r0, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	ldr r2, =0x149F26D2
+	str r2, [r0, #0x2c]
+	ldr r2, =0x00000010
+	str r2, [r0, #0x30]
+	ldr r2, =0x0021099B
+	str r2, [r0, #0x38]
+	ldr r2, =0x0000004F
+	str r2, [r0, #0x40]
+	ldr r2, =0x11420000
+	str r2, [r0, #0x400]
+	ldr r2, =0x83110000
+	str r2, [r0, #0x0]
+
+	ldr r2, =0x00020036
+	str r2, [r1, #0x4]
+	ldr r2, =0x00000000
+	str r2, [r1, #0x8]
+	ldr r2, =0x444961A5
+	str r2, [r1, #0xc]
+	ldr r2, =0x00160E83
+	str r2, [r1, #0x10]
+	ldr r2, =0x000000DD
+	str r2, [r1, #0x14]
+
+	ldr r2, =0x0000174C
+	str r2, [r1, #0x18]
+	ldr r2, =0x00008000
+	str r2, [r1, #0x1c]
+	ldr r2, =0x149F26D2
+	str r2, [r1, #0x2c]
+	ldr r2, =0x00000010
+	str r2, [r1, #0x30]
+	ldr r2, =0x0021099B
+	str r2, [r1, #0x38]
+	ldr r2, =0x00000017
+	str r2, [r1, #0x40]
+	ldr r2, =0x11420000
+	str r2, [r1, #0x400]
+	ldr r2, =0x83110000
+	str r2, [r1, #0x0]
+
+	ldr r2, =0x003F8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r0, #0x1c]
+	ldr r2, =0xC2018030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x06028030
+	str r2, [r0, #0x1c]
+	ldr r2, =0x02038030
+	str r2, [r0, #0x1c]
+
+	ldr r2, =0x003F8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xFF0A8030
+	str r2, [r1, #0x1c]
+	ldr r2, =0xC2018030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x06028030
+	str r2, [r1, #0x1c]
+	ldr r2, =0x02038030
+	str r2, [r1, #0x1c]
+
+	ldr r2, =0xA1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x20]
+	str r2, [r1, #0x20]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+
+	ldr r2, =0x00025576
+	str r2, [r0, #0x4]
+	str r2, [r1, #0x4]
+
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	str r2, [r1, #0x404]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x1c]
+	str r2, [r1, #0x1c]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x1c]
+.endm
+
 .macro imx6_ddr_setting
-	#if defined (CONFIG_MX6DQ_LPDDR2)
+	#if defined (CONFIG_MX6DQ_POP_LPDDR2)
+        imx6dq_pop_arm2_lpddr2_setting
+	#elif defined (CONFIG_MX6DQ_LPDDR2)
 	imx6dqarm2_lpddr2_setting
 	#elif defined (CONFIG_MX6Q)
 	imx6dqarm2_ddr_setting