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authorValentin Longchamp <valentin.longchamp@keymile.com>2014-01-27 11:49:07 +0100
committerYork Sun <yorksun@freescale.com>2014-02-03 08:38:50 -0800
commitfabb9297fa6bf88f44c36225c57b7779fc51f737 (patch)
treee6fc83104b16f3a4f19bde1bd2bd77996e9fb830 /board
parentf3e74d0a9fd8cdcbdc59b7c5a702aacc51908dca (diff)
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kmp204x: implement workaround for A-006559
According to the errata, some bits of an undocumented register in the DCSR must be set for every core in order to avoid a possible data or instruction corruption. This is required for the 2.0 revision of the P2041 that should be used as soon as available in our design. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/keymile/kmp204x/pbi.cfg10
1 files changed, 10 insertions, 0 deletions
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
index f38dcf9..9af8bd5 100644
--- a/board/keymile/kmp204x/pbi.cfg
+++ b/board/keymile/kmp204x/pbi.cfg
@@ -8,6 +8,16 @@
#
#PBI commands
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+#Freescale's errarta sheet suggests it may be done with PBI
+09000010 00000000
+09000014 00000000
+09000018 81d00000
+09021008 0000f000
+09021028 0000f000
+09021048 0000f000
+09021068 0000f000
+09000018 00000000
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000