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authorWolfgang Denk <wd@denx.de>2008-07-13 14:44:12 +0200
committerWolfgang Denk <wd@denx.de>2008-07-13 14:44:12 +0200
commitc90d115913a921c7548ad6eaaa0e13d4f484334c (patch)
tree324cbb51ec8d0e8047bbce13d5f9900da2db1cbe /board
parentdc42c7c08000f97651b763ab5b614e5f74c443ee (diff)
parent0740ac26f4e590bf5b4e7b9a9886208dc2dacb32 (diff)
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Merge branch 'master' of /home/wd/git/u-boot/custodians
Diffstat (limited to 'board')
-rw-r--r--board/BuS/EB+MCF-EV123/mii.c2
-rw-r--r--board/cobra5272/mii.c2
-rw-r--r--board/freescale/m5235evb/m5235evb.c3
3 files changed, 5 insertions, 2 deletions
diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c
index 3ea20a6..8ae2ec6 100644
--- a/board/BuS/EB+MCF-EV123/mii.c
+++ b/board/BuS/EB+MCF-EV123/mii.c
@@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c
index d0a4a39..b30ba80 100644
--- a/board/cobra5272/mii.c
+++ b/board/cobra5272/mii.c
@@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index c2c8fe8..bd8a4e5 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
sdram->dacr0 =
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+ asm("nop");
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+ asm("nop");
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
@@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+ asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;