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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-01-13 21:06:16 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-01-14 08:23:43 +0100
commitaf5b9b1f789d600cf0d996f1a5e80eb8b38f4264 (patch)
treed2ae3ae399676b59864bf3f58bfa69d7036c04c5 /board
parent4efd69250f6118ebd783867b3809001a1886ce9e (diff)
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mini2440: remove board support
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board')
-rw-r--r--board/friendlyarm/mini2440/Makefile8
-rw-r--r--board/friendlyarm/mini2440/mini2440.c118
-rw-r--r--board/friendlyarm/mini2440/mini2440.h144
3 files changed, 0 insertions, 270 deletions
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
deleted file mode 100644
index f367107..0000000
--- a/board/friendlyarm/mini2440/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2012
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mini2440.o
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
deleted file mode 100644
index 59ed054..0000000
--- a/board/friendlyarm/mini2440/mini2440.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2009
- * Michel Pollet <buserror@gmail.com>
- *
- * (C) Copyright 2012
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/s3c2440.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <netdev.h>
-#include "mini2440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline void pll_delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-int board_early_init_f(void)
-{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
-
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
- clk_power->clkdivn = CLKDIVN_VAL;
-
- /* configure UPLL */
- clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
- /* some delay between MPLL and UPLL */
- pll_delay(100);
-
- /* configure MPLL */
- clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
-
- /* some delay between MPLL and UPLL */
- pll_delay(10000);
-
- return 0;
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- /* IOMUX Port H : UART Configuration */
- gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
- IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
-
- gpio_direction_output(GPH8, 0);
- gpio_direction_output(GPH9, 0);
- gpio_direction_output(GPH10, 0);
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
-
- return 0;
-}
-
-int dram_init(void)
-{
- struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
-
- /*
- * Configuring bus width and timing
- * Initialize clocks for each bank 0..5
- * Bank 3 and 4 are used for DM9000
- */
- writel(BANK_CONF, &memctl->bwscon);
- writel(B0_CONF, &memctl->bankcon[0]);
- writel(B1_CONF, &memctl->bankcon[1]);
- writel(B2_CONF, &memctl->bankcon[2]);
- writel(B3_CONF, &memctl->bankcon[3]);
- writel(B4_CONF, &memctl->bankcon[4]);
- writel(B5_CONF, &memctl->bankcon[5]);
-
- /* Bank 6 and 7 are used for DRAM */
- writel(SDRAM_64MB, &memctl->bankcon[6]);
- writel(SDRAM_64MB, &memctl->bankcon[7]);
-
- writel(MEM_TIMING, &memctl->refresh);
- writel(BANKSIZE_CONF, &memctl->banksize);
- writel(B6_MRSR, &memctl->mrsrb6);
- writel(B7_MRSR, &memctl->mrsrb7);
-
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_DRIVER_DM9000
- return dm9000_initialize(bis);
-#else
- return 0;
-#endif
-}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
deleted file mode 100644
index db386ea..0000000
--- a/board/friendlyarm/mini2440/mini2440.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __MINI2440_BOARD_CONF_H__
-#define __MINI2440_BOARD_CONF_H__
-
-/* PLL Parameters */
-#define CLKDIVN_VAL 7
-#define M_MDIV 0x7f
-#define M_PDIV 0x2
-#define M_SDIV 0x1
-
-#define U_M_MDIV 0x38
-#define U_M_PDIV 0x2
-#define U_M_SDIV 0x2
-
-/* BWSCON */
-#define DW8 0x0
-#define DW16 0x1
-#define DW32 0x2
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-#define B1_BWSCON (DW32)
-#define B2_BWSCON (DW16)
-#define B3_BWSCON (DW16 + WAIT + UBLB)
-#define B4_BWSCON (DW16 + WAIT + UBLB)
-#define B5_BWSCON (DW16)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/*
- * Bank Configuration
- */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x0 /* 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0 /* 0clk */
-#define B0_PMC 0x0 /* normal */
-
-#define B1_Tacs 0x0
-#define B1_Tcos 0x0
-#define B1_Tacc 0x7
-#define B1_Tcoh 0x0
-#define B1_Tah 0x0
-#define B1_Tacp 0x0
-#define B1_PMC 0x0
-
-#define B2_Tacs 0x0
-#define B2_Tcos 0x0
-#define B2_Tacc 0x7
-#define B2_Tcoh 0x0
-#define B2_Tah 0x0
-#define B2_Tacp 0x0
-#define B2_PMC 0x0
-
-#define B3_Tacs 0x0
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7
-#define B3_Tcoh 0x1 /* 1clk */
-#define B3_Tah 0x3 /* 4clk */
-#define B3_Tacp 0x0
-#define B3_PMC 0x0
-
-#define B4_Tacs 0x0
-#define B4_Tcos 0x3
-#define B4_Tacc 0x7
-#define B4_Tcoh 0x1
-#define B4_Tah 0x3
-#define B4_Tacp 0x0
-#define B4_PMC 0x0
-
-#define B5_Tacs 0x0
-#define B5_Tcos 0x0
-#define B5_Tacc 0x7
-#define B5_Tcoh 0x0
-#define B5_Tah 0x0
-#define B5_Tacp 0x0
-#define B5_PMC 0x0
-
-/*
- * SDRAM Configuration
- */
-#define SDRAM_MT 0x3 /* SDRAM */
-#define SDRAM_Trcd 0x0 /* 2clk */
-#define SDRAM_SCAN_9 0x1 /* 9bit */
-#define SDRAM_SCAN_10 0x2 /* 10bit */
-
-#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
-
-/*
- * Refresh Parameter
- */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x1 /* 3clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x0 /* unused */
-#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
-
-/*
- * MRSR Parameter
- */
-#define BL 0x0
-#define BT 0x0
-#define CL 0x3 /* 3 clocks */
-#define TM 0x0
-#define WBL 0x0
-
-/*
- * BankSize Parameter
- */
-#define BK76MAP 0x2 /* 128MB/128MB */
-#define SCLK_EN 0x1 /* SCLK active */
-#define SCKE_EN 0x1 /* SDRAM power down mode enable */
-#define BURST_EN 0x1 /* Burst enable */
-
-/*
- * Register values
- */
-#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
- (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
- (B7_BWSCON<<28)))
-
-#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
- (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
-#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
- (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
-#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
- (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
-#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
- (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
-#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
- (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
-#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
- (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
-
-#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
- (Trc<<18) + (Tchr<<16) + REFCNT
-
-#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
-#define B6_MRSR (CL<<4)
-#define B7_MRSR (CL<<4)
-
-#endif