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authorTom Rini <trini@ti.com>2014-01-10 10:56:00 -0500
committerTom Rini <trini@ti.com>2014-01-10 10:56:00 -0500
commit7f673c99c2d8d1aa21996c5b914f06d784b080ca (patch)
treedf68108a0bd7326dc6299b96853b769220c55470 /board
parent8401bfa91ef57e331e2a3abdf768d41803bec88e (diff)
parent10a147bc665367111920be657409a5d56d3c0590 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board')
-rw-r--r--board/armltd/vexpress64/Makefile8
-rw-r--r--board/armltd/vexpress64/vexpress64.c56
-rw-r--r--board/atmel/at91sam9x5ek/at91sam9x5ek.c1
-rw-r--r--board/avionic-design/common/pinmux-config-tamonten-ng.h385
-rw-r--r--board/avionic-design/common/tamonten-ng.c85
-rw-r--r--board/avionic-design/dts/tegra30-tamonten.dtsi69
-rw-r--r--board/avionic-design/dts/tegra30-tec-ng.dts18
-rw-r--r--board/avionic-design/tec-ng/Makefile12
-rw-r--r--board/barco/titanium/Makefile (renamed from board/freescale/titanium/Makefile)0
-rw-r--r--board/barco/titanium/imximage.cfg (renamed from board/freescale/titanium/imximage.cfg)0
-rw-r--r--board/barco/titanium/titanium.c (renamed from board/freescale/titanium/titanium.c)110
-rw-r--r--board/boundary/nitrogen6x/nitrogen6x.c197
-rw-r--r--board/compulab/cm_t335/spl.c10
-rw-r--r--board/compulab/cm_t35/cm_t35.c18
-rw-r--r--board/congatec/cgtqmx6eval/cgtqmx6eval.c40
-rw-r--r--board/denx/m53evk/m53evk.c73
-rw-r--r--board/freescale/mx25pdk/mx25pdk.c2
-rw-r--r--board/freescale/mx31pdk/mx31pdk.c2
-rw-r--r--board/freescale/mx35pdk/mx35pdk.c2
-rw-r--r--board/freescale/mx51evk/mx51evk.c2
-rw-r--r--board/freescale/mx53evk/mx53evk.c2
-rw-r--r--board/freescale/mx53loco/mx53loco.c2
-rw-r--r--board/freescale/mx6qarm2/mx6qarm2.c68
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c62
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c155
-rw-r--r--board/genesi/mx51_efikamx/efikamx.c2
-rw-r--r--board/icpdas/lp8x4x/lp8x4x.c53
-rw-r--r--board/isee/igep0033/board.c10
-rw-r--r--board/logicpd/am3517evm/am3517evm.c32
-rw-r--r--board/logicpd/am3517evm/am3517evm.h2
-rw-r--r--board/logicpd/zoom2/Makefile11
-rw-r--r--board/logicpd/zoom2/config.mk17
-rw-r--r--board/logicpd/zoom2/debug_board.c44
-rw-r--r--board/logicpd/zoom2/led.c116
-rw-r--r--board/logicpd/zoom2/zoom2.c183
-rw-r--r--board/logicpd/zoom2/zoom2.h142
-rw-r--r--board/logicpd/zoom2/zoom2_serial.c130
-rw-r--r--board/logicpd/zoom2/zoom2_serial.h59
-rw-r--r--board/phytec/pcm051/board.c20
-rw-r--r--board/renesas/koelsch/koelsch.c83
-rw-r--r--board/renesas/lager/lager.c78
-rw-r--r--board/samsung/common/Makefile4
-rw-r--r--board/samsung/common/board.c411
-rw-r--r--board/samsung/dts/exynos5420-smdk5420.dts169
-rw-r--r--board/samsung/smdk5250/exynos5-dt.c350
-rw-r--r--board/samsung/smdk5250/smdk5250.c182
-rw-r--r--board/samsung/smdk5420/Makefile11
-rw-r--r--board/samsung/smdk5420/smdk5420.c159
-rw-r--r--board/samsung/smdk5420/smdk5420_spl.c52
-rw-r--r--board/samsung/trats/trats.c2
-rw-r--r--board/samsung/trats2/trats2.c6
-rw-r--r--board/siemens/common/board.c9
-rw-r--r--board/siemens/dxr2/board.c12
-rw-r--r--board/siemens/pxm2/board.c10
-rw-r--r--board/siemens/rut/board.c10
-rw-r--r--board/technexion/tao3530/Makefile5
-rw-r--r--board/technexion/tao3530/tao3530.c215
-rw-r--r--board/technexion/tao3530/tao3530.h371
-rw-r--r--board/ti/am335x/board.c40
-rw-r--r--board/ti/am43xx/board.c355
-rw-r--r--board/ti/am43xx/board.h36
-rw-r--r--board/ti/am43xx/mux.c35
-rw-r--r--board/ti/dra7xx/evm.c8
-rw-r--r--board/ti/ti814x/evm.c4
-rw-r--r--board/ti/ti816x/evm.c12
-rw-r--r--board/udoo/1066mhz_4x256mx16.cfg55
-rw-r--r--board/udoo/clocks.cfg32
-rw-r--r--board/udoo/ddr-setup.cfg87
-rw-r--r--board/udoo/udoo.c165
-rw-r--r--board/udoo/udoo.cfg29
-rw-r--r--board/wandboard/wandboard.c60
-rw-r--r--board/xilinx/dts/zynq-microzed.dts14
-rw-r--r--board/xilinx/dts/zynq-zc702.dts14
-rw-r--r--board/xilinx/dts/zynq-zc706.dts14
-rw-r--r--board/xilinx/dts/zynq-zc770-xm010.dts14
-rw-r--r--board/xilinx/dts/zynq-zc770-xm012.dts14
-rw-r--r--board/xilinx/dts/zynq-zc770-xm013.dts14
-rw-r--r--board/xilinx/dts/zynq-zed.dts14
-rw-r--r--board/xilinx/zynq/board.c25
79 files changed, 3725 insertions, 1655 deletions
diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
new file mode 100644
index 0000000..e009141
--- /dev/null
+++ b/board/armltd/vexpress64/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vexpress64.o
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
new file mode 100644
index 0000000..2ec3bc9
--- /dev/null
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * Clear spin table so that secondary processors
+ * observe the correct value after waken up from wfe.
+ */
+ *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 6f67c34..17a2a40 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -271,7 +271,6 @@ int board_init(void)
#endif
#ifdef CONFIG_ATMEL_SPI
- at91_spi0_hw_init(1 << 0);
at91_spi0_hw_init(1 << 4);
#endif
diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644
index 0000000..39df731
--- /dev/null
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PGRP_LPMD_##_lpmd, \
+ .schmt = PGRP_SCHMT_##_schmt, \
+ .hsm = PGRP_HSM_##_hsm, \
+ }
+
+static struct pingroup_config tamonten_ng_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* UART1 */
+ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+
+ /* UART2 */
+ DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+
+ /* UART3 */
+ DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* UART4 */
+ DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+
+ /* DAP */
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+ /* I2S1 */
+ DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+ /* SPDIF */
+ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+ /* I2S2 */
+ DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+
+ /* DAP4 */
+ DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* Tamonten GPIO */
+ DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* LCD */
+ DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+
+ /* BT656 */
+ LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* GPIOs */
+ DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* LCD BL */
+ DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ /* SPI4 */
+ DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+
+ /* Video input GPIO */
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Sensor GPIO */
+ DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* JTAG */
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* Power controls */
+ DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SPI1 */
+ DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+
+ /* PMU */
+ DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
+
+ /* PCI */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+
+ /* HDMI */
+ DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+ /* UART1 - NC */
+ DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+
+ /* UART2 - NC */
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+
+ /* DAP - NC */
+ DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* DAP4 - NC */
+ DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* Tamonten GPIO - NC */
+ DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+
+ /* BT656 - NC */
+ LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* GPIO - NC */
+ DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Video input - NC */
+ DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* KBC keys - NC */
+ DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+
+ /* PMU - NC */
+ DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Power rails GPIO - NC */
+ DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Others - NC */
+ DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct padctrl_config tamonten_ng_padctrl[] = {
+ /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
new file mode 100644
index 0000000..9d395c6
--- /dev/null
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-tamonten-ng.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS 0x2D
+
+#define PMU_REG_LDO5 0x32
+
+#define PMU_REG_LDO_HIGH_POWER 1
+
+/* Voltage selection for the LDOs with 100mV resolution */
+#define PMU_REG_LDO_SEL_100(mV) ((((mV - 1000) / 100) + 2) << 2)
+
+#define PMU_REG_LDO_100(st, mV) (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV))
+
+#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV)
+
+void pinmux_init(void)
+{
+ pinmux_config_table(tamonten_ng_pinmux_common,
+ ARRAY_SIZE(tamonten_ng_pinmux_common));
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ padgrp_config_table(tamonten_ng_padctrl,
+ ARRAY_SIZE(tamonten_ng_padctrl));
+}
+
+void gpio_early_init(void)
+{
+ /* Turn on the alive signal */
+ gpio_request(GPIO_PV2, "ALIVE");
+ gpio_direction_output(GPIO_PV2, 1);
+
+ /* Remove the reset on the external periph */
+ gpio_request(GPIO_PI4, "nRST_PERIPH");
+ gpio_direction_output(GPIO_PI4, 1);
+}
+
+void pmu_write(uchar reg, uchar data)
+{
+ i2c_set_bus_num(4); /* PMU is on bus 4 */
+ i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
+}
+
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+ /* Enable LDO5 with 3.3v for SDMMC3 */
+ pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
+
+ /* Switch the power on */
+ gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
+ gpio_direction_output(GPIO_PJ2, 1);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /*
+ * NOTE: We don't do mmc-specific pin muxes here.
+ * They were done globally in pinmux_init().
+ */
+
+ /* Bring up the SDIO1 power rail */
+ board_sdmmc_voltage_init();
+}
diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/board/avionic-design/dts/tegra30-tamonten.dtsi
new file mode 100644
index 0000000..50d5762
--- /dev/null
+++ b/board/avionic-design/dts/tegra30-tamonten.dtsi
@@ -0,0 +1,69 @@
+#include "tegra30.dtsi"
+
+/ {
+ model = "Avionic Design Tamonten NG";
+ compatible = "ad,tamonten-ng", "nvidia,tegra30";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ aliases {
+ i2c0 = "/i2c@7000c000";
+ i2c1 = "/i2c@7000c700";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000d000";
+ sdhci0 = "/sdhci@78000600";
+ sdhci1 = "/sdhci@78000400";
+ sdhci2 = "/sdhci@78000000";
+ usb0 = "/usb@7d008000";
+ };
+
+ /* GEN1 */
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ /* GEN2 */
+ i2c@7000c400 {
+ clock-frequency = <100000>;
+ };
+
+ /* CAM */
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ /* DDC */
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ /* PWR */
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ /* SD slot on the base board */
+ sdhci@78000400 {
+ cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+ wp-gpios = <&gpio 67 0>; /* gpio PI3 */
+ bus-width = <4>;
+ };
+
+ /* EMMC on the COM module */
+ sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ usb@7d008000 {
+ status = "okay";
+ };
+
+};
diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/board/avionic-design/dts/tegra30-tec-ng.dts
new file mode 100644
index 0000000..8a69e81
--- /dev/null
+++ b/board/avionic-design/dts/tegra30-tec-ng.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "tegra30-tamonten.dtsi"
+
+/ {
+ model = "Avionic Design Tamontenâ„¢ NG Evaluation Carrier";
+ compatible = "ad,tec-ng", "nvidia,tegra30";
+
+ /* GEN2 */
+ i2c@7000c400 {
+ status = "okay";
+ };
+
+ /* SD card slot */
+ sdhci@78000400 {
+ status = "okay";
+ };
+};
diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
new file mode 100644
index 0000000..f41eb30
--- /dev/null
+++ b/board/avionic-design/tec-ng/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2013
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
+
+obj-y := ../common/tamonten-ng.o
+
+include ../../nvidia/common/common.mk
diff --git a/board/freescale/titanium/Makefile b/board/barco/titanium/Makefile
index 0ad4cb9..0ad4cb9 100644
--- a/board/freescale/titanium/Makefile
+++ b/board/barco/titanium/Makefile
diff --git a/board/freescale/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg
index 7219256..7219256 100644
--- a/board/freescale/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
diff --git a/board/freescale/titanium/titanium.c b/board/barco/titanium/titanium.c
index 6025eb7..6db4488 100644
--- a/board/freescale/titanium/titanium.c
+++ b/board/barco/titanium/titanium.c
@@ -9,7 +9,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
@@ -45,18 +45,18 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
- MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -64,12 +64,12 @@ iomux_v3_cfg_t const uart4_pads[] = {
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
@@ -77,81 +77,81 @@ struct i2c_pads_info i2c_pad_info0 = {
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
- MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
- MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
- MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
- MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
- MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
- MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
iomux_v3_cfg_t nfc_pads[] = {
- MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_gpmi_nand(void)
@@ -272,7 +272,7 @@ int board_eth_init(bd_t *bis)
if (ret)
printf("FEC MXC: %s:failed\n", __func__);
- return 0;
+ return ret;
}
int board_early_init_f(void)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 53cb8df..3f4cfa1 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -17,6 +17,7 @@
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
@@ -71,13 +72,13 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -86,12 +87,12 @@ iomux_v3_cfg_t const uart2_pads[] = {
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
@@ -100,12 +101,12 @@ struct i2c_pads_info i2c_pad_info0 = {
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
@@ -114,87 +115,87 @@ struct i2c_pads_info i2c_pad_info1 = {
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
- MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
- MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
- MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
- MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
- MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
- MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const misc_pads[] = {
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
/* OTG Power enable */
- MX6_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(OUTPUT_40OHM),
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
};
/* wl1271 pads on nitrogen6x */
iomux_v3_cfg_t const wl12xx_pads[] = {
- (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
+ (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(WEAK_PULLDOWN),
- (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
+ (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(OUTPUT_40OHM),
- (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
+ (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
@@ -204,17 +205,17 @@ iomux_v3_cfg_t const wl12xx_pads[] = {
/* Button assignments for J14 */
static iomux_v3_cfg_t const button_pads[] = {
/* Menu */
- MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Back */
- MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Labelled Search (mapped to Power under Android) */
- MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Home */
- MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Down */
- MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Up */
- MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
};
static void setup_iomux_enet(void)
@@ -238,7 +239,7 @@ static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
@@ -330,7 +331,7 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
@@ -401,74 +402,48 @@ static void setup_buttons(void)
ARRAY_SIZE(button_pads));
}
-#ifdef CONFIG_CMD_SATA
-
-int setup_sata(void)
-{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
- int ret = enable_sata_clock();
- if (ret)
- return ret;
-
- clrsetbits_le32(&iomuxc_regs->gpr[13],
- IOMUXC_GPR13_SATA_MASK,
- IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
- |IOMUXC_GPR13_SATA_PHY_7_SATA2M
- |IOMUXC_GPR13_SATA_SPEED_3G
- |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
- |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
- |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
- |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
- |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
- |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
- MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
- MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
- MX6_PAD_DI0_PIN4__GPIO_4_20,
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DI0_PIN4__GPIO4_IO20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
};
struct display_info_t {
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
index 99f3a86..b3b150a 100644
--- a/board/compulab/cm_t335/spl.c
+++ b/board/compulab/cm_t335/spl.c
@@ -20,6 +20,14 @@
#include <asm/arch/hardware_am33xx.h>
#include <asm/sizes.h>
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+};
+
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = MT41J128MJT125_WR_DQS,
@@ -89,7 +97,7 @@ static void probe_sdram_size(long size)
reset_cpu(0);
}
debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
- config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(303, &ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index bc8e0ca..00bcf41 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -105,6 +105,22 @@ static inline int splash_load_from_nand(void)
}
#endif /* CONFIG_CMD_NAND */
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
int splash_screen_prepare(void)
{
char *env_splashimage_value;
@@ -440,7 +456,7 @@ void set_muxconf_regs(void)
cm_t3730_set_muxconf();
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 1ea68f4..7492534 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -35,32 +35,32 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
static void setup_iomux_uart(void)
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
index 3275170..0f71a16 100644
--- a/board/denx/m53evk/m53evk.c
+++ b/board/denx/m53evk/m53evk.c
@@ -13,6 +13,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
+#include <asm/imx-common/mx5_video.h>
#include <asm/arch/spl.h>
#include <asm/errno.h>
#include <netdev.h>
@@ -22,6 +23,11 @@
#include <fsl_esdhc.h>
#include <asm/gpio.h>
#include <usb/ehci-fsl.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+/* Special MXCFB sync flags are here. */
+#include "../drivers/video/mxcfb.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -166,6 +172,32 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_VIDEO
+static struct fb_videomode const ampire_wvga = {
+ .name = "Ampire",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29851, /* picosecond (33.5 MHz) */
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+};
+
+int board_video_skip(void)
+{
+ int ret;
+ ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
+ if (ret)
+ printf("Ampire LCD cannot be configured: %d\n", ret);
+ return ret;
+}
+#endif
+
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
@@ -179,6 +211,46 @@ static void setup_iomux_i2c(void)
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
+static void setup_iomux_video(void)
+{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
+ MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
+ MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
+ MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
+ MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
+ MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
+ MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
+ MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
+ MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
+ MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
+ MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
+ MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
+ MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
+ MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
+ MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
+ MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
+ MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
+ MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
+ MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
+ MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
+ MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
+ MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
+ MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
+ MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
+ MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
+ MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
+ MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
+ MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
+ MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
+ MX53_PAD_EIM_A25__IPU_DI1_PIN12,
+ MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
static void setup_iomux_nand(void)
{
static const iomux_v3_cfg_t nand_pads[] = {
@@ -269,6 +341,7 @@ int board_early_init_f(void)
setup_iomux_fec();
setup_iomux_i2c();
setup_iomux_nand();
+ setup_iomux_video();
m53_set_clock();
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index ebe3bcb..71a395c 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -138,7 +138,7 @@ int board_late_init(void)
mx25pdk_fec_init();
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(I2C_0);
if (ret)
return ret;
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 148b4f4..13b9d51 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -85,7 +85,7 @@ int board_late_init(void)
struct pmic *p;
int ret;
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return ret;
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index 9fabef5..12467a9 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -213,7 +213,7 @@ int board_late_init(void)
struct pmic *p;
int ret;
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(I2C_0);
if (ret)
return ret;
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index d01465e..9b43c84 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -174,7 +174,7 @@ static void power_init(void)
struct pmic *p;
int ret;
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return;
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 3b398b6..13519e2 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -81,7 +81,7 @@ void power_init(void)
struct pmic *p;
int ret;
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(I2C_0);
if (ret)
return;
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index ae7eca8..db0bf17 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -258,7 +258,7 @@ static int power_init(void)
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(I2C_0);
if (ret)
return ret;
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 05c938f..e063407 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/gpio.h>
@@ -38,52 +38,52 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart4_pads[] = {
- MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c55ee87..fc75eae 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -11,7 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
@@ -51,25 +51,25 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart4_pads[] = {
- MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
@@ -77,12 +77,12 @@ iomux_v3_cfg_t const enet_pads[] = {
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
@@ -94,22 +94,22 @@ struct i2c_pads_info i2c_pad_info1 = {
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
iomux_v3_cfg_t const i2c3_pads[] = {
- MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const port_exp[] = {
- MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_enet(void)
@@ -118,18 +118,18 @@ static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 9dbe605..2ffc3b8 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -45,28 +48,28 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
- MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_enet(void)
@@ -80,44 +83,62 @@ static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
};
static void setup_iomux_uart(void)
@@ -249,8 +270,22 @@ static int detect_hdmi(struct display_info_t const *dev)
return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
}
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ int reg = readl(&iomux->gpr[2]);
+
+ reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+
+ writel(reg, &iomux->gpr[2]);
+}
+
static void do_enable_hdmi(struct display_info_t const *dev)
{
+ disable_lvds(dev);
imx_enable_hdmi_phy();
}
@@ -259,18 +294,19 @@ static void enable_lvds(struct display_info_t const *dev)
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
- IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
writel(reg, &iomux->gpr[2]);
}
+
static struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = enable_lvds,
.mode = {
- .name = "HDMI",
+ .name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
@@ -286,11 +322,11 @@ static struct display_info_t const displays[] = {{
} }, {
.bus = -1,
.addr = 0,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = NULL,
- .enable = enable_lvds,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
.mode = {
- .name = "Hannstar-XGA",
+ .name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
@@ -356,11 +392,14 @@ static void setup_display(void)
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
+ /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+ imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
- reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
writel(reg, &mxc_ccm->CCGR3);
@@ -440,6 +479,10 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+
return 0;
}
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 76753f9..16769e5 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -159,7 +159,7 @@ static void power_init(void)
struct pmic *p;
int ret;
- ret = pmic_init(I2C_PMIC);
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return;
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c
index 92dd4ff..a136dc4 100644
--- a/board/icpdas/lp8x4x/lp8x4x.c
+++ b/board/icpdas/lp8x4x/lp8x4x.c
@@ -61,15 +61,24 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_CMD_USB
int board_usb_init(int index, enum usb_init_type init)
{
- writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
+ if (index !=0 || init != USB_INIT_HOST)
+ return -1;
+
+ writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR)
continue; /* required by checkpath.pl */
+ writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+ writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x800, UHCRHDA);
+
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
@@ -83,19 +92,10 @@ int board_usb_init(int index, enum usb_init_type init)
/* Set port power control mask bits, only 3 ports. */
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
- /* enable port 2 */
- writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
- UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
return 0;
}
-void usb_board_stop(void)
+int usb_board_stop(void)
{
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
@@ -104,32 +104,25 @@ void usb_board_stop(void)
writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
+ writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
+
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
- return;
+ return 0;
}
-#endif
-#ifdef CONFIG_DRIVER_DM9000
-void lp8x4x_eth1_mac_init(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- u8 eth1addr[8];
- int i;
- u8 reg;
-
- eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
- if (!is_valid_ether_addr(eth1addr))
- return;
-
- for (i = 0, reg = 0x10; i < 6; i++, reg++) {
- writeb(reg, (u8 *)(DM9000_IO_2));
- writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
- }
+ if (index !=0 || init != USB_INIT_HOST)
+ return -1;
+
+ return usb_board_stop();
}
+#endif
+#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
- lp8x4x_eth1_mac_init();
return dm9000_initialize(bis);
}
#endif
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 6a8ca2b..089a835 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -77,9 +77,17 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
void sdram_init(void)
{
- config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(400, &ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 1569905..24be6ea 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -22,6 +22,7 @@
#include <asm/arch/musb.h>
#include <asm/mach-types.h>
#include <asm/errno.h>
+#include <asm/gpio.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
@@ -31,6 +32,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define AM3517_IP_SW_RESET 0x48002598
+#define CPGMACSS_SW_RST (1 << 1)
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -98,6 +102,9 @@ static void am3517_evm_musb_init(void)
*/
int misc_init_r(void)
{
+ volatile unsigned int ctr;
+ u32 reset;
+
#ifdef CONFIG_SYS_I2C_OMAP34XX
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
@@ -106,6 +113,31 @@ int misc_init_r(void)
am3517_evm_musb_init();
+ /* activate PHY reset */
+ gpio_direction_output(30, 0);
+ gpio_set_value(30, 0);
+
+ ctr = 0;
+ do {
+ udelay(1000);
+ ctr++;
+ } while (ctr < 300);
+
+ /* deactivate PHY reset */
+ gpio_set_value(30, 1);
+
+ /* allow the PHY to stabilize and settle down */
+ ctr = 0;
+ do {
+ udelay(1000);
+ ctr++;
+ } while (ctr < 300);
+
+ /* ensure that the module is out of reset */
+ reset = readl(AM3517_IP_SW_RESET);
+ reset &= (~CPGMACSS_SW_RST);
+ writel(reset,AM3517_IP_SW_RESET);
+
return 0;
}
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index 704af84..d407d66 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
/*SYS_nRESWARM */\
- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
/* - PEN_IRQ */\
diff --git a/board/logicpd/zoom2/Makefile b/board/logicpd/zoom2/Makefile
deleted file mode 100644
index 8ec5f25..0000000
--- a/board/logicpd/zoom2/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := zoom2.o
-obj-y += debug_board.o
-obj-y += zoom2_serial.o
-obj-$(CONFIG_STATUS_LED) += led.o
diff --git a/board/logicpd/zoom2/config.mk b/board/logicpd/zoom2/config.mk
deleted file mode 100644
index 1c382f7..0000000
--- a/board/logicpd/zoom2/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2009
-# Texas Instruments, <www.ti.com>
-#
-# Zoom II uses OMAP3 (ARM-CortexA8) CPU
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Physical Address:
-# 0x80000000 (bank0)
-# 0xA0000000 (bank1)
-# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c
deleted file mode 100644
index 071f410..0000000
--- a/board/logicpd/zoom2/debug_board.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/mux.h>
-#include <asm/gpio.h>
-
-#define DEBUG_BOARD_CONNECTED 1
-#define DEBUG_BOARD_NOT_CONNECTED 0
-
-static int debug_board_connected = DEBUG_BOARD_CONNECTED;
-
-static void zoom2_debug_board_detect (void)
-{
- int val = 0;
-
- if (!gpio_request(158, "")) {
- /*
- * GPIO to query for debug board
- * 158 db board query
- */
- gpio_direction_input(158);
- val = gpio_get_value(158);
- }
-
- if (!val)
- debug_board_connected = DEBUG_BOARD_NOT_CONNECTED;
-}
-
-int zoom2_debug_board_connected (void)
-{
- static int first_time = 1;
-
- if (first_time) {
- zoom2_debug_board_detect ();
- first_time = 0;
- }
- return debug_board_connected;
-}
diff --git a/board/logicpd/zoom2/led.c b/board/logicpd/zoom2/led.c
deleted file mode 100644
index 5d37ac1..0000000
--- a/board/logicpd/zoom2/led.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-
-static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
-
-/*
- * GPIO LEDs
- * 173 red
- * 154 blue
- * 61 blue2
- */
-#define ZOOM2_LED_RED 173
-#define ZOOM2_LED_BLUE 154
-#define ZOOM2_LED_BLUE2 61
-
-void red_led_off(void)
-{
- /* red */
- if (!gpio_request(ZOOM2_LED_RED, "")) {
- gpio_direction_output(ZOOM2_LED_RED, 0);
- gpio_set_value(ZOOM2_LED_RED, 0);
- }
- saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void blue_led_off(void)
-{
- /* blue */
- if (!gpio_request(ZOOM2_LED_BLUE, "")) {
- gpio_direction_output(ZOOM2_LED_BLUE, 0);
- gpio_set_value(ZOOM2_LED_BLUE, 0);
- }
-
- /* blue 2 */
- if (!gpio_request(ZOOM2_LED_BLUE2, "")) {
- gpio_direction_output(ZOOM2_LED_BLUE2, 0);
- gpio_set_value(ZOOM2_LED_BLUE2, 0);
- }
- saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
-}
-
-void red_led_on(void)
-{
- blue_led_off();
-
- /* red */
- if (!gpio_request(ZOOM2_LED_RED, "")) {
- gpio_direction_output(ZOOM2_LED_RED, 0);
- gpio_set_value(ZOOM2_LED_RED, 1);
- }
- saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void blue_led_on(void)
-{
- red_led_off();
-
- /* blue */
- if (!gpio_request(ZOOM2_LED_BLUE, "")) {
- gpio_direction_output(ZOOM2_LED_BLUE, 0);
- gpio_set_value(ZOOM2_LED_BLUE, 1);
- }
-
- /* blue 2 */
- if (!gpio_request(ZOOM2_LED_BLUE2, "")) {
- gpio_direction_output(ZOOM2_LED_BLUE2, 0);
- gpio_set_value(ZOOM2_LED_BLUE2, 1);
- }
-
- saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
-}
-
-void __led_init (led_id_t mask, int state)
-{
- __led_set (mask, state);
-}
-
-void __led_toggle (led_id_t mask)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
- blue_led_off();
- else
- blue_led_on();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
- red_led_off();
- else
- red_led_on();
- }
-}
-
-void __led_set (led_id_t mask, int state)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == state)
- blue_led_on();
- else
- blue_led_off();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
- red_led_on();
- else
- red_led_off();
- }
-}
diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c
deleted file mode 100644
index e14de04..0000000
--- a/board/logicpd/zoom2/zoom2.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * Derived from Zoom1 code by
- * Nishanth Menon <nm@ti.com>
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/gpio.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "zoom2.h"
-#include "zoom2_serial.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This the the zoom2, board specific, gpmc configuration for the
- * quad uart on the debug board. The more general gpmc configurations
- * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c
- *
- * The details of the setting of the serial gpmc setup are not available.
- * The values were provided by another party.
- */
-static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
- 0x00011000,
- 0x001F1F01,
- 0x00080803,
- 0x1D091D09,
- 0x041D1F1F,
- 0x1D0904C4, 0
-};
-
-/* Used to track the revision of the board */
-static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN;
-
-/*
- * Routine: zoom2_get_revision
- * Description: Return the revision of the Zoom2 this code is running on.
- */
-zoom2_revision zoom2_get_revision(void)
-{
- return revision;
-}
-
-/*
- * Routine: zoom2_identify
- * Description: Detect which version of Zoom2 we are running on.
- */
-void zoom2_identify(void)
-{
- /*
- * To check for production board vs beta board,
- * check if gpio 94 is clear.
- *
- * No way yet to check for alpha board identity.
- * Alpha boards were produced in very limited quantities
- * and they are not commonly used. They are mentioned here
- * only for completeness.
- */
- if (!gpio_request(94, "")) {
- unsigned int val;
-
- gpio_direction_input(94);
- val = gpio_get_value(94);
-
- if (val)
- revision = ZOOM2_REVISION_BETA;
- else
- revision = ZOOM2_REVISION_PRODUCTION;
- }
-
- printf("Board revision ");
- switch (revision) {
- case ZOOM2_REVISION_PRODUCTION:
- printf("Production\n");
- break;
- case ZOOM2_REVISION_BETA:
- printf("Beta\n");
- break;
- default:
- printf("Unknown\n");
- break;
- }
-}
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init (void)
-{
- u32 *gpmc_config;
-
- gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
-
- /* Configure console support on zoom2 */
- gpmc_config = gpmc_serial_TL16CP754C;
- enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3],
- SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
-
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
- status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure zoom board specific configurations
- */
-int misc_init_r(void)
-{
- zoom2_identify();
- twl4030_power_init();
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
- dieid_num_r();
-
- /*
- * Board Reset
- * The board is reset by holding the the large button
- * on the top right side of the main board for
- * eight seconds.
- *
- * There are reported problems of some beta boards
- * continously resetting. For those boards, disable resetting.
- */
- if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision())
- twl4030_power_reset_init();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs (void)
-{
- /* platform specific muxes */
- MUX_ZOOM2 ();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/logicpd/zoom2/zoom2.h b/board/logicpd/zoom2/zoom2.h
deleted file mode 100644
index 850c790..0000000
--- a/board/logicpd/zoom2/zoom2.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * Derived from: board/omap3/zoom1/zoom1.h
- * Nishanth Menon <nm@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _BOARD_ZOOM2_H_
-#define _BOARD_ZOOM2_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 Zoom2 ",
- "NAND",
-};
-
-typedef enum {
- ZOOM2_REVISION_UNKNOWN = 0,
- ZOOM2_REVISION_ALPHA,
- ZOOM2_REVISION_BETA,
- ZOOM2_REVISION_PRODUCTION
-} zoom2_revision;
-
-zoom2_revision zoom2_get_revision(void);
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_ZOOM2() \
- /* SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
-/* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\
-/* IDCC modem Power On */\
- MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\
- MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\
-/* GPMC CS7 has LAN9211 device */\
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\
-/* GPMC CS3 has Serial TL16CP754C device */\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\
-/* Toggle Reset pin of TL16CP754C device */\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\
- udelay(10);\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\
-/* LEDS */\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */
-
-#endif /* _BOARD_ZOOM2_H_ */
diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c
deleted file mode 100644
index 2959276..0000000
--- a/board/logicpd/zoom2/zoom2_serial.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c
- */
-
-#include <common.h>
-#include <serial.h>
-#include <ns16550.h>
-#include <asm/arch/cpu.h>
-#include "zoom2_serial.h"
-
-int quad_init_dev (unsigned long base)
-{
- /*
- * The Quad UART is on the debug board.
- * Check if the debug board is attached before using the UART
- */
- if (zoom2_debug_board_connected ()) {
- NS16550_t com_port = (NS16550_t) base;
- int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 /
- CONFIG_BAUDRATE;
-
- /*
- * Zoom2 has a board specific initialization of its UART.
- * This generic initialization has been copied from
- * drivers/serial/ns16550.c. The macros have been expanded.
- *
- * Do the following instead of
- *
- * NS16550_init (com_port, clock_divisor);
- */
- com_port->ier = 0x00;
-
- /*
- * On Zoom2 board Set pre-scalar to 1
- * CLKSEL is GND => MCR[7] is 1 => preslr is 4
- * So change the prescl to 1
- */
- com_port->lcr = 0xBF;
- com_port->fcr |= 0x10;
- com_port->mcr &= 0x7F;
-
- /* This is generic ns16550.c setup */
- com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
- com_port->dll = 0;
- com_port->dlm = 0;
- com_port->lcr = UART_LCR_8N1;
- com_port->mcr = UART_MCR_DTR | UART_MCR_RTS;
- com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR |
- UART_FCR_TXSR;
- com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
- com_port->dll = baud_divisor & 0xff;
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = UART_LCR_8N1;
- }
- /*
- * We have to lie here, otherwise the board init code will hang
- * on the check
- */
- return 0;
-}
-
-void quad_putc_dev (unsigned long base, const char c)
-{
- if (zoom2_debug_board_connected ()) {
-
- if (c == '\n')
- quad_putc_dev (base, '\r');
-
- NS16550_putc ((NS16550_t) base, c);
- } else {
- usbtty_putc(c);
- }
-}
-
-void quad_puts_dev (unsigned long base, const char *s)
-{
- if (zoom2_debug_board_connected ()) {
- while ((s != NULL) && (*s != '\0'))
- quad_putc_dev (base, *s++);
- } else {
- usbtty_puts(s);
- }
-}
-
-int quad_getc_dev (unsigned long base)
-{
- if (zoom2_debug_board_connected ())
- return NS16550_getc ((NS16550_t) base);
-
- return usbtty_getc();
-}
-
-int quad_tstc_dev (unsigned long base)
-{
- if (zoom2_debug_board_connected ())
- return NS16550_tstc ((NS16550_t) base);
-
- return usbtty_tstc();
-}
-
-void quad_setbrg_dev (unsigned long base)
-{
- if (zoom2_debug_board_connected ()) {
-
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 /
- CONFIG_BAUDRATE;
-
- NS16550_reinit ((NS16550_t) base, clock_divisor);
- }
-}
-
-QUAD_INIT (0)
-QUAD_INIT (1)
-QUAD_INIT (2)
-QUAD_INIT (3)
-
-struct serial_device *default_serial_console(void)
-{
- switch (ZOOM2_DEFAULT_SERIAL_DEVICE) {
- case 0: return &zoom2_serial_device0;
- case 1: return &zoom2_serial_device1;
- case 2: return &zoom2_serial_device2;
- case 3: return &zoom2_serial_device3;
- }
-}
diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h
deleted file mode 100644
index 8224452..0000000
--- a/board/logicpd/zoom2/zoom2_serial.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ZOOM2_SERIAL_H
-#define ZOOM2_SERIAL_H
-
-#include <linux/stringify.h>
-
-extern int zoom2_debug_board_connected (void);
-
-#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */
-
-#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE
-#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100)
-#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200)
-#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300)
-
-#define QUAD_INIT(n) \
-int quad_init_##n(void) \
-{ \
- return quad_init_dev(QUAD_BASE_##n); \
-} \
-void quad_setbrg_##n(void) \
-{ \
- quad_setbrg_dev(QUAD_BASE_##n); \
-} \
-void quad_putc_##n(const char c) \
-{ \
- quad_putc_dev(QUAD_BASE_##n, c); \
-} \
-void quad_puts_##n(const char *s) \
-{ \
- quad_puts_dev(QUAD_BASE_##n, s); \
-} \
-int quad_getc_##n(void) \
-{ \
- return quad_getc_dev(QUAD_BASE_##n); \
-} \
-int quad_tstc_##n(void) \
-{ \
- return quad_tstc_dev(QUAD_BASE_##n); \
-} \
-struct serial_device zoom2_serial_device##n = \
-{ \
- .name = __stringify(n), \
- .start = quad_init_##n, \
- .stop = NULL, \
- .setbrg = quad_setbrg_##n, \
- .getc = quad_getc_##n, \
- .tstc = quad_tstc_##n, \
- .putc = quad_putc_##n, \
- .puts = quad_puts_##n, \
-};
-
-#endif /* ZOOM2_SERIAL_H */
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 68463e7..7e5e07f 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -50,6 +50,14 @@ const struct dpll_params *get_dpll_ddr_params(void)
}
#ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -81,10 +89,18 @@ static struct emif_regs ddr3_emif_reg_data = {
void sdram_init(void)
{
- config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#else
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
@@ -116,7 +132,7 @@ static struct emif_regs ddr3_emif_reg_data = {
void sdram_init(void)
{
- config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 7153f65..89f5c91 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -16,6 +16,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
#include <i2c.h>
#include "qos.h"
@@ -207,6 +209,10 @@ void s_init(void)
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
+#define MSTPSR8 0xE61509A0
+#define SMSTPCR8 0xE6150990
+#define ETHER_MSTP813 (1 << 13)
+
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
@@ -241,9 +247,16 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
return 0;
}
+/* LSI pin pull-up control */
+#define PUPR5 0xe6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC (1 << 27)
int board_init(void)
{
/* adress of boot parameters */
@@ -252,9 +265,59 @@ int board_init(void)
/* Init PFC controller */
r8a7791_pinmux_init();
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+ gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+ gpio_direction_output(GPIO_GP_5_22, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_22, 1);
+ udelay(1);
+
return 0;
}
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@@ -263,6 +326,20 @@ int dram_init(void)
return 0;
}
+/* koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+ return 0;
+}
+
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
@@ -280,4 +357,10 @@ int board_late_init(void)
void reset_cpu(ulong addr)
{
+ u8 val;
+
+ i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 5c99fc9..cdd5b32 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -18,6 +18,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <miiphy.h>
+#include <i2c.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -207,6 +209,10 @@ void s_init(void)
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
+#define MSTPSR8 0xE61509A0
+#define SMSTPCR8 0xE6150990
+#define ETHER_MSTP813 (1 << 13)
+
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
@@ -242,6 +248,9 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
return 0;
}
@@ -256,6 +265,68 @@ int board_init(void)
/* Init PFC controller */
r8a7790_pinmux_init();
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
+ gpio_direction_output(GPIO_GP_5_31, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_31, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_ETHER
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+#endif
+
+ return ret;
+}
+
+/* lager has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
return 0;
}
@@ -284,4 +355,11 @@ int board_late_init(void)
void reset_cpu(ulong addr)
{
+ u8 val;
+
+ i2c_set_bus_num(3); /* PowerIC connected to ch3 */
+ i2c_init(400000, 0);
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 501d974..22bd6b1 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -8,3 +8,7 @@
obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
obj-$(CONFIG_THOR_FUNCTION) += thor.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_BOARD_COMMON) += board.o
+endif
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
new file mode 100644
index 0000000..cd873bc
--- /dev/null
+++ b/board/samsung/common/board.c
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <tmu.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <power/pmic.h>
+#include <asm/arch/sromc.h>
+#include <power/max77686_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct local_info {
+ struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
+ int cros_ec_err; /* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+#if defined CONFIG_EXYNOS_TMU
+/* Boot Time Thermal Analysis for SoC temperature threshold breach */
+static void boot_temp_check(void)
+{
+ int temp;
+
+ switch (tmu_monitor(&temp)) {
+ case TMU_STATUS_NORMAL:
+ break;
+ case TMU_STATUS_TRIPPED:
+ /*
+ * Status TRIPPED ans WARNING means corresponding threshold
+ * breach
+ */
+ puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+ set_ps_hold_ctrl();
+ hang();
+ break;
+ case TMU_STATUS_WARNING:
+ puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+ break;
+ case TMU_STATUS_INIT:
+ /*
+ * TMU_STATUS_INIT means something is wrong with temperature
+ * sensing and TMU status was changed back from NORMAL to INIT.
+ */
+ puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
+ break;
+ default:
+ debug("EXYNOS_TMU: Unknown TMU state\n");
+ }
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+ if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+ debug("%s: Failed to init TMU\n", __func__);
+ return -1;
+ }
+ boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+ return exynos_init();
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
+ }
+}
+
+static int board_uart_init(void)
+{
+ int err, uart_id, ret = 0;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ ret |= err;
+ }
+ }
+ return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ board_i2c_init(gd->fdt_blob);
+#endif
+
+ return err;
+}
+#endif
+
+struct cros_ec_dev *board_get_cros_ec_dev(void)
+{
+ return local.cros_ec_dev;
+}
+
+#ifdef CONFIG_CROS_EC
+static int board_init_cros_ec_devices(const void *blob)
+{
+ local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
+ if (local.cros_ec_err)
+ return -1; /* Will report in board_late_init() */
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+static int max77686_init(void)
+{
+ struct pmic *p;
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif
+
+int power_init_board(void)
+{
+ int ret = 0;
+
+ set_ps_hold_ctrl();
+
+#ifdef CONFIG_POWER_MAX77686
+ ret = max77686_init();
+#endif
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_OF_CONTROL
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+ int err;
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+ if (node < 0) {
+ debug("Could not find SROMC node\n");
+ return node;
+ }
+
+ config->bank = fdtdec_get_int(blob, node, "bank", 0);
+ config->width = fdtdec_get_int(blob, node, "width", 2);
+
+ err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+ FDT_SROM_TIMING_COUNT);
+ if (err < 0) {
+ debug("Could not decode SROMC configuration Error: %s\n",
+ fdt_strerror(err));
+ return -FDT_ERR_NOTFOUND;
+ }
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+ u32 smc_bw_conf, smc_bc_conf;
+ struct fdt_sromc config;
+ fdt_addr_t base_addr;
+ int node;
+
+ node = decode_sromc(gd->fdt_blob, &config);
+ if (node < 0) {
+ debug("%s: Could not find sromc configuration\n", __func__);
+ return 0;
+ }
+ node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+ if (node < 0) {
+ debug("%s: Could not find lan9215 configuration\n", __func__);
+ return 0;
+ }
+
+ /* We now have a node, so any problems from now on are errors */
+ base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (base_addr == FDT_ADDR_T_NONE) {
+ debug("%s: Could not find lan9215 address\n", __func__);
+ return -1;
+ }
+
+ /* Ethernet needs data bus width of 16 bits */
+ if (config.width != 2) {
+ debug("%s: Unsupported bus width %d\n", __func__,
+ config.width);
+ return -1;
+ }
+ smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+ | SROMC_BYTE_ENABLE(config.bank);
+
+ smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
+ SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+ SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+ SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+ SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
+ SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+ SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+ /* Select and configure the SROMC bank */
+ exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+ s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+ return smc911x_initialize(0, base_addr);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* dwmmc initializattion for available channels */
+ ret = exynos_dwmmc_init(gd->fdt_blob);
+ if (ret)
+ debug("dwmmc init failed\n");
+
+ return ret;
+}
+#endif
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ stdio_print_current_devices();
+
+ if (local.cros_ec_err) {
+ /* Force console on */
+ gd->flags &= ~GD_FLG_SILENT;
+
+ printf("cros-ec communications failure %d\n",
+ local.cros_ec_err);
+ puts("\nPlease reset with Power+Refresh\n\n");
+ panic("Cannot init cros-ec device");
+ return -1;
+ }
+ return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+ if (board_init_cros_ec_devices(gd->fdt_blob)) {
+ printf("%s: Failed to init EC\n", __func__);
+ return 0;
+ }
+#endif
+
+ return 0;
+}
diff --git a/board/samsung/dts/exynos5420-smdk5420.dts b/board/samsung/dts/exynos5420-smdk5420.dts
new file mode 100644
index 0000000..d739763
--- /dev/null
+++ b/board/samsung/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,169 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos5420.dtsi"
+
+/ {
+ model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
+ compatible = "samsung,smdk5420", "samsung,exynos5";
+
+ config {
+ hwid = "smdk5420 TEST A-A 9382";
+ };
+
+ aliases {
+ i2c0 = "/i2c@12c60000";
+ i2c1 = "/i2c@12c70000";
+ i2c2 = "/i2c@12c80000";
+ i2c3 = "/i2c@12c90000";
+ i2c4 = "/i2c@12ca0000";
+ i2c5 = "/i2c@12cb0000";
+ i2c6 = "/i2c@12cc0000";
+ i2c7 = "/i2c@12cd0000";
+ i2c8 = "/i2c@12e00000";
+ i2c9 = "/i2c@12e10000";
+ i2c10 = "/i2c@12e20000";
+ spi0 = "/spi@12d20000";
+ spi1 = "/spi@12d30000";
+ spi2 = "/spi@12d40000";
+ spi3 = "/spi@131a0000";
+ spi4 = "/spi@131b0000";
+ mmc0 = "/mmc@12200000";
+ mmc1 = "/mmc@12210000";
+ mmc2 = "/mmc@12220000";
+ xhci0 = "/xhci@12000000";
+ xhci1 = "/xhci@12400000";
+ serial0 = "/serial@12C30000";
+ console = "/serial@12C30000";
+ };
+
+ tmu@10060000 {
+ samsung,min-temp = <25>;
+ samsung,max-temp = <125>;
+ samsung,start-warning = <95>;
+ samsung,start-tripping = <105>;
+ samsung,hw-tripping = <110>;
+ samsung,efuse-min-value = <40>;
+ samsung,efuse-value = <55>;
+ samsung,efuse-max-value = <100>;
+ samsung,slope = <274761730>;
+ samsung,dc-value = <25>;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c@12ca0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@66 {
+ reg = <0x66>;
+ compatible = "samsung,s2mps11-pmic";
+ };
+ };
+
+ spi@12d20000 { /* spi0 */
+ spi-max-frequency = <50000000>;
+ firmware_storage_spi: flash@0 {
+ reg = <0>;
+ };
+ };
+
+ fimd@14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <2560>;
+ samsung,vl-row = <1600>;
+ samsung,vl-width = <2560>;
+ samsung,vl-height = <1600>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <80>;
+ samsung,vl-hfpd = <48>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <37>;
+ samsung,vl-vfpd = <3>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
+
+ sound@3830000 {
+ samsung,codec-type = "wm8994";
+ };
+
+ i2c@12c70000 {
+ soundcodec@1a {
+ reg = <0x1a>;
+ compatible = "wolfson,wm8994-codec";
+ };
+ };
+
+ mmc@12200000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ samsung,removable = <0>;
+ samsung,pre-init;
+ };
+
+ mmc@12210000 {
+ status = "disabled";
+ };
+
+ mmc@12220000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ samsung,removable = <1>;
+ };
+
+ mmc@12230000 {
+ status = "disabled";
+ };
+
+ fimd@14400000 {
+ /* sysmmu is not used in U-Boot */
+ samsung,disable-sysmmu;
+ };
+
+ dp@145b0000 {
+ samsung,lt-status = <0>;
+
+ samsung,master-mode = <0>;
+ samsung,bist-mode = <0>;
+ samsung,bist-pattern = <0>;
+ samsung,h-sync-polarity = <0>;
+ samsung,v-sync-polarity = <0>;
+ samsung,interlaced = <0>;
+ samsung,color-space = <0>;
+ samsung,dynamic-range = <0>;
+ samsung,ycbcr-coeff = <0>;
+ samsung,color-depth = <1>;
+ };
+
+ dmc {
+ mem-type = "ddr3";
+ };
+
+ xhci1: xhci@12400000 {
+ compatible = "samsung,exynos5250-xhci";
+ reg = <0x12400000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy {
+ compatible = "samsung,exynos5250-usb3-phy";
+ reg = <0x12500000 0x100>;
+ };
+ };
+};
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index 6aa0509..5fb8664 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -25,44 +25,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined CONFIG_EXYNOS_TMU
-/*
- * Boot Time Thermal Analysis for SoC temperature threshold breach
- */
-static void boot_temp_check(void)
-{
- int temp;
-
- switch (tmu_monitor(&temp)) {
- /* Status TRIPPED ans WARNING means corresponding threshold breach */
- case TMU_STATUS_TRIPPED:
- puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
- set_ps_hold_ctrl();
- hang();
- break;
- case TMU_STATUS_WARNING:
- puts("EXYNOS_TMU: WARNING! Temperature very high\n");
- break;
- /*
- * TMU_STATUS_INIT means something is wrong with temperature sensing
- * and TMU status was changed back from NORMAL to INIT.
- */
- case TMU_STATUS_INIT:
- default:
- debug("EXYNOS_TMU: Unknown TMU state\n");
- }
-}
-#endif
-
-struct local_info {
- struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
- int cros_ec_err; /* Error for cros_ec, 0 if ok */
-};
-
-static struct local_info local;
-
#ifdef CONFIG_SOUND_MAX98095
-static void board_enable_audio_codec(void)
+static void board_enable_audio_codec(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
@@ -73,261 +37,14 @@ static void board_enable_audio_codec(void)
}
#endif
-struct cros_ec_dev *board_get_cros_ec_dev(void)
-{
- return local.cros_ec_dev;
-}
-
-static int board_init_cros_ec_devices(const void *blob)
+int exynos_init(void)
{
- local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
- if (local.cros_ec_err)
- return -1; /* Will report in board_late_init() */
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-
-#if defined CONFIG_EXYNOS_TMU
- if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
- debug("%s: Failed to init TMU\n", __func__);
- return -1;
- }
- boot_temp_check();
-#endif
-
-#ifdef CONFIG_EXYNOS_SPI
- spi_init();
-#endif
-
- if (board_init_cros_ec_devices(gd->fdt_blob))
- return -1;
-
#ifdef CONFIG_SOUND_MAX98095
board_enable_audio_codec();
#endif
return 0;
}
-int dram_init(void)
-{
- int i;
- u32 addr;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- }
- return 0;
-}
-
-#if defined(CONFIG_POWER)
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
-
- set_ps_hold_ctrl();
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif
-
-void dram_init_banksize(void)
-{
- int i;
- u32 addr, size;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
-
- gd->bd->bi_dram[i].start = addr;
- gd->bd->bi_dram[i].size = size;
- }
-}
-
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
- int err;
- int node;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
- if (node < 0) {
- debug("Could not find SROMC node\n");
- return node;
- }
-
- config->bank = fdtdec_get_int(blob, node, "bank", 0);
- config->width = fdtdec_get_int(blob, node, "width", 2);
-
- err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
- FDT_SROM_TIMING_COUNT);
- if (err < 0) {
- debug("Could not decode SROMC configuration Error: %s\n",
- fdt_strerror(err));
- return -FDT_ERR_NOTFOUND;
- }
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
- u32 smc_bw_conf, smc_bc_conf;
- struct fdt_sromc config;
- fdt_addr_t base_addr;
- int node;
-
- node = decode_sromc(gd->fdt_blob, &config);
- if (node < 0) {
- debug("%s: Could not find sromc configuration\n", __func__);
- return 0;
- }
- node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
- if (node < 0) {
- debug("%s: Could not find lan9215 configuration\n", __func__);
- return 0;
- }
-
- /* We now have a node, so any problems from now on are errors */
- base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
- if (base_addr == FDT_ADDR_T_NONE) {
- debug("%s: Could not find lan9215 address\n", __func__);
- return -1;
- }
-
- /* Ethernet needs data bus width of 16 bits */
- if (config.width != 2) {
- debug("%s: Unsupported bus width %d\n", __func__,
- config.width);
- return -1;
- }
- smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
- | SROMC_BYTE_ENABLE(config.bank);
-
- smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
- SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
- SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
- SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
- SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
- SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
- SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
-
- /* Select and configure the SROMC bank */
- exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
- s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
- return smc911x_initialize(0, base_addr);
-#endif
- return 0;
-}
-
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
@@ -343,50 +60,6 @@ int checkboard(void)
}
#endif
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- /* dwmmc initializattion for available channels */
- ret = exynos_dwmmc_init(gd->fdt_blob);
- if (ret)
- debug("dwmmc init failed\n");
-
- return ret;
-}
-#endif
-
-static int board_uart_init(void)
-{
- int err, uart_id, ret = 0;
-
- for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
- err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART%d not configured\n",
- (uart_id - PERIPH_ID_UART0));
- ret |= err;
- }
- }
- return ret;
-}
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- int err;
- err = board_uart_init();
- if (err) {
- debug("UART init failed\n");
- return err;
- }
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_i2c_init(gd->fdt_blob);
-#endif
- return err;
-}
-#endif
-
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
@@ -410,22 +83,3 @@ void exynos_set_dp_phy(unsigned int onoff)
set_dp_phy_ctrl(onoff);
}
#endif
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- stdio_print_current_devices();
-
- if (local.cros_ec_err) {
- /* Force console on */
- gd->flags &= ~GD_FLG_SILENT;
-
- printf("cros-ec communications failure %d\n",
- local.cros_ec_err);
- puts("\nPlease reset with Power+Refresh\n\n");
- panic("Cannot init cros-ec device");
- return -1;
- }
- return 0;
-}
-#endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 97fe0ad..943c29a 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <cros_ec.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <errno.h>
@@ -26,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
-int board_usb_vbus_init(void)
+static int board_usb_vbus_init(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
@@ -53,13 +54,8 @@ static void board_enable_audio_codec(void)
}
#endif
-int board_init(void)
+int exynos_init(void)
{
- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-
-#ifdef CONFIG_EXYNOS_SPI
- spi_init();
-#endif
#ifdef CONFIG_USB_EHCI_EXYNOS
board_usb_vbus_init();
#endif
@@ -69,147 +65,6 @@ int board_init(void)
return 0;
}
-int dram_init(void)
-{
- int i;
- u32 addr;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- }
- return 0;
-}
-
-#if defined(CONFIG_POWER)
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
-
- set_ps_hold_ctrl();
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1_05V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif
-
-void dram_init_banksize(void)
-{
- int i;
- u32 addr, size;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- gd->bd->bi_dram[i].start = addr;
- gd->bd->bi_dram[i].size = size;
- }
-}
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
@@ -301,21 +156,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
-static int board_uart_init(void)
-{
- int err, uart_id, ret = 0;
-
- for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
- err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART%d not configured\n",
- (uart_id - PERIPH_ID_UART0));
- ret |= err;
- }
- }
- return ret;
-}
-
void board_i2c_init(const void *blob)
{
int i;
@@ -326,22 +166,6 @@ void board_i2c_init(const void *blob)
}
}
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- int err;
- err = board_uart_init();
- if (err) {
- debug("UART init failed\n");
- return err;
- }
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_i2c_init(NULL);
-#endif
- return err;
-}
-#endif
-
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile
new file mode 100644
index 0000000..c2f8886
--- /dev/null
+++ b/board/samsung/smdk5420/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += smdk5420_spl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += smdk5420.o
+endif
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
new file mode 100644
index 0000000..3ad2ad0
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <spi.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dp_info.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+static int board_usb_vbus_init(void)
+{
+ struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
+
+ /* Enable VBUS power switch */
+ s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+ /* VBUS turn ON time */
+ mdelay(3);
+
+ return 0;
+}
+#endif
+
+int exynos_init(void)
+{
+#ifdef CONFIG_USB_EHCI_EXYNOS
+ board_usb_vbus_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ /* For Backlight */
+ s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+ /* LCD power on */
+ s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+ /* Set Hotplug detect for DP */
+ s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 2560,
+ .vl_row = 1600,
+ .vl_width = 2560,
+ .vl_height = 1600,
+ .vl_clkp = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_LOW,
+ .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
+
+ /* wDP panel timing infomation */
+ .vl_hspw = 32,
+ .vl_hbpd = 80,
+ .vl_hfpd = 48,
+
+ .vl_vspw = 6,
+ .vl_vbpd = 37,
+ .vl_vfpd = 3,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 3,
+ .cfg_gpio = cfg_lcd_gpio,
+ .backlight_on = NULL,
+ .lcd_power_on = NULL,
+ .reset_lcd = NULL,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 0,
+ .reset_delay = 0,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .dp_enabled = 1,
+};
+
+static struct edp_device_info edp_info = {
+ .disp_info = {
+ .h_res = 2560,
+ .h_sync_width = 32,
+ .h_back_porch = 80,
+ .h_front_porch = 48,
+ .v_res = 1600,
+ .v_sync_width = 6,
+ .v_back_porch = 37,
+ .v_front_porch = 3,
+ .v_sync_rate = 60,
+ },
+ .lt_info = {
+ .lt_status = DP_LT_NONE,
+ },
+ .video_info = {
+ .master_mode = 0,
+ .bist_mode = DP_DISABLE,
+ .bist_pattern = NO_PATTERN,
+ .h_sync_polarity = 0,
+ .v_sync_polarity = 0,
+ .interlaced = 0,
+ .color_space = COLOR_RGB,
+ .dynamic_range = VESA,
+ .ycbcr_coeff = COLOR_YCBCR601,
+ .color_depth = COLOR_8,
+ },
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+ .phy_enable = set_dp_phy_ctrl,
+ .edp_dev_info = &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->rgb_mode = MODE_RGB_P;
+
+ exynos_set_dp_platform_data(&dp_platform_data);
+}
+#endif
+
+int board_get_revision(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ const char *board_name;
+
+ board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ if (board_name == NULL)
+ printf("\nUnknown Board\n");
+ else
+ printf("\nBoard: %s\n", board_name);
+
+ return 0;
+}
+#endif
diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c
new file mode 100644
index 0000000..73359f7
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420_spl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 900,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 8aba51c..640a193 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -295,7 +295,7 @@ int power_init_board(void)
*/
ret = pmic_init(I2C_5);
ret |= pmic_init_max8997();
- ret |= power_fg_init(I2C_8);
+ ret |= power_fg_init(I2C_9);
ret |= power_muic_init(I2C_5);
ret |= power_bat_init(0);
if (ret)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 147de17..be15357 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -195,9 +195,9 @@ int power_init_board(void)
#endif
pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
pmic_init_max77686();
- pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */
- power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */
- power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */
+ pmic_init_max77693(I2C_10); /* I2C adapter 10 - bus name soft1 */
+ power_muic_init(I2C_10); /* I2C adapter 10 - bus name soft1 */
+ power_fg_init(I2C_9); /* I2C adapter 9 - bus name soft0 */
power_bat_init(0);
p_chrg = pmic_get("MAX77693_PMIC");
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 32d2ee4..7e8731b 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -159,13 +159,4 @@ U_BOOT_CMD(
"Sends U-Boot into infinite loop",
""
);
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- printf("Enable d-cache\n");
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
#endif /* !CONFIG_SPL_BUILD */
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index 3a5e11d..6c316fa 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = {
struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
};
+
+struct ctrl_ioregs dxr2_ddr3_ioregs = {
+};
+
/* pass values from eeprom */
dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
- config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
+ dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+ dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+ dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+ dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+ dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+ config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
}
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 0a25b4b..ef3d6cc 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -69,7 +69,15 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
.cmd2iclkout = 0,
};
- config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = DXR2_IOCTRL_VAL,
+ .cm1ioctl = DXR2_IOCTRL_VAL,
+ .cm2ioctl = DXR2_IOCTRL_VAL,
+ .dt0ioctl = DXR2_IOCTRL_VAL,
+ .dt1ioctl = DXR2_IOCTRL_VAL,
+};
+
+ config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
&pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
}
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 77592db..25ab54d 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -74,7 +74,15 @@ struct cmd_control rut_ddr3_cmd_ctrl_data = {
.cmd2iclkout = 1,
};
- config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = RUT_IOCTRL_VAL,
+ .cm1ioctl = RUT_IOCTRL_VAL,
+ .cm2ioctl = RUT_IOCTRL_VAL,
+ .dt0ioctl = RUT_IOCTRL_VAL,
+ .dt1ioctl = RUT_IOCTRL_VAL,
+};
+
+ config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
}
diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile
new file mode 100644
index 0000000..2aff383
--- /dev/null
+++ b/board/technexion/tao3530/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tao3530.o
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
new file mode 100644
index 0000000..44a8240
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.c
@@ -0,0 +1,215 @@
+/*
+ * Maintainer :
+ * Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+
+#include <usb.h>
+#include <asm/ehci-omap.h>
+
+#include "tao3530.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int tao3530_revision(void)
+{
+ int ret = 0;
+
+ /* char *label argument is unused in gpio_request() */
+ ret = gpio_request(65, "");
+ if (ret) {
+ puts("Error: GPIO 65 not available\n");
+ goto out;
+ }
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
+
+ ret = gpio_request(1, "");
+ if (ret) {
+ puts("Error: GPIO 1 not available\n");
+ goto out2;
+ }
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
+
+ ret = gpio_direction_input(65);
+ if (ret) {
+ puts("Error: GPIO 65 not available for input\n");
+ goto out3;
+ }
+
+ ret = gpio_direction_input(1);
+ if (ret) {
+ puts("Error: GPIO 1 not available for input\n");
+ goto out3;
+ }
+
+ ret = gpio_get_value(65) << 1 | gpio_get_value(1);
+
+out3:
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
+ gpio_free(1);
+out2:
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
+ gpio_free(65);
+out:
+
+ return ret;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+ /*
+ * Switch baseboard LED to red upon power-on
+ */
+ MUX_OMAP3_HA();
+
+ /* Request a gpio before using it */
+ gpio_request(111, "");
+ /* Sets the gpio as output and its value to 1, switch LED to red */
+ gpio_direction_output(111, 1);
+#endif
+
+ if (tao3530_revision() < 3) {
+ /* 256MB / Bank */
+ timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
+ timings->ctrla = HYNIX_V_ACTIMA_165;
+ timings->ctrlb = HYNIX_V_ACTIMB_165;
+ } else {
+ /* 128MB / Bank */
+ timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ }
+
+ timings->mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+ /* Configure GPIOs to output */
+ /* GPIO23 */
+ writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+ writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+ /* Set GPIOs */
+ writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
+ &gpio6_base->setdataout);
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+ switch (tao3530_revision()) {
+ case 0:
+ puts("TAO-3530 REV Reserve 1\n");
+ break;
+ case 1:
+ puts("TAO-3530 REV Reserve 2\n");
+ break;
+ case 2:
+ puts("TAO-3530 REV Cx\n");
+ break;
+ case 3:
+ puts("TAO-3530 REV Ax/Bx\n");
+ break;
+ default:
+ puts("Unknown board revision\n");
+ }
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_TAO3530();
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+ MUX_OMAP3_HA();
+#endif
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if (val == BOOTSTAGE_ID_RUN_OS)
+ usb_stop();
+}
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI */
diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h
new file mode 100644
index 0000000..daff109
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.h
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright TechNexion 2010
+ * Edward Lin <linuxfae@technexion.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _TAO3530_H_
+#define _TAO3530_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+ "HEAD acoustics OMAP3-HA",
+#else
+ "OMAP3 TAO-3530 board",
+#endif
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TAO3530() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \
+ /* MMC2 WLAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
+ /*LocalBus LAN Reset*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
+ /*LocalBus LAN IRQ*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0))
+
+#define MUX_OMAP3_HA() \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */
+
+#endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 33693e4..5721768 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -426,6 +426,38 @@ void set_mux_conf_regs(void)
enable_board_pin_mux(&header);
}
+const struct ctrl_ioregs ioregs_evmsk = {
+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+ .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
@@ -443,18 +475,18 @@ void sdram_init(void)
}
if (board_is_evm_sk(&header))
- config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(303, &ioregs_evmsk, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt(&header))
- config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
+ config_ddr(400, &ioregs_bonelt,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
else if (board_is_evm_15_or_later(&header))
- config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+ config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else
- config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+ config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 51b2576..ed87cd9 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -9,22 +9,326 @@
*/
#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
#include <spl.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am43xx_board_id *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ printf("Could not probe the EEPROM at 0x%x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct am43xx_board_id))) {
+ printf("Could not read the EEPROM\n");
+ return -EIO;
+ }
+
+ if (header->magic != 0xEE3355AA) {
+ /*
+ * read the eeprom using i2c again,
+ * but use only a 1 byte address
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct am43xx_board_id))) {
+ printf("Could not read the EEPROM at 0x%x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return -EIO;
+ }
+
+ if (header->magic != 0xEE3355AA) {
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header->magic);
+ return -EINVAL;
+ }
+ }
+
+ strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
+ am43xx_board_name[sizeof(header->name)] = 0;
+
+ return 0;
+}
+
#ifdef CONFIG_SPL_BUILD
-const struct dpll_params dpll_ddr = {
- -1, -1, -1, -1, -1, -1, -1};
+#define NUM_OPPS 6
+
+const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+ { /* 19.2 MHz */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
+ {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
+ },
+ { /* 24 MHz */
+ {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
+ {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
+ },
+ { /* 25 MHz */
+ {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
+ {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
+ },
+ { /* 26 MHz */
+ {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
+ {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
+ },
+};
+
+const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
+ {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
+ {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
+ {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
+};
+
+const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
+ {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
+ {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
+ {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
+};
+
+const struct dpll_params epos_evm_dpll_ddr = {
+ 266, 24, 1, -1, 1, -1, -1};
+
+const struct dpll_params gp_evm_dpll_ddr = {
+ 400, 23, 1, -1, 1, -1, -1};
+
+const struct ctrl_ioregs ioregs_lpddr2 = {
+ .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+ .sdram_config = 0x808012BA,
+ .ref_ctrl = 0x0000040D,
+ .sdram_tim1 = 0xEA86B411,
+ .sdram_tim2 = 0x103A094A,
+ .sdram_tim3 = 0x0F6BA37F,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_rd_wr_lvl_rmp_win = 0x0,
+ .emif_rd_wr_lvl_rmp_ctl = 0x0,
+ .emif_rd_wr_lvl_ctl = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E084006,
+ .emif_rd_wr_exec_thresh = 0x00000405,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00500050
+};
+
+const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+ 0x00500050,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40001000,
+ 0x08102040
+};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x0043,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E084008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
+ .emif_rd_wr_lvl_rmp_win = 0x0,
+ .emif_rd_wr_lvl_rmp_ctl = 0x0,
+ .emif_rd_wr_lvl_ctl = 0x0,
+ .emif_rd_wr_exec_thresh = 0x00000405
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+ 0x00400040,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+ if (board_is_eposevm()) {
+ *regs = ext_phy_ctrl_const_base_lpddr2;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+ } else if (board_is_gpevm()) {
+ *regs = ext_phy_ctrl_const_base_ddr3;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+ }
+
+ return;
+}
const struct dpll_params *get_dpll_ddr_params(void)
{
- return &dpll_ddr;
+ struct am43xx_board_id header;
+
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ if (board_is_eposevm())
+ return &epos_evm_dpll_ddr;
+ else if (board_is_gpevm())
+ return &gp_evm_dpll_ddr;
+
+ puts(" Board not supported\n");
+ return NULL;
+}
+
+/*
+ * get_sys_clk_index : returns the index of the sys_clk read from
+ * ctrl status register. This value is either
+ * read from efuse or sysboot pins.
+ */
+static u32 get_sys_clk_index(void)
+{
+ struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+ u32 ind = readl(&ctrl->statusreg), src;
+
+ src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+ if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+ return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+ CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+ else /* Value read from SYS BOOT pins */
+ return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+ CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+/*
+ * get_opp_offset:
+ * Returns the index for safest OPP of the device to boot.
+ * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
+ * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
+ * This data is read from dev_attribute register which is e-fused.
+ * A'1' in bit indicates OPP disabled and not available, a '0' indicates
+ * OPP available. Lowest OPP starts with min_off. So returning the
+ * bit with rightmost '0'.
+ */
+static int get_opp_offset(int max_off, int min_off)
+{
+ struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+ int opp = readl(&ctrl->dev_attr), offset, i;
+
+ for (i = max_off; i >= min_off; i--) {
+ offset = opp & (1 << i);
+ if (!offset)
+ return i;
+ }
+
+ return min_off;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+ int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
+ u32 ind = get_sys_clk_index();
+
+ return &dpll_mpu[ind][opp];
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+ int ind = get_sys_clk_index();
+
+ return &dpll_core[ind];
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+ int ind = get_sys_clk_index();
+
+ return &dpll_per[ind];
}
void set_uart_mux_conf(void)
@@ -37,14 +341,41 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
+static void enable_vtt_regulator(void)
+{
+ u32 temp;
+
+ /* enable module */
+ writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
+
+ /* enable output for GPIO0_22 */
+ writel(GPIO_SETDATAOUT(GPIO_22),
+ AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
+ temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+ temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
+ writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+}
+
void sdram_init(void)
{
+ /*
+ * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+ * GP EMV has 1GB DDR3 connected to EMIF
+ * along with VTT regulator.
+ */
+ if (board_is_eposevm()) {
+ config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+ } else if (board_is_gpevm()) {
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL,
+ &ddr3_emif_regs_400Mhz, 0);
+ }
}
#endif
int board_init(void)
{
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
@@ -52,6 +383,22 @@ int board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char safe_string[HDR_NAME_LEN + 1];
+ struct am43xx_board_id header;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Now set variables based on the header. */
+ strncpy(safe_string, (char *)header.name, sizeof(header.name));
+ safe_string[sizeof(header.name)] = 0;
+ setenv("board_name", safe_string);
+
+ strncpy(safe_string, (char *)header.version, sizeof(header.version));
+ safe_string[sizeof(header.version)] = 0;
+ setenv("board_rev", safe_string);
+#endif
return 0;
}
#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 8ca098b..091162e 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -12,6 +12,42 @@
#ifndef _BOARD_H_
#define _BOARD_H_
+#include <asm/arch/omap.h>
+
+static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+
+/*
+ * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+#define DEV_ATTR_MAX_OFFSET 5
+#define DEV_ATTR_MIN_OFFSET 0
+
+struct am43xx_board_id {
+ unsigned int magic;
+ char name[HDR_NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_eposevm(void)
+{
+ return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
+}
+
+static inline int board_is_gpevm(void)
+{
+ return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
+}
+
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
+void enable_i2c0_pin_mux(void);
#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 700e9a7..810b194 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -12,8 +12,29 @@
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
+ {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux gpio0_22_pin_mux[] = {
+ {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */
{-1},
};
@@ -24,4 +45,14 @@ void enable_uart0_pin_mux(void)
void enable_board_pin_mux(void)
{
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(i2c0_pin_mux);
+
+ if (board_is_gpevm())
+ configure_module_pin_mux(gpio0_22_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
}
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9ae88c5..1b60b8f 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -202,12 +202,12 @@ int board_eth_init(bd_t *bis)
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
- mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = mac_lo & 0xFF;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[5] = mac_lo & 0xFF;
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 0b76a77..140ad71 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -95,9 +95,9 @@ void sdram_init(void)
{
config_dmm(&evm_lisa_map_regs);
- config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+ config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif0_regs, 0);
- config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+ config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif1_regs, 1);
}
#endif
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index a53859e..b6bf162 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -191,22 +191,26 @@ void sdram_init(void)
if (CONFIG_TI816X_USE_EMIF0) {
ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+ config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+ 0);
}
if (CONFIG_TI816X_USE_EMIF1) {
ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+ config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+ 1);
}
#endif
#ifdef CONFIG_TI816X_EVM_DDR3
if (CONFIG_TI816X_USE_EMIF0)
- config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+ config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+ 0);
if (CONFIG_TI816X_USE_EMIF1)
- config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+ config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+ 1);
#endif
}
#endif /* CONFIG_SPL_BUILD */
diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000..1ac0aec
--- /dev/null
+++ b/board/udoo/1066mhz_4x256mx16.cfg
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+
+DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg
new file mode 100644
index 0000000..9cd1af1
--- /dev/null
+++ b/board/udoo/clocks.cfg
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg
new file mode 100644
index 0000000..78cbe17
--- /dev/null
+++ b/board/udoo/ddr-setup.cfg
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index e9d6375..e9236d4 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -9,15 +9,20 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
+#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -40,24 +48,117 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
- MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D19__GPIO_3_19,
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO3_IO19,
+};
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /*
+ * Bug: Apparently uDoo does not works with Gigabit switches...
+ * Limiting speed to 10/100Mbps, and setting master mode, seems to
+ * be the only way to have a successfull PHY auto negotiation.
+ * How to fix: Understand why Linux kernel do not have this issue.
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+ return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* RGMII reset */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Ethernet power supply */
+ MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+static iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ udelay(20);
+ gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
+
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
+
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+ udelay(1000);
+
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
+
+ /* Need 100ms delay to exit from reset. */
+ udelay(1000 * 100);
+
+ gpio_free(IMX_GPIO_NR(6, 24));
+ gpio_free(IMX_GPIO_NR(6, 25));
+ gpio_free(IMX_GPIO_NR(6, 27));
+ gpio_free(IMX_GPIO_NR(6, 28));
+ gpio_free(IMX_GPIO_NR(6, 29));
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
@@ -68,6 +169,7 @@ static void setup_iomux_wdog(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
+ gpio_direction_input(WDT_TRG);
}
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
@@ -77,6 +179,37 @@ int board_mmc_getcd(struct mmc *mmc)
return 1; /* Always present */
}
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan phy 4,5,6,7 */
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+
+ if (!phydev) {
+ free(bus);
+ return 0;
+ }
+ printf("using phy at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+#endif
+ return 0;
+}
+
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
@@ -94,11 +227,23 @@ int board_early_init_f(void)
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
return 0;
}
diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg
new file mode 100644
index 0000000..8d7ff25
--- /dev/null
+++ b/board/udoo/udoo.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 23a78c1..0043bc6 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -51,50 +51,50 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* Carrier MicroSD Card Detect */
- MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* SOM MicroSD Card Detect */
- MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
- MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
@@ -230,8 +230,10 @@ int board_video_skip(void)
ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
- if (ret)
+ if (ret) {
printf("HDMI cannot be configured: %d\n", ret);
+ return ret;
+ }
imx_enable_hdmi_phy();
@@ -263,7 +265,7 @@ int board_eth_init(bd_t *bis)
if (ret)
printf("FEC MXC: %s:failed\n", __func__);
- return 0;
+ return ret;
}
int board_early_init_f(void)
diff --git a/board/xilinx/dts/zynq-microzed.dts b/board/xilinx/dts/zynq-microzed.dts
new file mode 100644
index 0000000..6da71c1
--- /dev/null
+++ b/board/xilinx/dts/zynq-microzed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx MicroZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq MicroZED Board";
+ compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc702.dts b/board/xilinx/dts/zynq-zc702.dts
new file mode 100644
index 0000000..667dc28
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc702.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC702 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZC702 Board";
+ compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc706.dts b/board/xilinx/dts/zynq-zc706.dts
new file mode 100644
index 0000000..526fc88
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc706.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC706 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZC706 Board";
+ compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/board/xilinx/dts/zynq-zc770-xm010.dts
new file mode 100644
index 0000000..8b542a1
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm010.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM010 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZC770 XM010 Board";
+ compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/board/xilinx/dts/zynq-zc770-xm012.dts
new file mode 100644
index 0000000..0379a07
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm012.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM012 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZC770 XM012 Board";
+ compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/board/xilinx/dts/zynq-zc770-xm013.dts
new file mode 100644
index 0000000..a4f9e05
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm013.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZC770 XM013 Board";
+ compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zed.dts b/board/xilinx/dts/zynq-zed.dts
new file mode 100644
index 0000000..91a5deb
--- /dev/null
+++ b/board/xilinx/dts/zynq-zed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZED Board";
+ compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5119c09..a5b9bde 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,6 +12,12 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK 0x0F
+#define ZYNQ_BM_NOR 0x02
+#define ZYNQ_BM_SD 0x05
+#define ZYNQ_BM_JTAG 0x0
+
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
@@ -59,6 +65,25 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+ switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+ case ZYNQ_BM_NOR:
+ setenv("modeboot", "norboot");
+ break;
+ case ZYNQ_BM_SD:
+ setenv("modeboot", "sdboot");
+ break;
+ case ZYNQ_BM_JTAG:
+ setenv("modeboot", "jtagboot");
+ break;
+ default:
+ setenv("modeboot", "");
+ break;
+ }
+
+ return 0;
+}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)