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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-10-15 17:47:11 +0400
committerKumar Gala <galak@kernel.crashing.org>2009-10-27 09:44:40 -0500
commit70d665b1d230b9575a647948e8db3da1e6743e5c (patch)
tree58f5e69757562d8f3ac1d04784148f62df371180 /board
parent65dec3b4599a17e83ec69dfd059e4ea1e795ef37 (diff)
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mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boards
SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 2d07922..7d1d02e 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -154,6 +154,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 10, 2, 0, 3}, /* UART1_CTS_B */
{5, 11, 1, 0, 2}, /* UART1_RTS_B */
+ /* SPI Flash, M25P40 */
+ {4, 27, 3, 0, 1}, /* SPI_MOSI */
+ {4, 28, 3, 0, 1}, /* SPI_MISO */
+ {4, 29, 3, 0, 1}, /* SPI_CLK */
+ {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
+
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};