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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2011-08-04 02:22:20 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-09-03 22:40:44 +0200
commit6785c7c84ad6803587b247f363fe977d3e0775fb (patch)
tree98405a7e7b9728bc81e0986e516988804ff08e0e /board
parent0cb77bfa7a828f7d62eb92e03861d4fcb4d8226d (diff)
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sbc35_a9g20: update board to the new AT91 organization
Cc: Albin Tonnerre <tonnerrealbin@gmail.com> Cc: Gregory Hermant <gregory.hermant@calao-systems.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de> Removed SBC35 from MAKEALL
Diffstat (limited to 'board')
-rw-r--r--board/calao/sbc35_a9g20/sbc35_a9g20.c88
1 files changed, 45 insertions, 43 deletions
diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c
index 9df45c0..5f448d9 100644
--- a/board/calao/sbc35_a9g20/sbc35_a9g20.c
+++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -26,15 +26,14 @@
*/
#include <common.h>
-#include <asm/arch/at91sam9260.h>
+#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@@ -50,33 +49,36 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void sbc35_a9g20_nand_hw_init(void)
{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -89,10 +91,13 @@ static void sbc35_a9g20_nand_hw_init(void)
#ifdef CONFIG_MACB
static void sbc35_a9g20_macb_hw_init(void)
{
- unsigned long rstc;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+ struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+ unsigned long erstl;
- /* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+ /* Enable EMAC clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
/*
* Disable pull-up on:
@@ -111,24 +116,23 @@ static void sbc35_a9g20_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
pin_to_mask(AT91_PIN_PA28),
- pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ &pioa->pudr);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0D << 8)) |
- AT91_RSTC_URSTEN);
+ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+ AT91_RSTC_MR_URSTEN, &rstc->mr);
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+ ;
/* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
+ &rstc->mr);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |
@@ -137,7 +141,7 @@ static void sbc35_a9g20_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
pin_to_mask(AT91_PIN_PA28),
- pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+ &pioa->puer);
at91_macb_hw_init();
}
@@ -150,9 +154,9 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_serial_hw_init();
+ at91_seriald_hw_init();
sbc35_a9g20_nand_hw_init();
#ifdef CONFIG_ATMEL_SPI
at91_spi0_hw_init(1 << 4 | 1 << 5);
@@ -166,11 +170,9 @@ int board_init(void)
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
- return -1;
-
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
@@ -184,7 +186,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
#endif
return rc;
}