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authorWolfgang Denk <wd@denx.de>2011-01-25 21:13:04 +0100
committerWolfgang Denk <wd@denx.de>2011-01-25 21:13:04 +0100
commit5aebe3b07254d9ec8f7ae23a4525a6c535a7f858 (patch)
tree398660b7a43c39cee91c51e54678eab46aa7103d /board
parentd6a5e6d531e357dd8016141f73d370d02886a7eb (diff)
parent92966835e96af324fed574815036e481be807d04 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board')
-rw-r--r--board/freescale/corenet_ds/config.mk27
-rw-r--r--board/freescale/corenet_ds/ddr.c159
-rw-r--r--board/freescale/mpc8536ds/config.mk14
-rw-r--r--board/freescale/mpc8572ds/config.mk4
-rw-r--r--board/freescale/p1022ds/config.mk10
-rw-r--r--board/freescale/p1_p2_rdb/config.mk14
-rw-r--r--board/freescale/p1_p2_rdb/p1_p2_rdb.c4
-rw-r--r--board/freescale/p1_p2_rdb/tlb.c4
-rw-r--r--board/freescale/p2020ds/config.mk26
-rw-r--r--board/tqc/tqm85xx/sdram.c8
10 files changed, 94 insertions, 176 deletions
diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk
deleted file mode 100644
index 15bbf20..0000000
--- a/board/freescale/corenet_ds/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# P4080DS board
-#
-
-RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 85b6c78..6660b01 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -56,12 +56,14 @@ phys_size_t fixed_sdram(void)
strmhz(buf, sysinfo.freqDDRBus));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
#endif
@@ -143,6 +145,7 @@ typedef struct {
u32 datarate_mhz_high;
u32 n_ranks;
u32 clk_adjust;
+ u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
@@ -162,57 +165,61 @@ typedef struct {
/* XXX: Single rank at 800 MHz is OK. */
const board_specific_parameters_t board_specific_parameters[][30] = {
{
- /* memory controller 0 */
- /* lo| hi| num| clk| cpo|wrdata|2T */
- /* mhz| mhz|ranks|adjst| | delay| */
- { 0, 333, 4, 6, 7, 3, 0},
- {334, 400, 4, 6, 9, 3, 0},
- {401, 549, 4, 6, 11, 3, 0},
- {550, 680, 4, 1, 10, 5, 0},
- {681, 850, 4, 1, 12, 5, 0},
- {851, 1050, 4, 1, 12, 5, 0},
- {1051, 1250, 4, 1, 15, 4, 0},
- {1251, 1350, 4, 1, 15, 4, 0},
- { 0, 333, 2, 6, 7, 3, 0},
- {334, 400, 2, 6, 9, 3, 0},
- {401, 549, 2, 6, 11, 3, 0},
- {550, 680, 2, 1, 10, 5, 0},
- {681, 850, 2, 1, 12, 5, 0},
- {851, 1050, 2, 1, 12, 5, 0},
- {1051, 1250, 2, 1, 15, 4, 0},
- {1251, 1350, 2, 1, 15, 4, 0},
- { 0, 333, 1, 6, 7, 3, 0},
- {334, 400, 1, 6, 9, 3, 0},
- {401, 549, 1, 6, 11, 3, 0},
- {550, 680, 1, 1, 10, 5, 0},
- {681, 850, 1, 1, 12, 5, 0}
+ /*
+ * memory controller 0
+ * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
+ * mhz| mhz|ranks|adjst| start | delay|
+ */
+ { 0, 333, 4, 5, 7, 0xff, 2, 0},
+ {334, 400, 4, 5, 7, 0xff, 2, 0},
+ {401, 549, 4, 5, 7, 0xff, 2, 0},
+ {550, 680, 4, 5, 7, 0xff, 2, 0},
+ {681, 850, 4, 5, 7, 0xff, 2, 0},
+ {851, 1050, 4, 5, 7, 0xff, 2, 0},
+ {1051, 1250, 4, 5, 8, 0xff, 2, 0},
+ {1251, 1350, 4, 5, 9, 0xff, 2, 0},
+ { 0, 333, 2, 5, 7, 0xff, 2, 0},
+ {334, 400, 2, 5, 7, 0xff, 2, 0},
+ {401, 549, 2, 5, 7, 0xff, 2, 0},
+ {550, 680, 2, 5, 7, 0xff, 2, 0},
+ {681, 850, 2, 5, 7, 0xff, 2, 0},
+ {851, 1050, 2, 5, 7, 0xff, 2, 0},
+ {1051, 1250, 2, 5, 7, 0xff, 2, 0},
+ {1251, 1350, 2, 5, 7, 0xff, 2, 0},
+ { 0, 333, 1, 5, 7, 0xff, 2, 0},
+ {334, 400, 1, 5, 7, 0xff, 2, 0},
+ {401, 549, 1, 5, 7, 0xff, 2, 0},
+ {550, 680, 1, 5, 7, 0xff, 2, 0},
+ {681, 850, 1, 5, 7, 0xff, 2, 0}
},
{
- /* memory controller 1 */
- /* lo| hi| num| clk| cpo|wrdata|2T */
- /* mhz| mhz|ranks|adjst| | delay| */
- { 0, 333, 4, 6, 7, 3, 0},
- {334, 400, 4, 6, 9, 3, 0},
- {401, 549, 4, 6, 11, 3, 0},
- {550, 680, 4, 1, 10, 5, 0},
- {681, 850, 4, 1, 12, 5, 0},
- {851, 1050, 4, 1, 12, 5, 0},
- {1051, 1250, 4, 1, 15, 4, 0},
- {1251, 1350, 4, 1, 15, 4, 0},
- { 0, 333, 2, 6, 7, 3, 0},
- {334, 400, 2, 6, 9, 3, 0},
- {401, 549, 2, 6, 11, 3, 0},
- {550, 680, 2, 1, 11, 6, 0},
- {681, 850, 2, 1, 13, 6, 0},
- {851, 1050, 2, 1, 13, 6, 0},
- {1051, 1250, 2, 1, 15, 4, 0},
- {1251, 1350, 2, 1, 15, 4, 0},
- { 0, 333, 1, 6, 7, 3, 0},
- {334, 400, 1, 6, 9, 3, 0},
- {401, 549, 1, 6, 11, 3, 0},
- {550, 680, 1, 1, 11, 6, 0},
- {681, 850, 1, 1, 13, 6, 0}
+ /*
+ * memory controller 1
+ * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
+ * mhz| mhz|ranks|adjst| start | delay|
+ */
+ { 0, 333, 4, 5, 7, 0xff, 2, 0},
+ {334, 400, 4, 5, 7, 0xff, 2, 0},
+ {401, 549, 4, 5, 7, 0xff, 2, 0},
+ {550, 680, 4, 5, 7, 0xff, 2, 0},
+ {681, 850, 4, 5, 7, 0xff, 2, 0},
+ {851, 1050, 4, 5, 7, 0xff, 2, 0},
+ {1051, 1250, 4, 5, 8, 0xff, 2, 0},
+ {1251, 1350, 4, 5, 9, 0xff, 2, 0},
+ { 0, 333, 2, 5, 7, 0xff, 2, 0},
+ {334, 400, 2, 5, 7, 0xff, 2, 0},
+ {401, 549, 2, 5, 7, 0xff, 2, 0},
+ {550, 680, 2, 5, 7, 0xff, 2, 0},
+ {681, 850, 2, 5, 7, 0xff, 2, 0},
+ {851, 1050, 2, 5, 7, 0xff, 2, 0},
+ {1051, 1250, 2, 5, 7, 0xff, 2, 0},
+ {1251, 1350, 2, 5, 7, 0xff, 2, 0},
+ { 0, 333, 1, 5, 7, 0xff, 2, 0},
+ {334, 400, 1, 5, 7, 0xff, 2, 0},
+ {401, 549, 1, 5, 7, 0xff, 2, 0},
+ {550, 680, 1, 5, 7, 0xff, 2, 0},
+ {681, 850, 1, 5, 7, 0xff, 2, 0}
}
};
@@ -227,37 +234,18 @@ void fsl_ddr_board_options(memctl_options_t *popts,
u32 i;
ulong ddr_freq;
- /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i&1) { /* odd CS */
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- } else { /* even CS */
- if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
- popts->cs_local_opts[i].odt_rd_cfg = 3;
- popts->cs_local_opts[i].odt_wr_cfg = 3;
- }
- }
- }
-
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
for (i = 0; i < num_params; i++) {
if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm->n_ranks == pbsp->n_ranks) {
- popts->cpo_override = 0xff; /* force auto CPO calibration */
- popts->write_data_delay = 2;
- popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
+ ddr_freq <= pbsp->datarate_mhz_high &&
+ pdimm[0].n_ranks == pbsp->n_ranks) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
popts->twoT_en = pbsp->force_2T;
}
pbsp++;
@@ -272,17 +260,32 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* Write leveling override
*/
popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x7;
+ popts->wrlvl_sample = 0xf;
+
/*
* Rtt and Rtt_WR override
*/
- popts->rtt_override = 1;
- popts->rtt_override_value = DDR3_RTT_120_OHM;
- popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+ popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 60 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+
+ /* override SPD values. rcw_2 should vary at differnt speed */
+ if (pdimm[0].n_ranks == 4) {
+ popts->rcw_override = 1;
+ popts->rcw_1 = 0x000a5a00;
+ if (ddr_freq <= 800)
+ popts->rcw_2 = 0x00000000;
+ else if (ddr_freq <= 1066)
+ popts->rcw_2 = 0x00100000;
+ else if (ddr_freq <= 1333)
+ popts->rcw_2 = 0x00200000;
+ else
+ popts->rcw_2 = 0x00300000;
+ }
}
phys_size_t initdram(int board_type)
diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk
index b7deb4a..228d8c0 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Freescale Semiconductor.
+# Copyright 2008, 2011 Freescale Semiconductor.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -28,15 +28,3 @@ ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
-
-ifeq ($(CONFIG_SDCARD), y)
-RESET_VECTOR_ADDRESS = 0xf8fffffc
-endif
-
-ifeq ($(CONFIG_SPIFLASH), y)
-RESET_VECTOR_ADDRESS = 0xf8fffffc
-endif
-
-ifndef RESET_VECTOR_ADDRESS
-RESET_VECTOR_ADDRESS = 0xeffffffc
-endif
diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk
index 7fd6412..9fd30f9 100644
--- a/board/freescale/mpc8572ds/config.mk
+++ b/board/freescale/mpc8572ds/config.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
+# Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -28,5 +28,3 @@ ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
-
-RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk
deleted file mode 100644
index a953fdd..0000000
--- a/board/freescale/p1022ds/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2010 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the Free
-# Software Foundation; either version 2 of the License, or (at your option)
-# any later version.
-#
-
-RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk
index eececaa..0769804 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2009 Freescale Semiconductor, Inc.
+# Copyright 2009, 2011 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -29,15 +29,3 @@ ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
-
-ifeq ($(CONFIG_SDCARD), y)
-RESET_VECTOR_ADDRESS = 0xf8fffffc
-endif
-
-ifeq ($(CONFIG_SPIFLASH), y)
-RESET_VECTOR_ADDRESS = 0xf8fffffc
-endif
-
-ifndef RESET_VECTOR_ADDRESS
-RESET_VECTOR_ADDRESS = 0xeffffffc
-endif
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 440fcb9..0780942 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -222,7 +222,9 @@ void ft_board_setup(void *blob, bd_t *bd)
base = getenv_bootm_low();
size = getenv_bootm_size();
+#if defined(CONFIG_PCI)
ft_pci_board_setup(blob);
+#endif /* #if defined(CONFIG_PCI) */
fdt_fixup_memory(blob, (u64)base, (u64)size);
}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index 93d0bf7..b85c268 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_16M, 1),
+#if defined(CONFIG_PCI)
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -68,6 +69,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
+#endif /* #if defined(CONFIG_PCI) */
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/board/freescale/p2020ds/config.mk b/board/freescale/p2020ds/config.mk
deleted file mode 100644
index f5c07e5..0000000
--- a/board/freescale/p2020ds/config.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# p2020ds board
-#
-RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index b2d3185..39a9e21 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -240,7 +240,7 @@ static phys_size_t sdram_setup(int casl)
* 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
* training
*/
- ddr->debug_3 |= 0x00000400;
+ ddr->debug[2] |= 0x00000400;
/*
* 5. Wait 200 micro-seconds
@@ -282,18 +282,18 @@ static phys_size_t sdram_setup(int casl)
/*
* 8. Clear D3[21] to re-enable data training
*/
- ddr->debug_3 &= ~0x00000400;
+ ddr->debug[2] &= ~0x00000400;
/*
* 9. Set D2(21) to force data training to run
*/
- ddr->debug_2 |= 0x00000400;
+ ddr->debug[1] |= 0x00000400;
/*
* 10. Poll on D2[21] until it is cleared by hardware
*/
asm ("sync;isync;msync");
- while (ddr->debug_2 & 0x00000400)
+ while (ddr->debug[1] & 0x00000400)
asm ("eieio");
/*