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authorIngo van Lil <inguin@gmx.de>2009-11-24 14:09:21 +0100
committerWolfgang Denk <wd@denx.de>2009-12-05 01:08:53 +0100
commit3eb90bad651fab39cffba750ec4421a9c01d60e7 (patch)
tree63b21148a041603db252203a422dc465e862e016 /board
parent1c409bc7101a24ecd47a13a4e851845d66dc23ce (diff)
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Generic udelay() with watchdog support
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
Diffstat (limited to 'board')
-rw-r--r--board/armltd/integrator/timer.c2
-rw-r--r--board/freescale/mpc8313erdb/sdram.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c
index 087cf59..7562ffa 100644
--- a/board/armltd/integrator/timer.c
+++ b/board/armltd/integrator/timer.c
@@ -124,7 +124,7 @@ void set_timer (ulong ticks)
}
/* delay usec useconds */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo, tmp;
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index cb13829..0c4fd68 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -72,7 +72,7 @@ static long fixed_sdram(void)
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
- udelay(50000);
+ __udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;