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authorWolfgang Denk <wd@denx.de>2010-10-11 09:56:34 +0200
committerWolfgang Denk <wd@denx.de>2010-10-11 09:56:34 +0200
commit29840de6b6d322e9cca3d22d254a1d066afbef02 (patch)
treed73e08629803d5e11111c0e6c169acc622e1a1ba /board
parent02b117d42b1bff19b210ac258a1ef5cf58229274 (diff)
parentbfb707191a4332361f13f0fb3d99dd9986af8825 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board')
-rw-r--r--board/freescale/common/sys_eeprom.c44
-rw-r--r--board/freescale/corenet_ds/pci.c28
-rw-r--r--board/freescale/mpc8569mds/ddr.c16
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c26
-rw-r--r--board/freescale/mpc8569mds/tlb.c15
-rw-r--r--board/freescale/p1022ds/p1022ds.c67
6 files changed, 168 insertions, 28 deletions
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 3929ad0..11dfd84 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -28,13 +28,21 @@
#include <i2c.h>
#include <linux/ctype.h>
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
#include "../common/eeprom.h"
+#define MAX_NUM_PORTS 8
+#endif
-#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID)
-#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS 8
+#define NXID_VERSION 0
#endif
-#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS 23
+#define NXID_VERSION 1
+#endif
/**
* static eeprom: EEPROM layout for CCID or NXID formats
@@ -68,8 +76,8 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
- u32 crc; /* 0x72 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
+ u32 crc; /* x+1 CRC32 checksum */
#endif
} e;
@@ -204,7 +212,7 @@ static void update_crc(void)
*/
static int prog_eeprom(void)
{
- int ret = 0; /* shut up gcc */
+ int ret = 0;
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
@@ -225,6 +233,11 @@ static int prog_eeprom(void)
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
+ /*
+ * The AT24C02 datasheet says that data can only be written in page
+ * mode, which means 8 bytes at a time, and it takes up to 5ms to
+ * complete a given write.
+ */
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((sizeof(e) - i), 8));
@@ -233,12 +246,23 @@ static int prog_eeprom(void)
udelay(5000); /* 5ms write cycle timing */
}
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
+ has_been_read = 0;
return -1;
}
@@ -300,7 +324,7 @@ static void set_mac_address(unsigned int index, const char *string)
char *p = (char *) string;
unsigned int i;
- if (!string) {
+ if ((index >= MAX_NUM_PORTS) || !string) {
printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
return;
}
@@ -333,7 +357,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (cmd == 'i') {
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memcpy(e.id, "NXID", sizeof(e.id));
- e.version = 0;
+ e.version = NXID_VERSION;
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
@@ -382,8 +406,8 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
e.mac_count = simple_strtoul(argv[2], NULL, 16);
update_crc();
break;
- case '0' ... '7': /* "mac 0" through "mac 7" */
- set_mac_address(cmd - '0', argv[2]);
+ case '0' ... '9': /* "mac 0" through "mac 22" */
+ set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
break;
case 'h': /* help */
default:
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c
index 2994e36..e1bca19 100644
--- a/board/freescale/corenet_ds/pci.c
+++ b/board/freescale/corenet_ds/pci.c
@@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
+#ifdef CONFIG_PCIE4
+static struct pci_controller pcie4_hose;
+#endif
+
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[3];
+ struct fsl_pci_info pci_info[4];
u32 devdisr;
int first_free_busno = 0;
int num = 0;
@@ -119,6 +123,28 @@ void pci_init_board(void)
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
#endif
+
+#ifdef CONFIG_PCIE4
+ pcie_configured = is_serdes_configured(PCIE4);
+
+ if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
+ set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
+ LAW_TRGT_IF_PCIE_4);
+ set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCIE_4);
+ SET_STD_PCIE_INFO(pci_info[num], 4);
+ pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
+ printf(" PCIE4 connected to as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie4_hose, first_free_busno);
+ } else {
+ printf (" PCIE4: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
+#endif
}
void pci_of_setup(void *blob, bd_t *bd)
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index e938788..e3f5b4a 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts->write_data_delay = 2;
/*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
+ * Enable half drive strength
*/
- popts->half_strength_driver_enable = 0;
+ popts->half_strength_driver_enable = 1;
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x4;
+
+ /* Rtt and Rtt_W override */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_60_OHM;
+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
}
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 01b7dcb..795e565 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -27,6 +27,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
@@ -211,6 +212,31 @@ int board_early_init_f (void)
return 0;
}
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+ * Remap Boot flash to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
int checkboard (void)
{
printf ("Board: 8569 MDS\n");
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e..f852fc3 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
- * TLBe 0: 64M Non-cacheable, guarded
+ * TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
- * 0xfc000000 256K NAND FLASH (CS3)
- * 0xfe000000 32M NOR FLASH (CS0)
+ * 0xfc000000 32MB NAND FLASH (CS3)
+ * 0xfe000000 32MB NOR FLASH (CS0)
*/
+#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf8000000 32K BCSR
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 5cdee9f..ee93e8b 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -27,6 +27,7 @@
#include <asm/mp.h>
#include <netdev.h>
#include <i2c.h>
+#include <hwconfig.h>
#include "../common/ngpixis.h"
@@ -90,34 +91,58 @@ phys_size_t initdram(int board_type)
#define CONFIG_TFP410_I2C_ADDR 0x38
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+
int misc_init_r(void)
{
u8 temp;
+ const char *audclk;
+ size_t arglen;
- /* Enable the TFP410 Encoder */
+ /* For DVI, enable the TFP410 Encoder. */
temp = 0xBF;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n", temp);
temp = 0x10;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n",temp);
+ /*
+ * Enable the reference clock for the WM8776 codec, and route the MUX
+ * pins for SSI. The default is the 12.288 MHz clock
+ */
+
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ out_8(&pixis->brdcfg1, temp);
+
return 0;
}
@@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option. If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+ const char *audclk;
+ size_t arglen;
+ u32 freq;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ freq = 11289600;
+ else
+ freq = 12288000;
+
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ /* Update the WM8776 node's clock frequency property */
+ ft_codec_setup(blob, "wlf,wm8776");
}
#endif