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| author | Allen Xu <b45815@freescale.com> | 2014-02-26 15:37:12 -0600 |
|---|---|---|
| committer | Allen Xu <b45815@freescale.com> | 2014-02-27 18:08:11 -0600 |
| commit | 9a2163184a827c6520316055ce29e0a9d33c9206 (patch) | |
| tree | f40895fc5bc9fb4e223ac503f86ff60b2f2017be /board | |
| parent | ef9c7998a2598305a751e68886d859dc9d898f17 (diff) | |
| download | u-boot-imx-9a2163184a827c6520316055ce29e0a9d33c9206.zip u-boot-imx-9a2163184a827c6520316055ce29e0a9d33c9206.tar.gz u-boot-imx-9a2163184a827c6520316055ce29e0a9d33c9206.tar.bz2 | |
ENGR00301262-1 ARM: imx6sx: init for the QuadSPI
enable the clock, and set the proper PADs for the quadspi.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Allen Xu <b45815@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c index d1eea66..f78375b 100644 --- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c @@ -154,6 +154,39 @@ int board_mmc_getcd(struct mmc *mmc) return 1; /* Assume boot SD always present */ } +#ifdef CONFIG_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_34ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + /*MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),*/ + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + /*MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL2),*/ + /* just configs QSPIA */ +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(); + + return 0; +} +#endif + + #ifdef CONFIG_FSL_ESDHC int board_mmc_init(bd_t *bis) { @@ -453,6 +486,11 @@ int board_init(void) setup_fec(); #endif +#ifdef CONFIG_QSPI + board_qspi_init(); +#endif + + return 0; } |