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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-11-06 17:06:36 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2006-11-06 17:06:36 +0100 |
| commit | 91650b3e4de688038d4f71279c44858e3e2c6870 (patch) | |
| tree | 5e05ac34616bbdfe70ce7ed38e9ef6f383a12aae /board | |
| parent | ee58ea2689930669678fdcb27bf0cc5c341e18eb (diff) | |
| download | u-boot-imx-91650b3e4de688038d4f71279c44858e3e2c6870.zip u-boot-imx-91650b3e4de688038d4f71279c44858e3e2c6870.tar.gz u-boot-imx-91650b3e4de688038d4f71279c44858e3e2c6870.tar.bz2 | |
Sequential accesses to non-existent memory must be synchronized,
at least on G2 cores.
This fixes get_ram_size() problems on MPC5200 Rev. B boards.
Diffstat (limited to 'board')
| -rw-r--r-- | board/mcc200/mcc200.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 71a691b..8b475c6 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ @@ -98,6 +99,7 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -192,6 +194,23 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && + (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } |