ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR mode

On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller.
By default eSDHC is selected. However, eSDHC shows some borderline timing
in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode
at 50 MHz. Therefore, add a compile time option to uboot for MX50 to
select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port.

By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR,
is commented out in the include/configs/mx50_<board>.h file to
select eSDHC with DDR mode enabled. Uncomment the define to select
uSDHC with only SDR mode enabled.

Also increased max frequency supported by ESDHC to 52 MHz instead
of 50 MHz.

Signed-off-by: Anish Trivedi <anish@freescale.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/board/freescale/mx50_rdp/mx50_rdp.c b/board/freescale/mx50_rdp/mx50_rdp.c
index 5bac73a..133ef6a 100644
--- a/board/freescale/mx50_rdp/mx50_rdp.c
+++ b/board/freescale/mx50_rdp/mx50_rdp.c
@@ -800,6 +800,21 @@ int detect_mmc_emmc_ddr_port(struct fsl_esdhc_cfg *cfg)
 }
 #endif
 
+/* The following function enables uSDHC instead of eSDHC
+ * on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+#ifdef CONFIG_MX50_ENABLE_USDHC_SDR
+void enable_usdhc()
+{
+	/* Bring DIGCTL block out of reset and ungate clock */
+	writel(0xC0000000, DIGCTL_BASE_ADDR + 0x8);
+	/* Set bit 0 to select uSDHC */
+	writel(1, DIGCTL_BASE_ADDR + 0x4);
+}
+#endif
+
 int esdhc_gpio_init(bd_t *bis)
 {
 	s32 status = 0;