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| author | Terry Lv <r65388@freescale.com> | 2011-11-01 15:07:04 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2011-11-01 15:08:46 +0800 |
| commit | c1c2931c8e4b41e949fc1e77999b41c32f26da7b (patch) | |
| tree | a34e5d470e5c741e554655802c9eb37db6e6ae3a /board | |
| parent | 10bff02ace00c37a31d6842376f96e0cda6889c8 (diff) | |
| download | u-boot-imx-c1c2931c8e4b41e949fc1e77999b41c32f26da7b.zip u-boot-imx-c1c2931c8e4b41e949fc1e77999b41c32f26da7b.tar.gz u-boot-imx-c1c2931c8e4b41e949fc1e77999b41c32f26da7b.tar.bz2 | |
ENGR00161133: Add spi-nor support for mx6q
Add spi-nor support for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6q_arm2/mx6q_arm2.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/board/freescale/mx6q_arm2/mx6q_arm2.c b/board/freescale/mx6q_arm2/mx6q_arm2.c index 54873f3..4e1cc73 100644 --- a/board/freescale/mx6q_arm2/mx6q_arm2.c +++ b/board/freescale/mx6q_arm2/mx6q_arm2.c @@ -35,6 +35,10 @@ #include <lcd.h> #endif +#ifdef CONFIG_IMX_ECSPI +#include <imx_spi.h> +#endif + #if CONFIG_I2C_MXC #include <i2c.h> #endif @@ -336,6 +340,70 @@ void setup_lvds_poweron(void) #endif #endif +#ifdef CONFIG_IMX_ECSPI +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* SPI-NOR */ + dev->base = ECSPI1_BASE_ADDR; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 0; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + case 1: + /* SPI-NOR */ + dev->base = ECSPI1_BASE_ADDR; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 1; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID!\n"); + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + u32 reg; + + switch (dev->base) { + case ECSPI1_BASE_ADDR: + /* Enable clock */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR1); + reg |= 0x3; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR1); + + /* SCLK */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D16__ECSPI1_SCLK); + + /* MISO */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D17__ECSPI1_MISO); + + /* MOSI */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D18__ECSPI1_MOSI); + + if (dev->ss == 0) + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_EB2__ECSPI1_SS0); + else if (dev->ss == 1) + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D19__ECSPI1_SS1); + break; + case ECSPI2_BASE_ADDR: + case ECSPI3_BASE_ADDR: + /* ecspi2-3 fall through */ + break; + default: + break; + } +} +#endif + #define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10) #ifdef CONFIG_MXC_FEC |