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| author | Lily Zhang <r58066@freescale.com> | 2009-12-19 16:48:58 +0800 |
|---|---|---|
| committer | Lily Zhang <r58066@freescale.com> | 2009-12-19 16:48:58 +0800 |
| commit | e9ff0d26c61f8999a3f48b78538eae0b072ce4c6 (patch) | |
| tree | ec270f92bfdb989083767b926fe7006f6010d9ec /board | |
| parent | 97a1b233ef3d7cb7d01a6d4da06ea61c5e83e35f (diff) | |
| download | u-boot-imx-e9ff0d26c61f8999a3f48b78538eae0b072ce4c6.zip u-boot-imx-e9ff0d26c61f8999a3f48b78538eae0b072ce4c6.tar.gz u-boot-imx-e9ff0d26c61f8999a3f48b78538eae0b072ce4c6.tar.bz2 | |
ENGR00119505 MX51 BBG: Change DDR2 settings
1. Change the drive strength of DRAM PAD as high
2. Change ESDCFG setting
Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx51_bbg/flash_header.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/mx51_bbg/flash_header.S b/board/freescale/mx51_bbg/flash_header.S index 17a5c59..2f860b8 100644 --- a/board/freescale/mx51_bbg/flash_header.S +++ b/board/freescale/mx51_bbg/flash_header.S @@ -65,17 +65,17 @@ MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) /* Set drive strength to MAX */ -MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6) -MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6) -MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6) -MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6) +MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4) +MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4) +MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4) +MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4) /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ /* CAS=3, BL=4 */ MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) -MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) -MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) +MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333584ab) +MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333584ab) /* Init DRAM on CS0 */ MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) |