Add support for TB5200 board

The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006

Some code cleanup

19 files changed, 314 insertions, 210 deletions

diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index 9c7afb2..e698b20 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -30,7 +30,7 @@
 #include <asm/byteorder.h>
 
 extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, 
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
 		int flag, int argc, char *argv[]);
 
 extern int cmd_get_data_size(char* arg, int default_size);
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index c5a2e31..15b8a46 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -1004,7 +1004,7 @@ unsigned long flash_init(void)
 		}
 	} /*else if (index == 0) {*/
 /*		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/*			index = 8;*//* sram below op code flash -> new index 8*/
+/*			index = 8;*/ /* sram below op code flash -> new index 8*/
 /*	}*/
 
 	DEBUGF("\n");
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index 8cf2636..cb28936 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -102,4 +102,3 @@ tlbtab:
 	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
-
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 1ae3a54..ce1312c 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -1094,4 +1094,3 @@ unsigned long ppcMfsdr(unsigned long sdr_reg)
 
 	return (sdr_value);
 }
-
diff --git a/board/gth2/config.mk b/board/gth2/config.mk
index 6d21ba1..2bc1338 100644
--- a/board/gth2/config.mk
+++ b/board/gth2/config.mk
@@ -39,4 +39,3 @@ TEXT_BASE = 0x90000000
 endif
 endif
 endif
-
diff --git a/board/gth2/ee_access.c b/board/gth2/ee_access.c
index e293139..d4798c4 100644
--- a/board/gth2/ee_access.c
+++ b/board/gth2/ee_access.c
@@ -8,7 +8,7 @@
    For documentaion, see data sheet for DS2438, 2438.pdf
 
    By Thomas.Lange@corelatus.com 001025
-   
+
    Copyright (C) 2000-2005 Corelatus AB */
 
 /* This program is free software; you can redistribute it and/or
@@ -105,7 +105,7 @@ static u8 make_new_crc( u8 Old_crc, u8 New_value ){
 	/* Compute a new checksum with new byte, using previous checksum as input
 	   See DS app note 17, understanding and using cyclic redundancy checks...
 	   Also see DS2438, page 11 */
-	return( crc_lookup[Old_crc ^ New_value ]); 
+	return( crc_lookup[Old_crc ^ New_value ]);
 }
 
 int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
@@ -119,16 +119,16 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
 		Curr_byte++;
 	}
 	E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
-  
+
 	if(Curr_crc == Crc){
-		/* Good */ 
+		/* Good */
 		return(TRUE);
 	}
 	printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
 	return(FALSE);
 }
 
-static void 
+static void
 set_idle(void){
 	/* Send idle and keep start time
 	   Continous 1 is idle */
@@ -136,7 +136,7 @@ set_idle(void){
 }
 
 
-static int 
+static int
 do_cpu_reset(void){
 	/* Release reset and verify that chip responds with presence pulse */
 	int Retries=0;
@@ -146,10 +146,10 @@ do_cpu_reset(void){
 		/* Send reset */
 		WRITE_PORT(0);
 		udelay(RESET_LOW_TIME);
-    
+
 		/* Release reset */
 		WRITE_PORT(1);
-    
+
 		/* Wait for EEPROM to drive output */
 		udelay(PRESENCE_TIMEOUT);
 		if(!READ_PORT){
@@ -166,17 +166,17 @@ do_cpu_reset(void){
 	}
 
 	printk(KERN_ERR"eeprom did not respond when releasing reset\n");
-    
+
 	/* Make sure chip releases pin */
 	udelay(PRESENCE_LOW_TIME);
 
 	/* Set to idle again */
 	set_idle();
- 
+
 	return(-EIO);
 }
 
-static u8 
+static u8
 read_cpu_byte(void){
 	/* Read a single byte from EEPROM
 	   Read LSb first */
@@ -186,36 +186,36 @@ read_cpu_byte(void){
 	u32 Flags;
 
 	E_DEBUG("Reading byte\n");
-  
+
 	for(i=0;i<8;i++){
 		/* Small delay between pulses */
 		udelay(1);
 
-#ifdef __KERNEL__  
-		/* Disable irq */ 
+#ifdef __KERNEL__
+		/* Disable irq */
 		save_flags(Flags);
 		cli();
-#endif    
+#endif
 
 		/* Pull down pin short time to start read
 		   See page 26 in data sheet */
-    
+
 		WRITE_PORT(0);
 		udelay(READ_LOW);
 		WRITE_PORT(1);
-        
+
 		/* Wait for chip to drive pin */
 		udelay(READ_TIMEOUT);
-    
+
 		Value = READ_PORT;
 		if(Value)
 			Value=1;
 
 #ifdef __KERNEL__
-		/* Enable irq */ 
+		/* Enable irq */
 		restore_flags(Flags);
 #endif
-    
+
 		/* Wait for chip to release pin */
 		udelay(TOTAL_READ_LOW-READ_TIMEOUT);
 
@@ -230,30 +230,30 @@ read_cpu_byte(void){
 	return(Result);
 }
 
-static void 
+static void
 write_cpu_byte(u8 Byte){
 	/* Write a single byte to EEPROM
 	   Write LSb first */
 	int i;
 	int Value;
 	u32 Flags;
-  
+
 	E_DEBUG("Writing byte 0x%x\n",Byte);
-  
+
 	for(i=0;i<8;i++){
 		/* Small delay between pulses */
 		udelay(1);
 		Value = Byte&1;
-    
+
 #ifdef __KERNEL__
-		/* Disable irq */ 
+		/* Disable irq */
 		save_flags(Flags);
 		cli();
-#endif    
+#endif
 
 		/* Pull down pin short time for a 1, long time for a 0
 		   See page 26 in data sheet */
-    
+
 		WRITE_PORT(0);
 		if(Value){
 			/* Write a 1 */
@@ -267,54 +267,54 @@ write_cpu_byte(u8 Byte){
 		WRITE_PORT(1);
 
 #ifdef __KERNEL__
-		/* Enable irq */ 
+		/* Enable irq */
 		restore_flags(Flags);
 #endif
 
 		if(Value)
 			/* Wait for chip to read the 1 */
 			udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
-        
+
 		/* E_DEBUG("Wrote %d\n",Value); */
 		Byte>>=1;
 	}
 }
 
 int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
-	/* Execute this command string, including 
+	/* Execute this command string, including
 	   giving reset and setting to idle after command
-	   if Rx_len is set, we read out data from EEPROM */ 
+	   if Rx_len is set, we read out data from EEPROM */
 	int i;
 
 	E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
-  
+
 	if(do_cpu_reset()){
 		/* Failed! */
 		return(-EIO);
 	}
 
 	if(Send_skip)
-		/* Always send SKIP_ROM first to tell chip we are sending a command, 
+		/* Always send SKIP_ROM first to tell chip we are sending a command,
 		   except when we read out rom data for chip */
 		write_cpu_byte(SKIP_ROM);
-  
+
 	/* Always have Tx data */
 	for(i=0;i<Tx_len;i++){
 		write_cpu_byte(Tx[i]);
 	}
-  
+
 	if(Rx_len){
 		for(i=0;i<Rx_len;i++){
 			Rx[i]=read_cpu_byte();
 		}
 	}
-  
+
 	set_idle();
 
 	E_DEBUG("Command done\n");
 
 	return(0);
-} 
+}
 
 int ee_init_cpu_data(void){
 	int i;
@@ -323,7 +323,7 @@ int ee_init_cpu_data(void){
 	/* Leave it floting since altera is driving the same pin */
 	set_idle();
 
-	/* Copy all User EEPROM data to scratchpad */ 
+	/* Copy all User EEPROM data to scratchpad */
 	for(i=0;i<USER_PAGES;i++){
 		Tx[0]=RECALL_MEMORY;
 		Tx[1]=EE_USER_PAGE_0+i;
@@ -332,16 +332,16 @@ int ee_init_cpu_data(void){
 
 	/* Make sure chip doesnt store measurements in NVRAM */
 	Tx[0]=WRITE_SCRATCHPAD;
-	Tx[1]=0; /* Page */ 
+	Tx[1]=0; /* Page */
 	Tx[2]=9;
 	if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
 
 	Tx[0]=COPY_SCRATCHPAD;
 	if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
-  
+
 	for(i=0;i<10;i++){
 		udelay(1000);
 	}
-  
+
 	return(0);
 }
diff --git a/board/gth2/ee_access.h b/board/gth2/ee_access.h
index c21730e..926199d 100644
--- a/board/gth2/ee_access.h
+++ b/board/gth2/ee_access.h
@@ -21,7 +21,7 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
 #define EE_BUSY  0x40000000
 #define EE_ERROR 0x20000000
 
-/* Commands */ 
+/* Commands */
 #define EE_CMD_NOP      0
 #define EE_CMD_INIT_RES 1
 #define EE_CMD_WR_BYTE  2
diff --git a/board/gth2/ee_dev.h b/board/gth2/ee_dev.h
index acc3418..89ef2f8 100644
--- a/board/gth2/ee_dev.h
+++ b/board/gth2/ee_dev.h
@@ -21,7 +21,7 @@
 #ifndef INCeedevh
 #define INCeedevh
 
-#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) 
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
 
 /* MIPS */
 #define WRITE_PORT(Value) write_gpio_data(Value)
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 77fc5b4..ffeaf58 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -61,13 +61,13 @@ void init_log_serial(void){
 	u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
 
 	/* Copy buffer from last run */
-	memcpy(serial_log_buffer + 4096, 
-	       serial_log_buffer, 
+	memcpy(serial_log_buffer + 4096,
+	       serial_log_buffer,
 	       4096);
 
 	memset(serial_log_buffer, 0, 4096);
 
-	*serial_log_offsetp = 4;	
+	*serial_log_offsetp = 4;
 }
 
 
@@ -118,7 +118,7 @@ void set_ledcard(u32 value){
 		udelay(1);
 		*sys_outputclr = GPIO_LEDCLK;
 		udelay(1);
-		
+
 		value<<=1;
 	}
 	/* Data is enable output */
@@ -228,7 +228,7 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
 		printf ("Invalid boot count %u, setting 1\n", Count);
 		Count = 1;
 	}
-	
+
 	printf ("Boot attempt %d\n", Count);
 
 	data = (System << 8) | Count;
@@ -241,9 +241,9 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
 }
 
 static int random_system(void){
-	/* EEPROM read failed. Just try to choose one 
+	/* EEPROM read failed. Just try to choose one
 	   system release and hope it works */
-	
+
 	/* FIXME */
 	return(SYSTEM_BOOT);
 }
@@ -320,8 +320,8 @@ static void check_boot_tries (void)
 			data = *addr;
 			system = data >> 8;
 			count = data & 0xFF;
-			if ((system != SYSTEM_BOOT) & 
-			    (system != SYSTEM2_BOOT) & 
+			if ((system != SYSTEM_BOOT) &
+			    (system != SYSTEM2_BOOT) &
 			    (system != FAILSAFE_BOOT)) {
 				printf ("*** Wrong system %d\n", system);
 				system = FAILSAFE_BOOT;
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index 62e3657..983ff70 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -197,11 +197,11 @@ noCacheJump:
 
 	/* RCE2 CP Altera */
 	li	t0, MEM_STCFG2
-	li	t1, 0x00000280 /* BE, EW */ 
+	li	t1, 0x00000280 /* BE, EW */
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STTIME2
-	li	t1, 0x0303000c 
+	li	t1, 0x0303000c
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR2
@@ -210,11 +210,11 @@ noCacheJump:
 
 	/* RCE3 DP Altera */
 	li	t0, MEM_STCFG3
-	li	t1, 0x00000280 /* BE, EW */ 
+	li	t1, 0x00000280 /* BE, EW */
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STTIME3
-	li	t1, 0x0303000c 
+	li	t1, 0x0303000c
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR3
@@ -428,14 +428,14 @@ mt0:	sw	t0, 0(t0)
 	li	t0, 0x80000000
 	li	t1, 0xFFF000 /* 64 MB */
 mt1:	lw	t2, 0(t0)
-	bne	t0, t2, memhang	
+	bne	t0, t2, memhang
 	add	t1, -1
 	add	t0, 4
 	bne	t1, zero, mt1
 	nop
 	nop
 	.globl	clearmem
-clearmem:		
+clearmem:
 		/* Clear memory */
 	li	t0, 0x80000000
 	li	t1, 0xFFF000 /* 64 MB */
@@ -445,10 +445,10 @@ mtc:	sw	zero, 0(t0)
 	bne	t1, zero, mtc
 	nop
 	nop
-memtestend:		
+memtestend:
 	j	ra
 	nop
-	
-memhang:	
+
+memhang:
 	b	memhang
 	nop
diff --git a/board/ppmc7xx/config.mk b/board/ppmc7xx/config.mk
index bcb6c81..d8eac77 100644
--- a/board/ppmc7xx/config.mk
+++ b/board/ppmc7xx/config.mk
@@ -1,6 +1,6 @@
 #
 # (C) Copyright 2005
-# Richard Danter, Wind River Systems 
+# Richard Danter, Wind River Systems
 #
 # (C) Copyright 2000
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -24,10 +24,6 @@
 # MA 02111-1307 USA
 #
 
-#
-# 
-#
-
 TEXT_BASE = 0xFFF00000
 TEXT_END  = 0xFFF40000
 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c
index 1cbcadc..4be6f13 100644
--- a/board/ppmc7xx/flash.c
+++ b/board/ppmc7xx/flash.c
@@ -1,10 +1,10 @@
 /*
  * flash.c
  * -------
- * 
+ *
  * Flash programming routines for the Wind River PPMC 74xx/7xx
  * based on flash.c from the TQM8260 board.
- * 
+ *
  * By Richard Danter (richard.danter@windriver.com)
  * Copyright (C) 2005 Wind River Systems
  */
@@ -27,13 +27,13 @@ void flash_reset (void)
 {
 	unsigned long msr;
 	DWORD cmd_reset = 0x00F000F000F000F0LL;
-	
+
 	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
 		msr = get_msr ();
 		set_msr (msr | MSR_FP);
 
 		write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
-		
+
 		set_msr (msr);
 	}
 }
@@ -50,16 +50,16 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info)
 
 	/* Enable FPU */
 	msr = get_msr ();
-	set_msr (msr | MSR_FP);	
-							
+	set_msr (msr | MSR_FP);
+
 	/* Write auto-select command sequence */
 	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
 	write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
 	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
-	
+
 	/* Restore FPU */
 	set_msr (msr);
-	
+
 	/* Read manufacturer ID */
 	flashtest = *(volatile DWORD*)baseaddr;
 	switch ((int)flashtest) {
@@ -70,7 +70,7 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info)
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
 	default:
-		/* No, faulty or unknown flash */ 
+		/* No, faulty or unknown flash */
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
@@ -291,7 +291,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
 						   0x0080008000800080LL, 0x00AA00AA00AA00AALL,
 						   0x0055005500550055LL, 0x0030003000300030LL };
-	
+
 	if ((s_first < 0) || (s_first > s_last)) {
 		if (info->flash_id == FLASH_UNKNOWN) {
 			printf ("- missing\n");
@@ -319,7 +319,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	/* Enable FPU */
 	msr = get_msr();
 	set_msr ( msr | MSR_FP );
-						   
+
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 
@@ -344,7 +344,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 
 	/* Restore FPU */
 	set_msr (msr);
-	
+
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
 
@@ -373,7 +373,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
   DONE:
 	/* reset to read mode */
 	flash_reset ();
-	
+
 	printf (" done\n");
 	return 0;
 }
@@ -446,7 +446,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
 	DWORD data;
 	DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
 						   0x00A000A000A000A0LL };
-						   
+
 	for (data = 0, i = 0; i < 8; i++)
 		data = (data << 8) + *pdata++;
 
@@ -454,11 +454,11 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
 	if ((*(DWORD*)dest & data) != data) {
 		return (2);
 	}
-	
+
 	/* Enable FPU */
 	msr = get_msr();
 	set_msr( msr | MSR_FP );
-	
+
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 
@@ -473,7 +473,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
 
 	/* Restore FPU */
 	set_msr(msr);
-	
+
 	/* data polling for D7 */
 	start = get_timer (0);
 	while (*(volatile DWORD*)dest != data ) {
diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S
index e4ed7a6..99a818a 100644
--- a/board/ppmc7xx/init.S
+++ b/board/ppmc7xx/init.S
@@ -21,314 +21,314 @@ board_asm_init:
       ori    r4,r4,0x0000
       lis    r5,0xFEE0
       ori    r5,r5,0x0000
-      lis    r3,0x8000          # ADDR_00                        
+      lis    r3,0x8000          # ADDR_00
       ori    r3,r3,0x0000
       stwbrx    r3,0,r4
-      li     r3,0x1057          # VENDOR                         
+      li     r3,0x1057          # VENDOR
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_02                        
+      lis    r3,0x8000          # ADDR_02
       ori    r3,r3,0x0002
       stwbrx    r3,0,r4
-      li     r3,0x0004          # ID                             
+      li     r3,0x0004          # ID
       li    r8, 0x2
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_04                        
+      lis    r3,0x8000          # ADDR_04
       ori    r3,r3,0x0004
       stwbrx    r3,0,r4
-      li     r3,0x0006          # PCICMD                         
+      li     r3,0x0006          # PCICMD
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_06                        
+      lis    r3,0x8000          # ADDR_06
       ori    r3,r3,0x0006
       stwbrx    r3,0,r4
-      li     r3,0x00A0          # PCISTAT                        
+      li     r3,0x00A0          # PCISTAT
       li    r8, 0x2
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_08                        
+      lis    r3,0x8000          # ADDR_08
       ori    r3,r3,0x0008
       stwbrx    r3,0,r4
-      li     r3,0x10            # REVID                          
+      li     r3,0x10            # REVID
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_09                        
+      lis    r3,0x8000          # ADDR_09
       ori    r3,r3,0x0009
       stwbrx    r3,0,r4
-      li     r3,0x00            # PROGIR                         
+      li     r3,0x00            # PROGIR
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_0A                        
+      lis    r3,0x8000          # ADDR_0A
       ori    r3,r3,0x000A
       stwbrx    r3,0,r4
-      li     r3,0x00            # SUBCCODE                       
+      li     r3,0x00            # SUBCCODE
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_0B                        
+      lis    r3,0x8000          # ADDR_0B
       ori    r3,r3,0x000B
       stwbrx    r3,0,r4
-      li     r3,0x06            # PBCCR                          
+      li     r3,0x06            # PBCCR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_0C                        
+      lis    r3,0x8000          # ADDR_0C
       ori    r3,r3,0x000C
       stwbrx    r3,0,r4
-      li     r3,0x08            # PCLSR                          
+      li     r3,0x08            # PCLSR
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_0D                        
+      lis    r3,0x8000          # ADDR_0D
       ori    r3,r3,0x000D
       stwbrx    r3,0,r4
-      li     r3,0x00            # PLTR                           
+      li     r3,0x00            # PLTR
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_0E                        
+      lis    r3,0x8000          # ADDR_0E
       ori    r3,r3,0x000E
       stwbrx    r3,0,r4
-      li     r3,0x00            # HEADTYPE                       
+      li     r3,0x00            # HEADTYPE
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_0F                        
+      lis    r3,0x8000          # ADDR_0F
       ori    r3,r3,0x000F
       stwbrx    r3,0,r4
-      li     r3,0x00            # BISTCTRL                       
+      li     r3,0x00            # BISTCTRL
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_10                        
+      lis    r3,0x8000          # ADDR_10
       ori    r3,r3,0x0010
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # LMBAR                          
+      lis    r3,0x0000          # LMBAR
       ori    r3,r3,0x0008
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_14                        
+      lis    r3,0x8000          # ADDR_14
       ori    r3,r3,0x0014
       stwbrx    r3,0,r4
-      lis    r3,0xF000          # PCSRBAR                        
+      lis    r3,0xF000          # PCSRBAR
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_3C                        
+      lis    r3,0x8000          # ADDR_3C
       ori    r3,r3,0x003C
       stwbrx    r3,0,r4
-      li     r3,0x00            # ILR                            
+      li     r3,0x00            # ILR
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_3D                        
+      lis    r3,0x8000          # ADDR_3D
       ori    r3,r3,0x003D
       stwbrx    r3,0,r4
-      li     r3,0x01            # INTPIN                         
+      li     r3,0x01            # INTPIN
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_3E                        
+      lis    r3,0x8000          # ADDR_3E
       ori    r3,r3,0x003E
       stwbrx    r3,0,r4
-      li     r3,0x00            # MIN_GNT                        
+      li     r3,0x00            # MIN_GNT
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_3F                        
+      lis    r3,0x8000          # ADDR_3F
       ori    r3,r3,0x003F
       stwbrx    r3,0,r4
-      li     r3,0x00            # MAX_LAT                        
+      li     r3,0x00            # MAX_LAT
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_40                        
+      lis    r3,0x8000          # ADDR_40
       ori    r3,r3,0x0040
       stwbrx    r3,0,r4
-      li     r3,0x00            # BUSNB                          
+      li     r3,0x00            # BUSNB
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_41                        
+      lis    r3,0x8000          # ADDR_41
       ori    r3,r3,0x0041
       stwbrx    r3,0,r4
-      li     r3,0x00            # SBUSNB                         
+      li     r3,0x00            # SBUSNB
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_46                        
+      lis    r3,0x8000          # ADDR_46
       ori    r3,r3,0x0046
       stwbrx    r3,0,r4
-#      li     r3,0xE080          # PCIARB                         
-      li     r3,-0x1F80          # PCIARB                         
+#      li     r3,0xE080          # PCIARB
+      li     r3,-0x1F80          # PCIARB
       li    r8, 0x2
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_70                        
+      lis    r3,0x8000          # ADDR_70
       ori    r3,r3,0x0070
       stwbrx    r3,0,r4
-      li     r3,0x0000          # PMCR1                          
+      li     r3,0x0000          # PMCR1
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_72                        
+      lis    r3,0x8000          # ADDR_72
       ori    r3,r3,0x0072
       stwbrx    r3,0,r4
-      li     r3,0xC0            # PMCR2                          
+      li     r3,0xC0            # PMCR2
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_73                        
+      lis    r3,0x8000          # ADDR_73
       ori    r3,r3,0x0073
       stwbrx    r3,0,r4
-      li     r3,0xEF            # ODCR                           
+      li     r3,0xEF            # ODCR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_74                        
+      lis    r3,0x8000          # ADDR_74
       ori    r3,r3,0x0074
       stwbrx    r3,0,r4
-      li     r3,0x7D00          # CLKDCR                         
+      li     r3,0x7D00          # CLKDCR
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_76                        
+      lis    r3,0x8000          # ADDR_76
       ori    r3,r3,0x0076
       stwbrx    r3,0,r4
-      li     r3,0x00            # MDCR                           
+      li     r3,0x00            # MDCR
       stb    r3,0x2(r5)
       lis    r6,0xFCE0
       ori    r6,r6,0x0000       # r6 is the EUMBAR Base Address
-      lis    r3,0x8000          # ADDR_78                        
+      lis    r3,0x8000          # ADDR_78
       ori    r3,r3,0x0078
       stwbrx    r3,0,r4
-      lis    r3,0xFCE0          # EUMBBAR                        
+      lis    r3,0xFCE0          # EUMBBAR
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_80                        
+      lis    r3,0x8000          # ADDR_80
       ori    r3,r3,0x0080
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # MSADDR1                        
+      lis    r3,0xFFFF          # MSADDR1
       ori    r3,r3,0x4000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_84                        
+      lis    r3,0x8000          # ADDR_84
       ori    r3,r3,0x0084
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # MSADDR2                        
+      lis    r3,0xFFFF          # MSADDR2
       ori    r3,r3,0xFFFF
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_88                        
+      lis    r3,0x8000          # ADDR_88
       ori    r3,r3,0x0088
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EMSADDR1                       
+      lis    r3,0x0303          # EMSADDR1
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_8C                        
+      lis    r3,0x8000          # ADDR_8C
       ori    r3,r3,0x008C
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EMSADDR2                       
+      lis    r3,0x0303          # EMSADDR2
       ori    r3,r3,0x0303
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_90                        
+      lis    r3,0x8000          # ADDR_90
       ori    r3,r3,0x0090
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # EMEADDR1                       
+      lis    r3,0xFFFF          # EMEADDR1
       ori    r3,r3,0x7F3F
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_94                        
+      lis    r3,0x8000          # ADDR_94
       ori    r3,r3,0x0094
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # EMEADDR2                       
+      lis    r3,0xFFFF          # EMEADDR2
       ori    r3,r3,0xFFFF
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_98                        
+      lis    r3,0x8000          # ADDR_98
       ori    r3,r3,0x0098
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EXTEMEM1                       
+      lis    r3,0x0303          # EXTEMEM1
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_9C                        
+      lis    r3,0x8000          # ADDR_9C
       ori    r3,r3,0x009C
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EXTEMEM2                       
+      lis    r3,0x0303          # EXTEMEM2
       ori    r3,r3,0x0303
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_A0                        
+      lis    r3,0x8000          # ADDR_A0
       ori    r3,r3,0x00A0
       stwbrx    r3,0,r4
-      li     r3,0x03            # MEMBNKEN                       
+      li     r3,0x03            # MEMBNKEN
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_A3                        
+      lis    r3,0x8000          # ADDR_A3
       ori    r3,r3,0x00A3
       stwbrx    r3,0,r4
-      li     r3,0x00            # MEMPMODE                       
+      li     r3,0x00            # MEMPMODE
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_B8                        
+      lis    r3,0x8000          # ADDR_B8
       ori    r3,r3,0x00B8
       stwbrx    r3,0,r4
-      li     r3,0x00            # ECCCNT                         
+      li     r3,0x00            # ECCCNT
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_B9                        
+      lis    r3,0x8000          # ADDR_B9
       ori    r3,r3,0x00B9
       stwbrx    r3,0,r4
-      li     r3,0x00            # ECCTRG                         
+      li     r3,0x00            # ECCTRG
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_C0                        
+      lis    r3,0x8000          # ADDR_C0
       ori    r3,r3,0x00C0
       stwbrx    r3,0,r4
-      li     r3,0xFF            # ERRENR1                        
+      li     r3,0xFF            # ERRENR1
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_C1                        
+      lis    r3,0x8000          # ADDR_C1
       ori    r3,r3,0x00C1
       stwbrx    r3,0,r4
-      li     r3,0x00            # ERRDR1                         
+      li     r3,0x00            # ERRDR1
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_C3                        
+      lis    r3,0x8000          # ADDR_C3
       ori    r3,r3,0x00C3
       stwbrx    r3,0,r4
-      li     r3,0x50            # IPBESR                         
+      li     r3,0x50            # IPBESR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_C4                        
+      lis    r3,0x8000          # ADDR_C4
       ori    r3,r3,0x00C4
       stwbrx    r3,0,r4
-      li     r3,0xBF            # ERRENR2                        
+      li     r3,0xBF            # ERRENR2
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_C5                        
+      lis    r3,0x8000          # ADDR_C5
       ori    r3,r3,0x00C5
       stwbrx    r3,0,r4
-      li     r3,0x00            # ERRDR2                         
+      li     r3,0x00            # ERRDR2
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_C7                        
+      lis    r3,0x8000          # ADDR_C7
       ori    r3,r3,0x00C7
       stwbrx    r3,0,r4
-      li     r3,0x00            # PCIBESR                        
+      li     r3,0x00            # PCIBESR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_C8                        
+      lis    r3,0x8000          # ADDR_C8
       ori    r3,r3,0x00C8
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # BERRADDR                       
+      lis    r3,0x0000          # BERRADDR
       ori    r3,r3,0xE0FE
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_E0                        
+      lis    r3,0x8000          # ADDR_E0
       ori    r3,r3,0x00E0
       stwbrx    r3,0,r4
-      li     r3,0xC0            # AMBOR                          
+      li     r3,0xC0            # AMBOR
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_F4                        
+      lis    r3,0x8000          # ADDR_F4
       ori    r3,r3,0x00F4
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # MCCR2                          
+      lis    r3,0x0000          # MCCR2
       ori    r3,r3,0x020C
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_F8                        
+      lis    r3,0x8000          # ADDR_F8
       ori    r3,r3,0x00F8
       stwbrx    r3,0,r4
-      lis    r3,0x0230          # MCCR3                          
+      lis    r3,0x0230          # MCCR3
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_FC                        
+      lis    r3,0x8000          # ADDR_FC
       ori    r3,r3,0x00FC
       stwbrx    r3,0,r4
-      lis    r3,0x2532          # MCCR4                          
+      lis    r3,0x2532          # MCCR4
       ori    r3,r3,0x2220
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_F0                        
+      lis    r3,0x8000          # ADDR_F0
       ori    r3,r3,0x00F0
       stwbrx    r3,0,r4
-      lis    r3,0xFFC8          # MCCR1                          
+      lis    r3,0xFFC8          # MCCR1
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_A8                        
+      lis    r3,0x8000          # ADDR_A8
       ori    r3,r3,0x00A8
       stwbrx    r3,0,r4
-      lis    r3,0xFF14          # PICR1                          
+      lis    r3,0xFF14          # PICR1
       ori    r3,r3,0x1CC8
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_AC                        
+      lis    r3,0x8000          # ADDR_AC
       ori    r3,r3,0x00AC
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # PICR2                          
+      lis    r3,0x0000          # PICR2
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c
index 0597c72..402ac5e 100644
--- a/board/ppmc7xx/ppmc7xx.c
+++ b/board/ppmc7xx/ppmc7xx.c
@@ -1,9 +1,9 @@
 /*
  * ppmc7xx.c
  * ---------
- * 
+ *
  * Main board-specific routines for Wind River PPMC 7xx/74xx board.
- * 
+ *
  * By Richard Danter (richard.danter@windriver.com)
  * Copyright (C) 2005 Wind River Systems
  */
@@ -24,7 +24,7 @@ extern void _start_warm(void);
 
 /*
  * initdram()
- * 
+ *
  * This function normally initialises the (S)DRAM of the system. For this board
  * the SDRAM was already initialised by board_asm_init (see init.S) so we just
  * return the size of RAM.
@@ -37,12 +37,12 @@ long initdram( int board_type )
 
 /*
  * after_reloc()
- * 
+ *
  * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
  * us an opportunity to do some additional setup before the rest of the system
  * is initialised. We don't need to do anything, so we just call board_init_r()
  * which should never return.
- */ 
+ */
 void after_reloc( ulong dest_addr, gd_t* gd )
 {
 	/* Jump to the main U-Boot board init code */
@@ -52,7 +52,7 @@ void after_reloc( ulong dest_addr, gd_t* gd )
 
 /*
  * checkboard()
- * 
+ *
  * We could do some board level checks here, such as working out what version
  * it is, but for this board we simply display it's name (on the console).
  */
@@ -65,7 +65,7 @@ int checkboard( void )
 
 /*
  * misc_init_r
- * 
+ *
  * Used for other setup which needs to be done late in the bring-up phase.
  */
 int misc_init_r( void )
@@ -78,27 +78,27 @@ int misc_init_r( void )
 
 	/* Enable the I-Cache */
 	icache_enable();
-	
+
 	return 0;
 }
 
 
 /*
  * do_reset()
- * 
+ *
  * Shell command to reset the board.
  */
 void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 {
 	printf( "Resetting...\n" );
-	
+
 	/* Disabe and invalidate cache */
 	icache_disable();
 	dcache_disable();
 
 	/* Jump to warm start (in RAM) */
 	_start_warm();
-	
+
 	/* Should never get here */
 	while(1);
 }
diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile
index ab0ff1a..9a1ea48 100644
--- a/board/tqm5200/Makefile
+++ b/board/tqm5200/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o cmd_stk52xx.o
+OBJS	:= $(BOARD).o cmd_stk52xx.o cmd_tb5200.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c
index 8b9057f..2326a28 100755
--- a/board/tqm5200/cmd_stk52xx.c
+++ b/board/tqm5200/cmd_stk52xx.c
@@ -30,6 +30,7 @@
 #include <command.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined (CONFIG_STK52XX)
 
 #define DEFAULT_VOL	45
 #define DEFAULT_FREQ	500
@@ -60,7 +61,6 @@ static int spi_transmit(unsigned char data);
 static void pcm1772_write_reg(unsigned char addr, unsigned char data);
 static void set_attenuation(unsigned char attenuation);
 
-#ifdef CONFIG_STK52XX
 static void spi_init(void)
 {
 	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
diff --git a/board/tqm5200/cmd_tb5200.c b/board/tqm5200/cmd_tb5200.c
new file mode 100644
index 0000000..8784b1f
--- /dev/null
+++ b/board/tqm5200/cmd_tb5200.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2005 - 2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TB5200 specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined (CONFIG_TB5200)
+
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+
+static void led_init(void)
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	/* configure timer 4 for simple GPIO output */
+	gpt->gpt4.emsr |=  0x00000024;
+}
+
+int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	led_init();
+
+	if (strcmp (argv[1], "on") == 0) {
+		debug ("switch status LED on\n");
+		gpt->gpt4.emsr |=  (1 << 4);
+	} else if (strcmp (argv[1], "off") == 0) {
+		debug ("switch status LED off\n");
+		gpt->gpt4.emsr &=  ~(1 << 4);
+	} else {
+		printf ("Usage:\nled on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+	if (state == 1) {
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+			(1 << 26) | (1 << 27);
+	} else if (state == 0)
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+			~((1 << 26) | (1 << 27));
+}
+
+int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (strcmp (argv[1], "on") == 0) {
+		debug ("switch backlight on\n");
+		sm501_backlight (1);
+	} else if (strcmp (argv[1], "off") == 0) {
+		debug ("switch backlight off\n");
+		sm501_backlight (0);
+	} else {
+		printf ("Usage:\nbacklight on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	led ,	2,	1,	cmd_led,
+	"led     - switch status LED on or off\n",
+	"on/off\n"
+);
+
+U_BOOT_CMD(
+	backlight ,	2,	1,	cmd_backlight,
+	"backlight - switch backlight on or off\n",
+	"on/off\n"
+	);
+
+#endif /* CONFIG_STK52XX */
+#endif /* CFG_CMD_BSP */
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
index 310abd2..c6309e3 100644
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@@ -260,6 +260,9 @@ int checkboard (void)
 #if defined (CONFIG_STK52XX)
 	puts ("       on a STK52XX baseboard\n");
 #endif
+#if defined (CONFIG_TB5200)
+	puts ("       on a TB5200 baseboard\n");
+#endif
 
 	return 0;
 }
@@ -567,10 +570,15 @@ void video_get_info_str (int line_number, char *info)
 {
 	if (line_number == 1) {
 	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_STK52XX)
+#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
 	} else if (line_number == 2) {
+#if defined (CONFIG_STK52XX)
 		strcpy (info, "        on a STK52XX baseboard");
 #endif
+#if defined (CONFIG_TB5200)
+		strcpy (info, "        on a TB5200 baseboard");
+#endif
+#endif
 	}
 	else {
 		info [0] = '\0';
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
index befe8b7..a87affc 100644
--- a/board/tqm85xx/tqm85xx.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -423,4 +423,3 @@ int board_early_init_r (void)
 	return (0);
 }
 #endif /* CONFIG_BOARD_EARLY_INIT_R */
-