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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-10-29 13:32:59 -0400 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2008-10-29 13:08:17 -0500 |
| commit | c013b74975dab0805ef6d369b013230c4e8a660d (patch) | |
| tree | 281f4327624d9b9d9700aeacda0c62ce301ee0cd /board | |
| parent | 4e190b03aaf2309bd2e025d1187a2ca880fedc95 (diff) | |
| download | u-boot-imx-c013b74975dab0805ef6d369b013230c4e8a660d.zip u-boot-imx-c013b74975dab0805ef6d369b013230c4e8a660d.tar.gz u-boot-imx-c013b74975dab0805ef6d369b013230c4e8a660d.tar.bz2 | |
NAND: Add support for MPC8572DS board
This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns
0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in
config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to
make room for the increased code size with NAND enabled.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mpc8572ds/law.c | 1 | ||||
| -rw-r--r-- | board/freescale/mpc8572ds/tlb.c | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index 9f11902..83eb681 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -36,6 +36,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 1c5ed3f..8d1f646 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -80,6 +80,12 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |