ENGR00131705-2 Add MX53 ARD support

Add MX53 Automotive Reference Board (ARD) support
1. Add DDR2 initialization script
2. Add external ethernet support
3. Update PIN settings for UART, I2C, SDHC etc

Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>

2 files changed, 336 insertions, 6 deletions

diff --git a/board/freescale/mx53_rd/flash_header.S b/board/freescale/mx53_rd/flash_header.S
index 014333d..d6f9d81 100644
--- a/board/freescale/mx53_rd/flash_header.S
+++ b/board/freescale/mx53_rd/flash_header.S
@@ -246,5 +246,76 @@ MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x020, 0x00001800)
 MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x040, 0x04b80003)
 MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x058, 0x00022227)
 MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
+
+#elif defined(CONFIG_MX53_ARD)
+
+dcd_hdr:          .word 0x400002D2 /* Tag=0xD2, Len=63*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04FC01CC /* Tag=0xCC, Len=63*8 + 4, Param=4 */
+
+/* DCD */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00380000)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00380000)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x06000000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
+MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2b2f3031)
+MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333)
+MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800)
+MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x01310132)
+MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x0133014b)
+MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710)
+MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0x84110000)
+MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2)
+MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22)
+MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092)
+MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e)
+MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
+MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
+MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
+MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
+MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031)
+MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0)
+MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
+MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
+MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
+MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030)
+MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031)
+MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00468031)
+MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
+MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
+MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
+MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039)
+MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138)
+MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
+MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
+MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
+MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038)
+MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039)
+MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
+MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
+MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
+
 #endif
 #endif
diff --git a/board/freescale/mx53_rd/mx53_rd.c b/board/freescale/mx53_rd/mx53_rd.c
index 0f4f475..c2d549f 100644
--- a/board/freescale/mx53_rd/mx53_rd.c
+++ b/board/freescale/mx53_rd/mx53_rd.c
@@ -29,6 +29,7 @@
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <imx_spi.h>
+#include <netdev.h>
 
 #if CONFIG_I2C_MXC
 #include <i2c.h>
@@ -212,8 +213,18 @@ int dram_init(void)
 
 static void setup_uart(void)
 {
+#if defined(CONFIG_MX53_ARD)
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 0x1E4);
 
 	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+	mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 0x1E4);
+#else
+	/* MX53 EVK and ARM2 board */
+	/* UART1 RXD */
 	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
 	mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4);
 	mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
@@ -221,6 +232,7 @@ static void setup_uart(void)
 	/* UART1 TXD */
 	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
 	mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4);
+#endif
 }
 
 #ifdef CONFIG_I2C_MXC
@@ -228,6 +240,10 @@ static void setup_i2c(unsigned int module_base)
 {
 	switch (module_base) {
 	case I2C1_BASE_ADDR:
+#if defined(CONFIG_MX53_ARD)
+		/* No device is connected via I2C1 on ARD */
+		break;
+#else
 		/* i2c1 SDA */
 		mxc_request_iomux(MX53_PIN_CSI0_D8,
 				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
@@ -246,6 +262,7 @@ static void setup_i2c(unsigned int module_base)
 				PAD_CTL_ODE_OPENDRAIN_ENABLE |
 				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 				PAD_CTL_HYS_ENABLE);
+#endif
 		break;
 	case I2C2_BASE_ADDR:
 		/* i2c2 SDA */
@@ -259,6 +276,17 @@ static void setup_i2c(unsigned int module_base)
 				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 				PAD_CTL_HYS_ENABLE);
 
+#if	defined(CONFIG_MX53_ARD)
+		mxc_request_iomux(MX53_PIN_EIM_EB2,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH1);
+		mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+				PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+#else
 		/* i2c2 SCL */
 		mxc_request_iomux(MX53_PIN_KEY_COL3,
 				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
@@ -269,6 +297,32 @@ static void setup_i2c(unsigned int module_base)
 				PAD_CTL_ODE_OPENDRAIN_ENABLE |
 				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 				PAD_CTL_HYS_ENABLE);
+
+#endif
+		break;
+	case I2C3_BASE_ADDR:
+#if	defined(CONFIG_MX53_ARD)
+		/* GPIO_3 for I2C3_SCL */
+		mxc_request_iomux(MX53_PIN_GPIO_3,
+				IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH1);
+		mxc_iomux_set_pad(MX53_PIN_GPIO_3,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD |
+				PAD_CTL_HYS_ENABLE);
+		/* GPIO_16 for I2C3_SDA */
+		mxc_request_iomux(MX53_PIN_GPIO_16,
+				IOMUX_CONFIG_ALT6 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH1);
+		mxc_iomux_set_pad(MX53_PIN_GPIO_16,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD |
+				PAD_CTL_HYS_ENABLE);
+#else
+		/* No device is connected via I2C3 in EVK and ARM2 */
+#endif
 		break;
 	default:
 		printf("Invalid I2C base: 0x%x\n", module_base);
@@ -278,6 +332,7 @@ static void setup_i2c(unsigned int module_base)
 
 void setup_core_voltages(void)
 {
+#if	!defined(CONFIG_MX53_ARD)
 	unsigned char buf[4] = { 0 };
 
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
@@ -295,12 +350,12 @@ void setup_core_voltages(void)
 	buf[2] = 0x1a;
 	if (i2c_write(0x8, 26, 1, buf, 3))
 		return;
-
+#endif
 	/* Raise the core frequency to 800MHz */
 	writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 }
 
-#ifndef CONFIG_MX53_ARM2
+#ifdef CONFIG_MX53_EVK
 static int __read_adc_channel(unsigned int chan)
 {
 	unsigned char buf[4] = { 0 };
@@ -564,8 +619,8 @@ void spi_io_init(struct imx_spi_dev_t *dev)
 		mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
 		mxc_iomux_set_input(
 			MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
-
 		break;
+
 	case CSPI2_BASE_ADDR:
 	default:
 
@@ -676,13 +731,168 @@ int setup_mxc_kpd(void)
 }
 #endif
 
+#ifdef CONFIG_NET_MULTI
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+	return rc;
+}
+#endif
+
+#if defined(CONFIG_MX53_ARD)
+void weim_smc911x_iomux()
+{
+	unsigned int reg;
+
+	/* ETHERNET_INT_B as GPIO2_31 */
+	mxc_request_iomux(MX53_PIN_EIM_EB3,
+		IOMUX_CONFIG_ALT1);
+	reg = readl(GPIO2_BASE_ADDR + 0x4);
+	reg &= ~(0x80000000);
+	writel(reg, GPIO2_BASE_ADDR + 0x4);
+
+	/* Data bus */
+	mxc_request_iomux(MX53_PIN_EIM_D16,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D17,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D18,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D19,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D20,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D21,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D22,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D23,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D24,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D25,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D26,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D27,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D28,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D29,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D30,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_D31,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
+
+	/* Address lines */
+	mxc_request_iomux(MX53_PIN_EIM_DA0,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_DA1,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_DA2,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_DA3,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_DA4,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_DA5,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
+
+	mxc_request_iomux(MX53_PIN_EIM_DA6,
+		IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
+
+	/* other EIM signals for ethernet */
+	mxc_request_iomux(MX53_PIN_EIM_OE,
+		IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_EIM_RW,
+		IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_EIM_CS1,
+		IOMUX_CONFIG_ALT0);
+
+}
+
+void weim_cs1_settings()
+{
+	unsigned int reg;
+
+	writel(0x20001, (WEIM_BASE_ADDR + 0x18));
+	writel(0x0, (WEIM_BASE_ADDR + 0x1C));
+	writel(0x16000202, (WEIM_BASE_ADDR + 0x20));
+	writel(0x00000002, (WEIM_BASE_ADDR + 0x24));
+	writel(0x16002082, (WEIM_BASE_ADDR + 0x28));
+	writel(0x00000000, (WEIM_BASE_ADDR + 0x2C));
+	writel(0x00000000, (WEIM_BASE_ADDR + 0x90));
+
+	/* specify 64 MB on CS1 and CS0 */
+	reg = readl(IOMUXC_BASE_ADDR + 0x4);
+	reg &= ~0x3F;
+	reg |= 0x1B;
+	writel(reg, (IOMUXC_BASE_ADDR + 0x4));
+}
+#endif
+
 
 #ifdef CONFIG_CMD_MMC
 
+#if defined(CONFIG_MX53_ARD)
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1, 1},
+	{MMC_SDHC2_BASE_ADDR, 1, 1},
+};
+#else
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR, 1, 1},
 	{MMC_SDHC3_BASE_ADDR, 1, 1},
 };
+#endif
 
 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
 int get_mmc_env_devno()
@@ -721,6 +931,40 @@ int esdhc_gpio_init(bd_t *bis)
 			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
 			break;
 		case 1:
+#if defined(CONFIG_MX53_ARD)
+			mxc_request_iomux(MX53_PIN_SD2_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX53_PIN_SD2_CLK,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX53_PIN_SD2_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD2_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD2_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD2_DATA3,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_ATA_DATA12,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA13,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA14,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA15,
+						IOMUX_CONFIG_ALT2);
+
+			mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
+			mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
+			mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
+
+#else
 			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 						IOMUX_CONFIG_ALT2);
 			mxc_request_iomux(MX53_PIN_ATA_IORDY,
@@ -752,7 +996,7 @@ int esdhc_gpio_init(bd_t *bis)
 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
-
+#endif
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
@@ -791,18 +1035,29 @@ int board_init(void)
 #if defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
 	setup_board_rev(1);
 #endif
+
+#if defined(CONFIG_MX53_ARD)
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD;
+#else
 	gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;	/* board id for linux */
+#endif
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
 	setup_uart();
+#ifdef CONFIG_MXC_FEC
 	setup_fec();
+#endif
 
 #ifdef CONFIG_I2C_MXC
 	setup_i2c(CONFIG_SYS_I2C_PORT);
 	setup_core_voltages();
 #endif
 
+#if defined(CONFIG_MX53_ARD)
+	weim_smc911x_iomux();
+	weim_cs1_settings();
+#endif
 	return 0;
 }
 
@@ -936,15 +1191,19 @@ int checkboard(void)
 {
 	printf("Board: ");
 
-#ifdef CONFIG_MX53_ARM2
+#if defined(CONFIG_MX53_ARD)
+	printf("MX53-ARD 1.0 [");
+#elif defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
 	printf("Board: MX53 ARMADILLO2 ");
 	printf("1.0 [");
-#else
+#elif defined(CONFIG_MX53_EVK)
 #ifdef CONFIG_I2C_MXC
 	identify_board_id();
 
 	printf("Boot Reason: [");
 #endif
+#else
+	# error "Unknown board config!"
 #endif
 
 	switch (__REG(SRC_BASE_ADDR + 0x8)) {