ENGR00123641 MX53: Add DDR3 CPU board support

Add DDR3 CPU board support, DDR3 clock 400Mhz
Create one config file for it since the DDR3 init
script is much different wtih DDR2.

Signed-off-by:Jason Liu <r64343@freescale.com>

2 files changed, 59 insertions, 3 deletions

diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S
index 8d23242..014333d 100644
--- a/board/freescale/mx53_evk/flash_header.S
+++ b/board/freescale/mx53_evk/flash_header.S
@@ -52,7 +52,7 @@ boot_data:        .word 0x77800000
 image_len:        .word _end - TEXT_BASE
 plugin:           .word 0x0
 
-#ifdef CONFIG_MX53_EVK
+#if defined(CONFIG_MX53_EVK)
 dcd_hdr:          .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */
 
@@ -122,7 +122,7 @@ MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
 MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
 MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
 
-#else /*ARM2 board*/
+#elif defined(CONFIG_MX53_ARM2) /*ARM2 board*/
 dcd_hdr:          .word 0x400002D2 /* Tag=0xD2, Len=63*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x04FC01CC /* Tag=0xCC, Len=63*8 + 4, Param=4 */
 
@@ -190,5 +190,61 @@ MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
 MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
 MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
 MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
+#elif defined(CONFIG_MX53_ARM2_DDR3)
+dcd_hdr:          .word 0x40A001D2 /* Tag=0xD2, Len=51*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x049C01CC /* Tag=0xCC, Len=51*8 + 4, Param=4 */
+
+/* DCD */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00300000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00300040)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00300000)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00300040)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00300040)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00300000)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00300000)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00300000)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00300040)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00300040)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00300000)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00300000)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00300040)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00300000)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00300000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000000)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00300000)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00300000)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00300000)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x04000000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00300000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00300000)
+MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x32383535)
+MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40383538)
+MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x07c, 0x0136014d)
+MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x080, 0x01510141)
+MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x018, 0x00091740)
+MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x000, 0xc4190000)
+MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x00c, 0x565a7543)
+MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x010, 0xb6ae8aa3)
+MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x014, 0x01ff00db)
+MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x030, 0x009f0e21)
+MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
+MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
+MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
+MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00028031)
+MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x092080b0)
+MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
+MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
+MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00028039)
+MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x09208138)
+MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x04008048)
+MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x020, 0x00001800)
+MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x040, 0x04b80003)
+MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x058, 0x00022227)
+MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
 #endif
 #endif
diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
index 98d5938..2741088 100644
--- a/board/freescale/mx53_evk/mx53_evk.c
+++ b/board/freescale/mx53_evk/mx53_evk.c
@@ -684,7 +684,7 @@ int board_init(void)
 {
 	setup_boot_device();
 	setup_soc_rev();
-#ifdef CONFIG_MX53_ARM2
+#if defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
 	setup_board_rev(1);
 #endif
 	gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;	/* board id for linux */