Some code cleanup

3 files changed, 18 insertions, 18 deletions

diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 4197a7c..4f056b2 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -187,17 +187,17 @@ long int initdram (int board_type)
 #endif /* CFG_RAMBOOT */
 
 	/*
-	 * On MPC5200B we need to set the special configuration delay in the 
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM 
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is 
-	 * required to account for changes caused by normal wafer processing 
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
 	 * parameters."
-	 */ 
+	 */
 	svr = get_svr();
 	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) && 
+	if ((SVR_MJREV(svr) >= 2) &&
 	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 
 		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index 73a33f6..7ece7db 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -116,14 +116,14 @@ int fixed_sdram(void)
 	im->ddr.csbnds[2].csbnds = 0x0000000f;
 	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
 
-	/* currently we use only one CS, so disable the other banks */ 
+	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
 	im->ddr.cs_config[1] = 0;
 	im->ddr.cs_config[3] = 0;
 
 	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	
+
 	im->ddr.sdram_cfg =
 		SDRAM_CFG_SREN
 #if defined(CONFIG_DDR_2T_TIMING)
@@ -136,7 +136,7 @@ int fixed_sdram(void)
 #endif
 	im->ddr.sdram_mode = CFG_DDR_MODE;
 
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL; 
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 	udelay(200);
 
 	/* enable DDR controller */
@@ -361,12 +361,12 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	volatile u32 val;
 	u64 *addr, count, val64;
 	register u64 *i;
-	
+
 	if (argc > 4) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
-	
+
 	if (argc == 2) {
 		if (strcmp(argv[1], "status") == 0) {
 			ecc_print_status();
@@ -379,8 +379,8 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			ddr->capture_attributes = 0;
 			return 0;
 		}
-	} 
-	
+	}
+
 	if (argc == 3) {
 		if (strcmp(argv[1], "sbecnt") == 0) {
 			val = simple_strtoul(argv[2], NULL, 10);
@@ -416,8 +416,8 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			} else if (strcmp(argv[2], "+mse") == 0) {
 				val |= ECC_ERROR_DISABLE_MSED;
 			} else if (strcmp(argv[2], "+all") == 0) {
-				val |= (ECC_ERROR_DISABLE_SBED | 
-					ECC_ERROR_DISABLE_MBED | 
+				val |= (ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
 					ECC_ERROR_DISABLE_MSED);
 			} else if (strcmp(argv[2], "-sbe") == 0) {
 				val &= ~ECC_ERROR_DISABLE_SBED;
@@ -426,8 +426,8 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			} else if (strcmp(argv[2], "-mse") == 0) {
 				val &= ~ECC_ERROR_DISABLE_MSED;
 			} else if (strcmp(argv[2], "-all") == 0) {
-				val &= ~(ECC_ERROR_DISABLE_SBED | 
-					ECC_ERROR_DISABLE_MBED | 
+				val &= ~(ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
 					ECC_ERROR_DISABLE_MSED);
 			} else {
 				printf("Incorrect err_disable field\n");
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index 913f95c..abf2fd5 100644
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -85,7 +85,7 @@ int board_init (void)
 
 	GPCR = 0x000003AB;	/* I/O pad driving strength     */
 
-	/*	MX1_CS1U 	= 0x00000A00;	*//* SRAM initialization          */
+	/*	MX1_CS1U 	= 0x00000A00;	*/ /* SRAM initialization          */
 /*	MX1_CS1L 	= 0x11110601; 	*/
 
 	MPCTL0 = 0x04632410;	/* setting for 150 MHz MCU PLL CLK      */