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authorStefan Roese <sr@denx.de>2008-01-05 09:12:41 +0100
committerStefan Roese <sr@denx.de>2008-01-05 09:12:41 +0100
commit845c6c95dbfe6c915ce68a0a115852fa17932fb4 (patch)
treeb935ef67e63cae739a497daf7e70869653c1b2cb /board
parent5c740711f0ea5b51414b341b71597c4a0751be74 (diff)
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ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup
On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
-rw-r--r--board/amcc/katmai/katmai.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 25c9a22..e41caaf 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -246,6 +246,18 @@ int checkboard (void)
return 0;
}
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_wrdtr(u32 default_val) {
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+
#if defined(CFG_DRAM_TEST)
int testdram (void)
{