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| author | Terry Lv <r65388@freescale.com> | 2011-08-24 16:15:47 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2011-09-01 13:57:21 +0800 |
| commit | 7db399587fe4cd8d0e77491e9b2fad47c0a82be2 (patch) | |
| tree | 7c4b34e73aff3607eb7dec6ea522203da355f5b3 /board | |
| parent | ea7a4199586b4b9cd9a4e13c0e420a4e1699a297 (diff) | |
| download | u-boot-imx-7db399587fe4cd8d0e77491e9b2fad47c0a82be2.zip u-boot-imx-7db399587fe4cd8d0e77491e9b2fad47c0a82be2.tar.gz u-boot-imx-7db399587fe4cd8d0e77491e9b2fad47c0a82be2.tar.bz2 | |
ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHz
1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz.
2. When dpgdck0_2_en is 0, the formula to calculate output freq
will be changed to 2 * freq * [].
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx53_ard/lowlevel_init.S | 9 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/lowlevel_init.S | 9 | ||||
| -rw-r--r-- | board/freescale/mx53_loco/lowlevel_init.S | 9 | ||||
| -rw-r--r-- | board/freescale/mx53_pcba/lowlevel_init.S | 9 | ||||
| -rw-r--r-- | board/freescale/mx53_smd/lowlevel_init.S | 12 |
5 files changed, 42 insertions, 6 deletions
diff --git a/board/freescale/mx53_ard/lowlevel_init.S b/board/freescale/mx53_ard/lowlevel_init.S index 2a251f7..f8e7632 100644 --- a/board/freescale/mx53_ard/lowlevel_init.S +++ b/board/freescale/mx53_ard/lowlevel_init.S @@ -58,8 +58,15 @@ .endm /* init_aips */ .macro setup_pll pll, freq + /* + * If freq < 300MHz, we need to set dpdck0_2_en to 0 + */ + ldr r0, =\freq + ldr r1, =0x300 + cmp r0, r1 + ldrcs r1, =0x00001232 + ldrcc r1, =0x00000232 ldr r0, =\pll - ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S index 0122353..b52e518 100644 --- a/board/freescale/mx53_evk/lowlevel_init.S +++ b/board/freescale/mx53_evk/lowlevel_init.S @@ -58,8 +58,15 @@ .endm /* init_aips */ .macro setup_pll pll, freq + /* + * If freq < 300MHz, we need to set dpdck0_2_en to 0 + */ + ldr r0, =\freq + ldr r1, =0x300 + cmp r0, r1 + ldrcs r1, =0x00001232 + ldrcc r1, =0x00000232 ldr r0, =\pll - ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] diff --git a/board/freescale/mx53_loco/lowlevel_init.S b/board/freescale/mx53_loco/lowlevel_init.S index ff879a6..dbcb074 100644 --- a/board/freescale/mx53_loco/lowlevel_init.S +++ b/board/freescale/mx53_loco/lowlevel_init.S @@ -56,8 +56,15 @@ .endm /* init_aips */ .macro setup_pll pll, freq + /* + * If freq < 300MHz, we need to set dpdck0_2_en to 0 + */ + ldr r0, =\freq + ldr r1, =0x300 + cmp r0, r1 + ldrcs r1, =0x00001232 + ldrcc r1, =0x00000232 ldr r0, =\pll - ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] diff --git a/board/freescale/mx53_pcba/lowlevel_init.S b/board/freescale/mx53_pcba/lowlevel_init.S index 6a95a21..f9b1f11 100644 --- a/board/freescale/mx53_pcba/lowlevel_init.S +++ b/board/freescale/mx53_pcba/lowlevel_init.S @@ -56,8 +56,15 @@ .endm /* init_aips */ .macro setup_pll pll, freq + /* + * If freq < 300MHz, we need to set dpdck0_2_en to 0 + */ + ldr r0, =\freq + ldr r1, =0x300 + cmp r0, r1 + ldrcs r1, =0x00001232 + ldrcc r1, =0x00000232 ldr r0, =\pll - ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] diff --git a/board/freescale/mx53_smd/lowlevel_init.S b/board/freescale/mx53_smd/lowlevel_init.S index 07af735..8aef8b2 100644 --- a/board/freescale/mx53_smd/lowlevel_init.S +++ b/board/freescale/mx53_smd/lowlevel_init.S @@ -56,8 +56,15 @@ .endm /* init_aips */ .macro setup_pll pll, freq + /* + * If freq < 300MHz, we need to set dpdck0_2_en to 0 + */ + ldr r0, =\freq + ldr r1, =0x12c + cmp r0, r1 + ldrcs r1, =0x00001232 + ldrcc r1, =0x00000232 ldr r0, =\pll - ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] @@ -74,7 +81,8 @@ str r1, [r0, #PLL_DP_MFN] str r1, [r0, #PLL_DP_HFS_MFN] - ldr r1, =0x00001232 + ldrcs r1, =0x00001232 + ldrcc r1, =0x00000232 str r1, [r0, #PLL_DP_CTL] 1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 |