diff options
author | <m8@hekate.semihalf.com> | 2005-08-16 17:34:22 +0200 |
---|---|---|
committer | <m8@hekate.semihalf.com> | 2005-08-16 17:34:22 +0200 |
commit | 22e05df45cc343eda3266312bde676737d9bc70c (patch) | |
tree | 6f2209c6675e79d000e359725872a3ba15262140 /board | |
parent | d4f5c72896b6b47cae276f49081a801491be6838 (diff) | |
parent | 98128f389cc318dbd1d597cf8d2d09902cddcb4b (diff) | |
download | u-boot-imx-22e05df45cc343eda3266312bde676737d9bc70c.zip u-boot-imx-22e05df45cc343eda3266312bde676737d9bc70c.tar.gz u-boot-imx-22e05df45cc343eda3266312bde676737d9bc70c.tar.bz2 |
Merge with pollux.denx.org:/home/git/u-boot/.git
Diffstat (limited to 'board')
40 files changed, 8674 insertions, 2321 deletions
diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c index 5220fcf..f6228ef 100644 --- a/board/at91rm9200dk/flash.c +++ b/board/at91rm9200dk/flash.c @@ -259,8 +259,7 @@ void flash_print_info (flash_info_t * info) break; default: printf ("Unknown Chip Type\n"); - goto Done; - break; + return; } printf (" Size: %ld MB in %d Sectors\n", @@ -275,8 +274,6 @@ void flash_print_info (flash_info_t * info) info->protect[i] ? " (RO)" : " "); } printf ("\n"); - -Done: ; } /*----------------------------------------------------------------------- diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286 index aeebc85..0345fea 100644 --- a/board/cogent/README.cma286 +++ b/board/cogent/README.cma286 @@ -65,5 +65,5 @@ PITRTCLK=65103.515625 (bloody hell!). If anyone finds anything wrong with the stuff above, I would appreciate an email about it. -Murray Jensen <Murray.Jensen@cmst.csiro.au> +Murray Jensen <Murray.Jensen@csiro.au> 21-Aug-00 diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 2aa2b57..7db2a60 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -141,6 +141,20 @@ int board_early_init_f (void) } +int misc_init_r (void) +{ + unsigned long cntrl0Reg; + + /* + * Setup UART1 handshaking: use CTS instead of DSR + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00001000); + + return (0); +} + + /* * Check Board Identity: */ diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index cb458eb..d1b6807 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -77,10 +77,10 @@ int board_revision(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + value = in32(GPIO0_IR) & 0x00100200; /* get config bits */ /* * Restore GPIO settings @@ -88,18 +88,18 @@ int board_revision(void) mtdcr(cntrl0, cntrl0Reg); switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version 1.0 and 1.1 */ + case 0x00100200: + /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ return 1; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 1.2 */ + case 0x00000200: + /* CS2==0 && IRQ5==1 -> version 1.2 */ return 2; + case 0x00000000: + /* CS2==0 && IRQ5==0 -> version 1.3 */ + return 3; #if 0 /* not yet manufactured ! */ case 0x00100000: - /* CS2==1 && CS3==0 -> version 1.3 */ - return 3; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 1.4 */ + /* CS2==1 && IRQ5==0 -> version 1.4 */ return 4; #endif default: @@ -393,3 +393,48 @@ int testdram (void) } /* ------------------------------------------------------------------------- */ +int wpeeprom(int wp) +{ + int wp_state = wp; + volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404; + + if (wp == 1) { + *uart1_mcr &= ~0x02; + } else if (wp == 0) { + *uart1_mcr |= 0x02; + } else { + if (*uart1_mcr & 0x02) { + wp_state = 0; + } else { + wp_state = 1; + } + } + return wp_state; +} + +int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int wp = -1; + if (argc >= 2) { + if (argv[1][0] == '1') { + wp = 1; + } else if (argv[1][0] == '0') { + wp = 0; + } + } + + wp = wpeeprom(wp); + printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); + return 0; +} + +U_BOOT_CMD( + wpeeprom, 2, 1, do_wpeeprom, + "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n", + "wpeeprom\n" + " - check I2C EEPROM write protection state\n" + "wpeeprom 1\n" + " - enable I2C EEPROM write protection\n" + "wpeeprom 0\n" + " - disable I2C EEPROM write protection\n" + ); diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c index 71fde48..fdc02e3 100644 --- a/board/esd/wuh405/fpgadata.c +++ b/board/esd/wuh405/fpgadata.c @@ -1,1725 +1,1818 @@ - 0x1f,0x8b,0x08,0x08,0x72,0xdc,0x88,0x41,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x7b,0x78,0x14,0xd7, - 0x95,0x2f,0xba,0x7a,0x57,0x21,0x4a,0xdd,0x2d,0x75,0x59,0x40,0x46,0x31,0x36,0x94, - 0x5a,0x82,0x34,0x72,0xab,0x69,0x1a,0x22,0xcb,0xb2,0xdc,0x2a,0x04,0x93,0x28,0x40, - 0x82,0xc6,0xc9,0x9c,0xcf,0x33,0xc9,0x75,0xda,0x0e,0xc9,0x61,0x7c,0x70,0x8e,0xe2, - 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0xff,0x4f,0x1b,0xa0,0x78,0xf9,0x79,0x7c,0x38,0xd8,0xe0,0xc3,0xee,0x03,0xe3,0x1b, + 0xf3,0xfd,0x9b,0x4f,0x1e,0x0f,0x5d,0x7a,0xa6,0xff,0xe3,0x2f,0x1e,0xbd,0x0f,0x1e, + 0x11,0x2f,0x28,0x7c,0xc8,0xa6,0xbe,0xf8,0x59,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4, + 0xb4,0xb4,0xb4,0xb4,0xfe,0xdf,0x25,0x6b,0x07,0xaa,0x6b,0x07,0x2d,0x2d,0x2d,0x2d, + 0x2d,0x2d,0x2d,0x2d,0x2d,0x2d,0xad,0xe7,0x4b,0xd6,0x0e,0x09,0x5d,0x3b,0x68,0x69, + 0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x3d,0x5f,0xb2,0x76,0x30,0x65,0xed, + 0xf0,0xbf,0x0e,0x45,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0xeb,0xbf, + 0x28,0x5f,0xfc,0xd1,0x24,0xf8,0xe7,0x79,0x1f,0xb8,0xf8,0xce,0x53,0xdc,0x07,0xf6, + 0xb9,0xdf,0x27,0xd4,0x3f,0x6b,0xf8,0x50,0x25,0xd1,0x39,0x1f,0x9f,0x7e,0xb6,0xdf, + 0xbf,0x00,0x34,0x34,0xbf,0x69,0xee,0x33,0x01,0x00, diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 8980209..fca11d0 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -170,3 +170,13 @@ int board_early_init_r (void) *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); return 0; } +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif diff --git a/board/pm854/flash.c b/board/pm854/flash.c deleted file mode 100644 index d714589..0000000 --- a/board/pm854/flash.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#if !defined(CFG_NO_FLASH) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - } - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128 Mbit, 128 x 128K)\n"); - break; - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1] & 0x00FF00FF; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case (INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - sector_offset = 0x40000; - break; /* => 2x8 MB */ - - case (INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - sector_offset = 0x40000; - break; /* => 2x16 MB */ - - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CFG_NO_FLASH */ diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c new file mode 100644 index 0000000..762fb73 --- /dev/null +++ b/board/sandburst/common/flash.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Ported from Ebony flash support + * Travis B. Sawyer + * Sandburst Corporation + */ +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xfff80000} /* Boot Flash */ +}; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size( + (vu_long *)flash_addr_table[index][i], &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i]<<20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + total_b += flash_info[i].size; + } + + return total_b; +} + + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; k<size; k++) + { + if (*flash++ != 0xffffffff) + { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; + } + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); + + /* Write auto select command: read Manufacturer ID */ + udelay(10000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + udelay(1000); + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + udelay(1000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + udelay(1000); + + value = addr2[0]; + + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; /* => 512 kb */ + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* reset to return to reading data */ + addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + DEBUGF("Erasing sector %p\n", addr2); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c new file mode 100644 index 0000000..858b38c --- /dev/null +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by + * Travis B. Sawyer + * Sandburst Corporation. + */ +#include <common.h> +#include <ppc4xx.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include <i2c.h> +#include <440_i2c.h> +#include <command.h> +#include "ppc440gx_i2c.h" + +#ifdef CONFIG_I2C_BUS1 + +#define IIC_OK 0 +#define IIC_NOK 1 +#define IIC_NOK_LA 2 /* Lost arbitration */ +#define IIC_NOK_ICT 3 /* Incomplete transfer */ +#define IIC_NOK_XFRA 4 /* Transfer aborted */ +#define IIC_NOK_DATA 5 /* No data in buffer */ +#define IIC_NOK_TOUT 6 /* Transfer timeout */ + +#define IIC_TIMEOUT 1 /* 1 second */ +#if defined(CFG_I2C_NOPROBES) +static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#endif + +static void _i2c_bus1_reset (void) +{ + int i, status; + + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out8 (IIC_STS1, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out8 (IIC_EXTSTS1, 0x8F); + __asm__ volatile ("eieio"); + + /* + * Get current state, reset bus + * only if no transfers are pending. + */ + i = 10; + do { + /* Get status */ + status = in8 (IIC_STS1); + udelay (500); /* 500us */ + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + /* Soft reset controller */ + status = in8 (IIC_XTCNTLSS1); + out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); + __asm__ volatile ("eieio"); + + /* make sure where in initial state, data hi, clock hi */ + out8 (IIC_DIRECTCNTL1, 0xC); + for (i = 0; i < 10; i++) { + if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { + /* clock until we get to known state */ + out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ + udelay (100); /* 100us */ + out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ + udelay (100); /* 100us */ + } else { + break; + } + } + /* send start condition */ + out8 (IIC_DIRECTCNTL1, 0x4); + udelay (1000); /* 1ms */ + /* send stop condition */ + out8 (IIC_DIRECTCNTL1, 0xC); + udelay (1000); /* 1ms */ + /* Unreset controller */ + out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); + udelay (1000); /* 1ms */ +} + +void i2c1_init (int speed, int slaveadd) +{ + sys_info_t sysInfo; + unsigned long freqOPB; + int val, divisor; + +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif + + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus1_reset (); + + /* clear lo master address */ + out8 (IIC_LMADR1, 0); + + /* clear hi master address */ + out8 (IIC_HMADR1, 0); + + /* clear lo slave address */ + out8 (IIC_LSADR1, 0); + + /* clear hi slave address */ + out8 (IIC_HSADR1, 0); + + /* Clock divide Register */ + /* get OPB frequency */ + get_sys_info (&sysInfo); + freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + /* set divisor according to freqOPB */ + divisor = (freqOPB - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out8 (IIC_CLKDIV1, divisor); + + /* no interrupts */ + out8 (IIC_INTRMSK1, 0); + + /* clear transfer count */ + out8 (IIC_XFRCNT1, 0); + + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out8 (IIC_XTCNTLSS1, 0xF0); + + /* Mode Control Register + Flush Slave/Master data buffer */ + out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + __asm__ volatile ("eieio"); + + + val = in8(IIC_MDCNTL1); + __asm__ volatile ("eieio"); + + /* Ignore General Call, slave transfers are ignored, + disable interrupts, exit unknown bus state, enable hold + SCL + 100kHz normaly or FastMode for 400kHz and above + */ + + val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; + if( speed >= 400000 ){ + val |= IIC_MDCNTL_FSM; + } + out8 (IIC_MDCNTL1, val); + + /* clear control reg */ + out8 (IIC_CNTL1, 0x00); + __asm__ volatile ("eieio"); + +} + +/* + This code tries to use the features of the 405GP i2c + controller. It will transfer up to 4 bytes in one pass + on the loop. It only does out8(lbz) to the buffer when it + is possible to do out16(lhz) transfers. + + cmd_type is 0 for write 1 for read. + + addr_len can take any value from 0-255, it is only limited + by the char, we could make it larger if needed. If it is + 0 we skip the address write cycle. + + Typical case is a Write of an addr followd by a Read. The + IBM FAQ does not cover this. On the last byte of the write + we don't set the creg CHT bit, and on the first bytes of the + read we set the RPST bit. + + It does not support address only transfers, there must be + a data part. If you want to write the address yourself, put + it in the data pointer. + + It does not support transfer to/from address 0. + + It does not check XFRCNT. +*/ +static +int i2c_transfer1(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len ) +{ + unsigned char* ptr; + int reading; + int tran,cnt; + int result; + int status; + int i; + uchar creg; + + if( data == 0 || data_len == 0 ){ + /*Don't support data transfer of no length or to address 0*/ + printf( "i2c_transfer: bad call\n" ); + return IIC_NOK; + } + if( addr && addr_len ){ + ptr = addr; + cnt = addr_len; + reading = 0; + }else{ + ptr = data; + cnt = data_len; + reading = cmd_type; + } + + /*Clear Stop Complete Bit*/ + out8(IIC_STS1,IIC_STS_SCMP); + /* Check init */ + i=10; + do { + /* Get status */ + status = in8(IIC_STS1); + __asm__ volatile("eieio"); + i--; + } while ((status & IIC_STS_PT) && (i>0)); + + if (status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + return(result); + } + /*flush the Master/Slave Databuffers*/ + out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); + /*need to wait 4 OPB clocks? code below should take that long*/ + + /* 7-bit adressing */ + out8(IIC_HMADR1,0); + out8(IIC_LMADR1, chip); + __asm__ volatile("eieio"); + + tran = 0; + result = IIC_OK; + creg = 0; + + while ( tran != cnt && (result == IIC_OK)) { + int bc,j; + + /* Control register = + Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, + Transfer is a sequence of transfers + */ + creg |= IIC_CNTL_PT; + + bc = (cnt - tran) > 4 ? 4 : + cnt - tran; + creg |= (bc-1)<<4; + /* if the real cmd type is write continue trans*/ + if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) + creg |= IIC_CNTL_CHT; + + if (reading) + creg |= IIC_CNTL_READ; + else { + for(j=0; j<bc; j++) { + /* Set buffer */ + out8(IIC_MDBUF1,ptr[tran+j]); + __asm__ volatile("eieio"); + } + } + out8(IIC_CNTL1, creg ); + __asm__ volatile("eieio"); + + /* Transfer is in progress + we have to wait for upto 5 bytes of data + 1 byte chip address+r/w bit then bc bytes + of data. + udelay(10) is 1 bit time at 100khz + Doubled for slop. 20 is too small. + */ + i=2*5*8; + do { + /* Get status */ + status = in8(IIC_STS1); + __asm__ volatile("eieio"); + udelay (10); + i--; + } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) + && (i>0)); + + if (status & IIC_STS_ERR) { + result = IIC_NOK; + status = in8 (IIC_EXTSTS1); + /* Lost arbitration? */ + if (status & IIC_EXTSTS_LA) + result = IIC_NOK_LA; + /* Incomplete transfer? */ + if (status & IIC_EXTSTS_ICT) + result = IIC_NOK_ICT; + /* Transfer aborted? */ + if (status & IIC_EXTSTS_XFRA) + result = IIC_NOK_XFRA; + } else if ( status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + } + /* Command is reading => get buffer */ + if ((reading) && (result == IIC_OK)) { + /* Are there data in buffer */ + if (status & IIC_STS_MDBS) { + /* + even if we have data we have to wait 4OPB clocks + for it to hit the front of the FIFO, after that + we can just read. We should check XFCNT here and + if the FIFO is full there is no need to wait. + */ + udelay (1); + for(j=0;j<bc;j++) { + ptr[tran+j] = in8(IIC_MDBUF1); + __asm__ volatile("eieio"); + } + } else + result = IIC_NOK_DATA; + } + creg = 0; + tran+=bc; + if( ptr == addr && tran == cnt ) { + ptr = data; + cnt = data_len; + tran = 0; + reading = cmd_type; + if( reading ) + creg = IIC_CNTL_RPST; + } + } + return (result); +} + +int i2c_probe1 (uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was <ACK>ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0); +} + + +int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + + if ( alen > 4 ) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { + printf( "I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if ( alen > 4 ) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + + } + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); +} + +/*----------------------------------------------------------------------- + * Read a register + */ +uchar i2c_reg_read1(uchar i2c_addr, uchar reg) +{ + char buf; + + i2c_read1(i2c_addr, reg, 1, &buf, 1); + + return(buf); +} + +/*----------------------------------------------------------------------- + * Write a register + */ +void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write1(i2c_addr, reg, 1, &val, 1); +} + + +int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int j; +#if defined(CFG_I2C_NOPROBES) + int k, skip; +#endif + + puts ("Valid chip addresses:"); + for(j = 0; j < 128; j++) { +#if defined(CFG_I2C_NOPROBES) + skip = 0; + for (k = 0; k < sizeof(i2c_no_probes); k++){ + if (j == i2c_no_probes[k]){ + skip = 1; + break; + } + } + if (skip) + continue; +#endif + if(i2c_probe1(j) == 0) { + printf(" %02X", j); + } + } + putc ('\n'); + +#if defined(CFG_I2C_NOPROBES) + puts ("Excluded chip addresses:"); + for( k = 0; k < sizeof(i2c_no_probes); k++ ) + printf(" %02X", i2c_no_probes[k] ); + putc ('\n'); +#endif + + return 0; +} + +U_BOOT_CMD( + iprobe1, 1, 1, do_i2c1_probe, + "iprobe1 - probe to discover valid I2C chip addresses\n", + "\n -discover valid I2C chip addresses\n" +); + +#endif /* CONFIG_I2C_BUS1 */ diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h new file mode 100644 index 0000000..cd4fc86 --- /dev/null +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ported from i2c driver for ppc4xx by AS HARNOIS by + * Travis B. Sawyer + * Sandburst Corporation + */ +#include <common.h> +#include <ppc4xx.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include <i2c.h> + +#ifdef CONFIG_HARD_I2C + +#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500) +#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR +#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) +#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) +#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR) +#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR) +#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL) +#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL) +#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS) +#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) +#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) +#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) +#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV) +#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) +#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) +#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) +#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL) + +void i2c1_init (int speed, int slaveadd); +int i2c_probe1 (uchar chip); +int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len); +int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len); +uchar i2c_reg_read1(uchar i2c_addr, uchar reg); +void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val); + +#endif /* CONFIG_HARD_I2C */ diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c new file mode 100644 index 0000000..3530416 --- /dev/null +++ b/board/sandburst/common/sb_common.c @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "ppc440gx_i2c.h" +#include "sb_common.h" + +long int fixed_sdram (void); + +/************************************************************************* + * metrobox_get_master + * + * PRI_N - active low signal. If the GPIO pin is low we are the master + * + ************************************************************************/ +int sbcommon_get_master(void) +{ + ppc440_gpio_regs_t *gpio_regs; + + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + + if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { + return 0; + } + else { + return 1; + } +} + +/************************************************************************* + * metrobox_secondary_present + * + * Figure out if secondary/slave board is present + * + ************************************************************************/ +int sbcommon_secondary_present(void) +{ + ppc440_gpio_regs_t *gpio_regs; + + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + + if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) + return 0; + else + return 1; +} + +/************************************************************************* + * sbcommon_get_serial_number + * + * Retrieve the board serial number via the mac address in eeprom + * + ************************************************************************/ +unsigned short sbcommon_get_serial_number(void) +{ + unsigned char buff[0x100]; + unsigned short sernum; + + /* Get the board serial number from eeprom */ + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + memcpy(&sernum, &buff[0xF4], 2); + sernum /= 32; + + return (sernum); +} + +/************************************************************************* + * sbcommon_fans + * + * Spin up fans 2 & 3 to get some air moving. OS will take care + * of the rest. This is mostly a precaution... + * + * Assumes i2c bus 1 is ready. + * + ************************************************************************/ +void sbcommon_fans(void) +{ + /* + * Attempt to turn on 2 of the fans... + * Need to go through the bridge + */ + puts ("FANS: "); + + /* select fan4 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x08); /* val = bus 4 */ + + /* Turn on FAN 4 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 4 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan3 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x04); /* val = bus 3 */ + + /* Turn on FAN 3 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 3 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan2 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x02); /* val = bus 4 */ + + /* Turn on FAN 2 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 2 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan1 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x01); /* val = bus 0 */ + + /* Turn on FAN 1 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 1 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + puts ("on\n"); + + return; + +} + +/************************************************************************* + * initdram + * + * Initialize sdram + * + ************************************************************************/ +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + return dram_size; +} + + +/************************************************************************* + * testdram + * + * + ************************************************************************/ +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing SDRAM: "); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("OK\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay (400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram (mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The metrobox is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The metrobox is always configured as host. */ + return(1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * board_get_enetaddr + * + * Get the ethernet MAC address for the management ethernet from the + * strap EEPROM. Note that is the BASE address for the range of + * external ethernet MACs on the board. The base + 31 is the actual + * mgmt mac address. + * + ************************************************************************/ +static int macaddr_idx = 0; + +void board_get_enetaddr (uchar * enet) +{ + int i; + unsigned short tmp; + unsigned char buff[0x100], *cp; + + if (0 == macaddr_idx) { + + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + cp = &buff[0xF0]; + + for (i = 0; i < 6; i++,cp++) + enet[i] = *cp; + + memcpy(&tmp, &enet[4], 2); + tmp += 31; + memcpy(&enet[4], &tmp, 2); + + macaddr_idx++; + } else { + enet[0] = 0x02; + enet[1] = 0x00; + enet[2] = 0x00; + enet[3] = 0x00; + enet[4] = 0x00; + if (1 == sbcommon_get_master() ) { + /* Master/Primary card */ + enet[5] = 0x01; + } else { + /* Slave/Secondary card */ + enet [5] = 0x02; + } + } + + return; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h new file mode 100644 index 0000000..888e4f0 --- /dev/null +++ b/board/sandburst/common/sb_common.h @@ -0,0 +1,76 @@ +#ifndef __SBCOMMON_H__ +#define __SBCOMMON_H__ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "ppc440gx_i2c.h" + +/* + * GPIO Settings + */ +/* Chassis settings */ +#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ +#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ + +/* Debug LEDs */ +#define SBCOMMON_GPIO_DBGLED_0 0x00000400 +#define SBCOMMON_GPIO_DBGLED_1 0x00000200 +#define SBCOMMON_GPIO_DBGLED_2 0x00100000 +#define SBCOMMON_GPIO_DBGLED_3 0x00000100 + +#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ + SBCOMMON_GPIO_DBGLED_1 | \ + SBCOMMON_GPIO_DBGLED_2 | \ + SBCOMMON_GPIO_DBGLED_3) + +#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 +#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 +#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 + +#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) + +#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ + SBCOMMON_GPIO_DBGLED_1 | \ + SBCOMMON_GPIO_DBGLED_2 | \ + SBCOMMON_GPIO_DBGLED_3 | \ + SBCOMMON_GPIO_SYS_STATUS) + +typedef struct ppc440_gpio_regs { + volatile unsigned long out; + volatile unsigned long tri_state; + volatile unsigned long dummy[4]; + volatile unsigned long open_drain; + volatile unsigned long in; +} __attribute__((packed)) ppc440_gpio_regs_t; + +int sbcommon_get_master(void); +int sbcommon_secondary_present(void); +unsigned short sbcommon_get_serial_number(void); +void sbcommon_fans(void); + +#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile new file mode 100644 index 0000000..8b3173c --- /dev/null +++ b/board/sandburst/karef/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2005 +# Sandburst Corporation +# Travis B. Sawyer +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# TBS: add for debugging purposes +BUILDUSER := $(shell whoami) +FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) + +CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +# TBS: end debugging + + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ + ../common/sb_common.o + +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk new file mode 100644 index 0000000..65c1e48 --- /dev/null +++ b/board/sandburst/karef/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2005 +# Sandburst Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Sandburst Corporation Metrobox Reference Design +# Travis B. Sawyer +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h new file mode 100644 index 0000000..cc501c9 --- /dev/null +++ b/board/sandburst/karef/hal_ka_of_auto.h @@ -0,0 +1,324 @@ +/* **************************************************************** + * Common defs for reg spec for chip ka_of + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_KA_OF_AUTO_H +#define HAL_KA_OF_AUTO_H + + +/* ---------------------------------------------------------------- + * For block: 'ofem' + */ + +/* ---- Block instance addressing (for block-select) */ +#define OFEM_BLOCK_ADDR_BIT_L 6 +#define OFEM_BLOCK_ADDR_BIT_H 9 +#define OFEM_BLOCK_ADDR_WIDTH 4 + +#define OFEM_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define OFEM_REG_ADDR_BIT_L 2 +#define OFEM_REG_ADDR_BIT_H 5 +#define OFEM_REG_ADDR_WIDTH 4 + + +/* ================================================================ + * ---- Register KA_OF_OFEM_REVISION */ +#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 +#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_RESET */ +#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 +#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 +#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_CNTL */ +#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 +#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 +#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c +#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_INTERRUPT */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 +#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c +#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_SCRATCH */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 +#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_SCRATCH_MASK */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 +#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register KA_OF_OFEM_REVISION */ +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_RESET */ +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_CNTL */ +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_INTERRUPT */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register KA_OF_OFEM_SCRATCH */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_SCRATCH_MASK */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h new file mode 100644 index 0000000..db1cec2 --- /dev/null +++ b/board/sandburst/karef/hal_ka_sc_auto.h @@ -0,0 +1,836 @@ +/* **************************************************************** + * Common defs for reg spec for chip ka_sc + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_KA_SC_AUTO_H +#define HAL_KA_SC_AUTO_H + + +/* ---------------------------------------------------------------- + * For block: 'scan' + */ + +/* ---- Block instance addressing (for block-select) */ +#define SCAN_BLOCK_ADDR_BIT_L 7 +#define SCAN_BLOCK_ADDR_BIT_H 9 +#define SCAN_BLOCK_ADDR_WIDTH 3 + +#define SCAN_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define SCAN_REG_ADDR_BIT_L 2 +#define SCAN_REG_ADDR_BIT_H 6 +#define SCAN_REG_ADDR_WIDTH 5 + + +/* ================================================================ + * ---- Register KA_SC_SCAN_REVISION */ +#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 +#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_RESET */ +#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 +#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 +#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_STATUS */ +#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 +#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 +#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_CNTL */ +#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c +#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_INFO */ +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_TO_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_TO_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_CTRL */ +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_PLL_CTRL */ +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 +#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c +#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 +#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 +#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_IN */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_MISC */ +#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 +#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 +#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_INTERRUPT */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c +#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 +#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCRATCH */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 +#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCRATCH_MASK */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 +#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register KA_SC_SCAN_REVISION */ +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_RESET */ +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_STATUS */ +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_CNTL */ +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_INFO */ +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_TO_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_TO_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_CTRL */ +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_PLL_CTRL */ +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_IN */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_MISC */ +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_INTERRUPT */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCRATCH */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCRATCH_MASK */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S new file mode 100644 index 0000000..b1d47a4 --- /dev/null +++ b/board/sandburst/karef/init.S @@ -0,0 +1,101 @@ +/* +* Copyright (C) 2005 Sandburst Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +/* + * Ported from Ebony init.S by Travis B. Sawyer + */ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c new file mode 100644 index 0000000..3856a39 --- /dev/null +++ b/board/sandburst/karef/karef.c @@ -0,0 +1,577 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <command.h> +#include "karef.h" +#include "karef_version.h" +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "../common/sb_common.h" +#include "../common/ppc440gx_i2c.h" + +void fpga_init (void); + +KAREF_BOARD_ID_ST board_id_as[] = +{ + {"Undefined"}, /* Not specified */ + {"Kamino Reference Design"}, + {"Reserved"}, /* Reserved for future use */ + {"Reserved"}, /* Reserved for future use */ +}; + +KAREF_BOARD_ID_ST ofem_board_id_as[] = +{ + {"Undefined"}, + {"1x10 + 10x2"}, + {"Reserved"}, + {"Reserved"}, +}; + +/************************************************************************* + * board_early_init_f + * + * Setup chip selects, initialize the Opto-FPGA, initialize + * interrupt polarity and triggers. + ************************************************************************/ +int board_early_init_f (void) +{ + ppc440_gpio_regs_t *gpio_regs; + + /* Enable GPIO interrupts */ + mtsdr(sdr_pfc0, 0x00103E00); + + /* Setup access for LEDs, and system topology info */ + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; + gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; + + /* Turn on all the leds for now */ + gpio_regs->out = SBCOMMON_GPIO_LEDS; + + /*--------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------*/ + mtebc(xbcfg, + EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | + EBC_CFG_PR_32); + + /*--------------------------------------------------------------------+ + | 1/2 MB FLASH. Initialize bank 0 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb0ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + /*--------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb1ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb2ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | KaRef Scan FPGA. Initialize bank 3 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb5ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | MAC A & B for Kamino. OFEM FPGA decodes the addresses + | Initialize bank 4 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb4ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | OFEM FPGA Initialize bank 5 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb3ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + + mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb6ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | BME-32. Initialize bank 7 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb7ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + +-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non- critical */ + mtdcr (uic0pr, 0xfffffe03); /* polarity */ + mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc8ff); /* polarity */ + mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffff83ff); /* polarity */ + mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); + mtdcr (uicb0tr, 0x00000000); + mtdcr (uicb0vr, 0x00000001); + + fpga_init(); + + return 0; +} + + +/************************************************************************* + * checkboard + * + * Dump pertinent info to the console + ************************************************************************/ +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char brd_rev, brd_id; + unsigned short sernum; + unsigned char scan_rev, scan_id, ofem_rev, ofem_id; + unsigned char ofem_brd_rev, ofem_brd_id; + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + + scan_id = (unsigned char)((karef_ps->revision_ul & + SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); + + scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) + >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); + + brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); + + brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); + + ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); + + ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); + + if (0xF != ofem_brd_id) { + ofem_id = (unsigned char)((ofem_ps->revision_ul & + SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); + + ofem_rev = (unsigned char)((ofem_ps->revision_ul & + SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) + >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); + } + + get_sys_info (&sysinfo); + + sernum = sbcommon_get_serial_number(); + + printf ("Board: Sandburst Corporation Kamino Reference Design " + "Serial Number: %d\n", sernum); + printf ("%s\n", KAREF_U_BOOT_REL_STR); + + printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + if (sbcommon_get_master()) { + printf("Slot 0 - Master\nSlave board"); + if (sbcommon_secondary_present()) + printf(" present\n"); + else + printf(" not detected\n"); + } else { + printf("Slot 1 - Slave\n\n"); + } + + printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); + printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); + if(0xF != ofem_brd_id) { + printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); + printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); + } + + printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + + /* Fix the ack in the bme 32 */ + udelay(5000); + out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + asm("eieio"); + + + return (0); +} + +/************************************************************************* + * misc_init_f + * + * Initialize I2C bus one to gain access to the fans + ************************************************************************/ +int misc_init_f (void) +{ + /* Turn on i2c bus 1 */ + puts ("I2C1: "); + i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + + /* Turn on fans 3 & 4 */ + sbcommon_fans(); + + return (0); +} + +/************************************************************************* + * misc_init_r + * + * Do nothing. + ************************************************************************/ +int misc_init_r (void) +{ + unsigned short sernum; + char envstr[255]; + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + unsigned char ofem_id; + + if(NULL != getenv("secondserial")) { + puts("secondserial is set, switching to second serial port\n"); + setenv("stderr", "serial1"); + setenv("stdout", "serial1"); + setenv("stdin", "serial1"); + } + + setenv("ubrelver", KAREF_U_BOOT_REL_STR); + + memset(envstr, 0, 255); + sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + setenv("bldstr", envstr); + saveenv(); + + if( getenv("autorecover")) { + setenv("autorecover", NULL); + saveenv(); + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for automatic filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type allow the system to continue to boot\n"); + } + + if( getenv("fakeled")) { + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; + karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; + setenv("bootdelay", "-1"); + saveenv(); + printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); + } + + return (0); +} + +/************************************************************************* + * ide_set_reset + ************************************************************************/ +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + KAREF_FPGA_REGS_ST *karef_ps; + /* TODO: ide reset */ + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + + if (on) { + karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; + } else { + karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; + } +} +#endif /* CONFIG_IDE_RESET */ + +/************************************************************************* + * fpga_init + ************************************************************************/ +void fpga_init(void) +{ + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + unsigned char ofem_id; + unsigned long tmp; + + /* Ensure we have power all around */ + udelay(500); + + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + tmp = + SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; + + karef_ps->reset_ul = tmp; + + /* + * Wait a bit to allow the ofem fpga to get its brains + */ + udelay(5000); + + /* + * Check to see if the ofem is there + */ + ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); + if(0xF != ofem_id) { + tmp = + SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | + SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | + SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; + + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps->reset_ul = tmp; + + ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; + } + + karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; + + asm("eieio"); + + return; +} + +int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + memset(envstr, 0, 255); + /* + * Setup our ip address + */ + sprintf(envstr, "10.100.70.%d", sernum); + + setenv("ipaddr", envstr); + /* + * Setup the host ip address + */ + setenv("serverip", "10.100.17.10"); + + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " + "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " + "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" + "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", + sernum, sernum, sernum); + + setenv("bootargs_nfs", envstr); + setenv("bootargs", envstr); + + /* + * Setup CF bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", + sernum, sernum); + + setenv("bootargs_cf", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); + setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); + + /* + * Setup compact flash boot command + */ + setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); + + saveenv(); + + return(1); +} + +int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + + setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type boot<cr>.\nWhen the kernel has booted" + " please type fsrecover.sh<cr>\n"); + + return(1); +} + +U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, + "kasetup - Set environment to factory defaults\n", NULL); + +U_BOOT_CMD(karecover, 1, 1, karefRecover, + "karecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h new file mode 100644 index 0000000..7790819 --- /dev/null +++ b/board/sandburst/karef/karef.h @@ -0,0 +1,76 @@ +#ifndef __KAREF_H__ +#define __KAREF_H__ +/* + * (C) Copyright 2005 + * Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Ka Reference Design OFEM FPGA Registers & definitions */ +#include "hal_ka_sc_auto.h" +#include "hal_ka_of_auto.h" + +typedef struct karef_board_id_s { + const char name[40]; +} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; + +/* SCAN FPGA */ +typedef struct karef_fpga_regs_s +{ + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long status_ul; /* Read Only */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long boardinfo_ul; /* Read Only */ + volatile unsigned long scan_from0_ul; /* Read Only */ + volatile unsigned long scan_from1_ul; /* Read Only */ + volatile unsigned long scan_to0_ul; /* Read/Write */ + volatile unsigned long scan_to1_ul; /* Read/Write */ + volatile unsigned long scan_control_ul; /* Read/Write */ + volatile unsigned long pll_control_ul; /* Read/Write */ + volatile unsigned long core_clock_cnt_ul; /* Read/Write */ + volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ + volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ + volatile unsigned long brdout_data_ul; /* Read/Write */ + volatile unsigned long brdout_enable_ul; /* Read/Write */ + volatile unsigned long brdin_data_ul; /* Read Only */ + volatile unsigned long misc_ul; /* Read/Write */ +} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST; + +/* OFEM FPGA */ +typedef struct ofem_fpga_regs_s +{ + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ +} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST; + + +#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h new file mode 100644 index 0000000..9960b9a --- /dev/null +++ b/board/sandburst/karef/karef_version.h @@ -0,0 +1,26 @@ +#ifndef _KAREF_VERSION_H_ +#define _KAREF_VERSION_H_ +/* + * Copyright (C) 2005 Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define KAREF_U_BOOT_REL_STR "Release 0.0.7" +#endif diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds new file mode 100644 index 0000000..ff8658f --- /dev/null +++ b/board/sandburst/karef/u-boot.lds @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/karef/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug new file mode 100644 index 0000000..c6522b9 --- /dev/null +++ b/board/sandburst/karef/u-boot.lds.debug @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/karef/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile new file mode 100644 index 0000000..06a9a22 --- /dev/null +++ b/board/sandburst/metrobox/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2005 +# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# TBS: add for debugging purposes +BUILDUSER := $(shell whoami) +FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) + +CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +# TBS: end debugging + + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ + ../common/sb_common.o +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk new file mode 100644 index 0000000..91aee2f --- /dev/null +++ b/board/sandburst/metrobox/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2005 +# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h new file mode 100644 index 0000000..c99b38c --- /dev/null +++ b/board/sandburst/metrobox/hal_xc_auto.h @@ -0,0 +1,553 @@ +/* **************************************************************** + * Common defs for reg spec for chip xc + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_XC_AUTO_H +#define HAL_XC_AUTO_H + +/* ---------------------------------------------------------------- + * For block: 'xcvr_cntl' + */ + +/* ---- Block instance addressing (for block-select) */ +#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 +#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 +#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 + +#define XCVR_CNTL_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define XCVR_CNTL_REG_ADDR_BIT_L 2 +#define XCVR_CNTL_REG_ADDR_BIT_H 5 +#define XCVR_CNTL_REG_ADDR_WIDTH 4 + + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_REVISION */ +#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_RESET */ +#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 +#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_STATUS */ +#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 +#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_CNTL */ +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c +#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_BRD_INFO */ +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 +#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 +#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_INTERRUPT */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c +#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 +#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_SCRATCH */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 +#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 +#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_REVISION */ +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_RESET */ +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_STATUS */ +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_CNTL */ +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_BRD_INFO */ +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_INTERRUPT */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_SCRATCH */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S new file mode 100644 index 0000000..e398f00 --- /dev/null +++ b/board/sandburst/metrobox/init.S @@ -0,0 +1,99 @@ +/* +* Copyright (C) 2005 +* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c new file mode 100644 index 0000000..869367d --- /dev/null +++ b/board/sandburst/metrobox/metrobox.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <common.h> +#include <command.h> +#include "metrobox.h" +#include "metrobox_version.h" +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "../common/ppc440gx_i2c.h" +#include "../common/sb_common.h" + +void fpga_init (void); + +METROBOX_BOARD_ID_ST board_id_as[] = +{ {"Undefined"}, /* Not specified */ + {"2x10Gb"}, /* 2 ports, 10 GbE */ + {"20x1Gb"}, /* 20 ports, 1 GbE */ + {"Reserved"}, /* Reserved for future use */ +}; + +/************************************************************************* + * board_early_init_f + * + * Setup chip selects, initialize the Opto-FPGA, initialize + * interrupt polarity and triggers. + ************************************************************************/ +int board_early_init_f (void) +{ + ppc440_gpio_regs_t *gpio_regs; + + /* Enable GPIO interrupts */ + mtsdr(sdr_pfc0, 0x00103E00); + + /* Setup access for LEDs, and system topology info */ + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; + gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; + + /* Turn on all the leds for now */ + gpio_regs->out = SBCOMMON_GPIO_LEDS; + + /*--------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------*/ + mtebc(xbcfg, + EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | + EBC_CFG_PR_32); + + /*--------------------------------------------------------------------+ + | 1/2 MB FLASH. Initialize bank 0 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb0ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + /*--------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb1ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb2ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | OPTO & OFEM FPGA. Initialize bank 3 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb3ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | MAC A for metrobox + | MAC A & B for Kamino. OFEM FPGA decodes the addresses + | Initialize bank 4 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb4ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | Metrobox MAC B Initialize bank 5 with default values. + | KA REF FPGA Initialize bank 5 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb5ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb6ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | BME-32. Initialize bank 7 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb7ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + +-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non- critical */ + mtdcr (uic0pr, 0xfffffe03); /* polarity */ + mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc8ff); /* polarity */ + mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffff83ff); /* polarity */ + mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); + mtdcr (uicb0tr, 0x00000000); + mtdcr (uicb0vr, 0x00000001); + + fpga_init(); + + return 0; +} + +/************************************************************************* + * checkboard + * + * Dump pertinent info to the console + ************************************************************************/ +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char brd_rev, brd_id; + unsigned short sernum; + unsigned char opto_rev, opto_id; + OPTO_FPGA_REGS_ST *opto_ps; + + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + + opto_id = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); + + brd_rev = (unsigned char)((opto_ps->boardinfo_ul & + SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) + >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); + + brd_id = (unsigned char)((opto_ps->boardinfo_ul & + SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) + >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); + + get_sys_info (&sysinfo); + + sernum = sbcommon_get_serial_number(); + printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); + printf ("%s\n", METROBOX_U_BOOT_REL_STR); + + printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + if (sbcommon_get_master()) { + printf("Slot 0 - Master\nSlave board"); + if (sbcommon_secondary_present()) + printf(" present\n"); + else + printf(" not detected\n"); + } else { + printf("Slot 1 - Slave\n\n"); + } + + printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); + printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]); + + printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + + + /* Fix the ack in the bme 32 */ + udelay(5000); + out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + asm("eieio"); + + + return (0); +} + +/************************************************************************* + * misc_init_f + * + * Initialize I2C bus one to gain access to the fans + ************************************************************************/ +int misc_init_f (void) +{ + /* Turn on i2c bus 1 */ + puts ("I2C1: "); + i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + + /* Turn on fans */ + sbcommon_fans(); + + return (0); +} + +/************************************************************************* + * misc_init_r + * + * Do nothing. + ************************************************************************/ +int misc_init_r (void) +{ + unsigned short sernum; + char envstr[255]; + unsigned char opto_rev; + OPTO_FPGA_REGS_ST *opto_ps; + + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + if(NULL != getenv("secondserial")) { + puts("secondserial is set, switching to second serial port\n"); + setenv("stderr", "serial1"); + setenv("stdout", "serial1"); + setenv("stdin", "serial1"); + } + + setenv("ubrelver", METROBOX_U_BOOT_REL_STR); + + memset(envstr, 0, 255); + sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + setenv("bldstr", envstr); + saveenv(); + + if( getenv("autorecover")) { + setenv("autorecover", NULL); + saveenv(); + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for automatic filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type allow the system to continue to boot\n"); + } + + if( getenv("fakeled")) { + setenv("bootdelay", "-1"); + saveenv(); + printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + + if(0x12 <= opto_rev) { + opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; + } + } + + return (0); +} + +/************************************************************************* + * ide_set_reset + ************************************************************************/ +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + OPTO_FPGA_REGS_ST *opto_ps; + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + if (on) { /* assert RESET */ + opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; + } else { /* release RESET */ + opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; + } +} +#endif /* CONFIG_IDE_RESET */ + +/************************************************************************* + * fpga_init + ************************************************************************/ +void fpga_init(void) +{ + OPTO_FPGA_REGS_ST *opto_ps; + unsigned char opto_rev; + unsigned long tmp; + + /* Ensure we have power all around */ + udelay(500); + + /* + * Take appropriate hw bits out of reset + */ + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + tmp = + SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; + opto_ps->reset_ul = tmp; + /* + * Turn on the 'Slow Blink' for the System Error Led. + * Ensure FPGA rev is up to at least rev 0x12 + */ + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + if(0x12 <= opto_rev) { + opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; + } + + asm("eieio"); + + return; +} + +int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + memset(envstr, 0, 255); + /* + * Setup our ip address + */ + sprintf(envstr, "10.100.60.%d", sernum); + + setenv("ipaddr", envstr); + /* + * Setup the host ip address + */ + setenv("serverip", "10.100.17.10"); + + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " + "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " + "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" + ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", + sernum, sernum, sernum); + + setenv("bootargs_nfs", envstr); + setenv("bootargs", envstr); + + /* + * Setup CF bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", + sernum, sernum); + + setenv("bootargs_cf", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); + setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); + + /* + * Setup compact flash boot command + */ + setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); + + saveenv(); + + + return(1); +} + +int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", + sernum, sernum); + + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type boot<cr>.\nWhen the kernel has booted" + " please type fsrecover.sh<cr>\n"); + + return(1); +} + +U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, + "mbsetup - Set environment to factory defaults\n", NULL); + +U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, + "mbrecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h new file mode 100644 index 0000000..cb7a83c --- /dev/null +++ b/board/sandburst/metrobox/metrobox.h @@ -0,0 +1,45 @@ +#ifndef __METROBOX_H__ +#define __METROBOX_H__ +/* + * (C) Copyright 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +typedef struct metrobox_board_id_s { + const char name[40]; +} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; + + +/* Metrobox Opto-FPGA registers and definitions */ +#include "hal_xc_auto.h" +typedef struct opto_fpga_regs_s { + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long status_ul; /* Read Only */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long boardinfo_ul; /* Read Only */ +} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST; + +#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h new file mode 100644 index 0000000..1b6fee5 --- /dev/null +++ b/board/sandburst/metrobox/metrobox_version.h @@ -0,0 +1,27 @@ +#ifndef _METROBOX_VERSION_H_ +#define _METROBOX_VERSION_H_ +/* + * (C) Copyright 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" + +#endif diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds new file mode 100644 index 0000000..0fdb166 --- /dev/null +++ b/board/sandburst/metrobox/u-boot.lds @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/metrobox/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug new file mode 100644 index 0000000..459a1d8 --- /dev/null +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/metrobox/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile new file mode 100644 index 0000000..8c529a0 --- /dev/null +++ b/board/stxxtc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stxxtc/config.mk b/board/stxxtc/config.mk new file mode 100644 index 0000000..f5dc034 --- /dev/null +++ b/board/stxxtc/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# STx XTc +# + +TEXT_BASE = 0x40F00000 diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c new file mode 100644 index 0000000..b38b4be --- /dev/null +++ b/board/stxxtc/stxxtc.c @@ -0,0 +1,638 @@ +/* + * (C) Copyright 2000-2004 + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2005 + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot port on STx XTc board + * Mostly copied from Netta + */ + +#include <common.h> +#include <miiphy.h> + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#endif + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Silicon Turnkey eXpress XTc\n"); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define GPL0_AAAA 0x00000000 +#define GPL0_AAA0 0x00200000 +#define GPL0_AAA1 0x00300000 +#define GPL0_000A 0x00800000 +#define GPL0_0000 0x00A00000 +#define GPL0_0001 0x00B00000 +#define GPL0_111A 0x00C00000 +#define GPL0_1110 0x00E00000 +#define GPL0_1111 0x00F00000 + +#define GPL1_0000 0x00000000 +#define GPL1_0001 0x00040000 +#define GPL1_1110 0x00080000 +#define GPL1_1111 0x000C0000 + +#define GPL2_0000 0x00000000 +#define GPL2_0001 0x00010000 +#define GPL2_1110 0x00020000 +#define GPL2_1111 0x00030000 + +#define GPL3_0000 0x00000000 +#define GPL3_0001 0x00004000 +#define GPL3_1110 0x00008000 +#define GPL3_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +#define A10_AAAA GPL0_AAAA +#define A10_AAA0 GPL0_AAA0 +#define A10_AAA1 GPL0_AAA1 +#define A10_000A GPL0_000A +#define A10_0000 GPL0_0000 +#define A10_0001 GPL0_0001 +#define A10_111A GPL0_111A +#define A10_1110 GPL0_1110 +#define A10_1111 GPL0_1111 + +#define RAS_0000 GPL1_0000 +#define RAS_0001 GPL1_0001 +#define RAS_1110 GPL1_1110 +#define RAS_1111 GPL1_1111 + +#define CAS_0000 GPL2_0000 +#define CAS_0001 GPL2_0001 +#define CAS_1110 GPL2_1110 +#define CAS_1111 GPL2_1111 + +#define WE_0000 GPL3_0000 +#define WE_0001 GPL3_0001 +#define WE_1110 GPL3_1110 +#define WE_1111 GPL3_1111 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +static const uint nandcs_table[0x40] = { + /* RSS */ + CS_1000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1110 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111, + CS_0000 | GPL4_0001 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ + + /* RBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_1000 | GPL4_1111 | GPL5_1110 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0001 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, + + /* WBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* UPT */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 , + CS_0001 | LAST, +}; + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 9 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + u32 d1, d2; + + upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CFG_BR4_PRELIM; + + memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + d1 = 0x12345678; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + + return size; +} + +/* ------------------------------------------------------------------------- */ + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + udelay(10000); + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + miiphy_read(phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK _BW(6) +#define PA_GP_OUTMASK (_BW(7)) +#define PA_SP_MASK 0 +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(7)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK 0 +#define PB_GP_OUTMASK (_B(23)) +#define PB_SP_MASK 0 +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_B(23)) +#define PB_SP_DIRVAL 0 + +#define PC_GP_INMASK 0 +#define PC_GP_OUTMASK (_BW(15)) + +#define PC_SP_MASK 0 +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL 0 +#define PC_SP_DIRVAL 0 + +#define PE_GP_INMASK 0 +#define PE_GP_OUTMASK 0 +#define PE_GP_OUTVAL 0 + +#define PE_SP_MASK 0 +#define PE_ODR_VAL 0 +#define PE_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + (void)ioport; + (void)cpm; +#if 1 + /* NAND chip select */ + upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); + memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); + memctl->memc_mbmr = 0; /* all clear */ +#endif + + memctl->memc_br5 &= ~BR_V; + memctl->memc_br6 &= ~BR_V; + memctl->memc_br7 &= ~BR_V; + +#if 1 + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + cpm->cp_pedat = PE_GP_OUTVAL; + cpm->cp_peodr = PE_ODR_VAL; + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; + cpm->cp_pepar = PE_SP_MASK; +#endif + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <linux/mtd/nand.h> + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen; + + totlen = nand_probe(CFG_NAND_BASE); + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + +/* called from timer interrupt every 1/CFG_HZ sec */ +void board_show_activity(ulong timestamp) +{ +} + +/* called when looping */ +void show_activity(int arg) +{ +} + +#endif + +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + /* printf("overwrite_console called\n"); */ + return 0; +} +#endif + +extern int drv_phone_init(void); +extern int drv_phone_use_me(void); +extern int drv_phone_is_idle(void); + +int misc_init_r(void) +{ + return 0; +} + +int last_stage_init(void) +{ + reset_phys(); + + return 0; +} diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds new file mode 100644 index 0000000..c3dac0e --- /dev/null +++ b/board/stxxtc/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug new file mode 100644 index 0000000..21b7e6a --- /dev/null +++ b/board/stxxtc/u-boot.lds.debug @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile index 44be6ca..6302fa8 100644 --- a/board/voiceblue/Makefile +++ b/board/voiceblue/Makefile @@ -32,21 +32,23 @@ SOBJS := setup.o gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) LOAD_ADDR = 0x10400000 +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds all: $(LIB) eeprom.srec eeprom.bin $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) $(SOBJS) -eeprom.srec: eeprom.o - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \ +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ -L../../examples -lstubs \ -L../../lib_generic -lgeneric \ -L$(gcclibdir) -lgcc $(OBJCOPY) -O srec $(<:.o=) $@ eeprom.bin: eeprom.srec - $(OBJCOPY) -O binary $< $@ 2>/dev/null + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null clean: rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c index 6383a02..0ad1b66 100644 --- a/board/voiceblue/eeprom.c +++ b/board/voiceblue/eeprom.c @@ -30,40 +30,6 @@ #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE -static int verify_macaddr(char *); -static int set_mac(char *); - -int eeprom(int argc, char *argv[]) -{ - app_startup(argv); - if (get_version() != XF_VERSION) { - printf("Wrong XF_VERSION.\n"); - printf("Application expects ABI version %d\n", XF_VERSION); - printf("Actual U-Boot ABI version %d\n", (int)get_version()); - return 1; - } - - if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { - printf("SMSC91111 not found.\n"); - return 2; - } - - if (argc != 2) { - printf("VoiceBlue EEPROM writer\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); - printf("Usage:\n\t<mac_address>"); - return 3; - } - - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - printf("*** ERROR ***\n"); - return 4; - } - - return 0; -} - static u16 read_eeprom_reg(u16 reg) { int timeout; @@ -106,17 +72,28 @@ static int write_eeprom_reg(u16 value, u16 reg) return 1; } +static int write_data(u16 *buf, int len) +{ + u16 reg = 0x23; + + while (len--) + write_eeprom_reg(*buf++, reg++); + + return 0; +} + static int verify_macaddr(char *s) { u16 reg; int i, err = 0; - printf("Verifying MAC Address: "); + printf("MAC Address: "); err = i = 0; for (i = 0; i < 3; i++) { reg = read_eeprom_reg(0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - err |= reg != ((u16 *)s)[i]; + if (s) + err |= reg != ((u16 *)s)[i]; } return err ? 0 : 1; @@ -138,3 +115,97 @@ static int set_mac(char *s) return 0; } + +static int parse_element(char *s, unsigned char *buf, int len) +{ + int cnt; + char *p, num[3]; + unsigned char id; + + id = simple_strtoul(s, &p, 16); + if (*p++ != ':') + return -1; + cnt = 2; + num[2] = 0; + for (; *p; p += 2) { + if (p[1] == 0) + return -2; + if (cnt + 3 > len) + return -3; + num[0] = p[0]; + num[1] = p[1]; + buf[cnt++] = simple_strtoul(num, NULL, 16); + } + buf[0] = id; + buf[1] = cnt - 2; + + return cnt; +} + +int eeprom(int argc, char *argv[]) +{ + int i, len, ret; + unsigned char buf[58], *p; + + app_startup(argv); + if (get_version() != XF_VERSION) { + printf("Wrong XF_VERSION.\n"); + printf("Application expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf("SMSC91111 not found.\n"); + return 2; + } + + /* Called without parameters - print MAC address */ + if (argc < 2) { + verify_macaddr(NULL); + return 0; + } + + /* Print help message */ + if (argv[1][1] == 'h') { + printf("VoiceBlue EEPROM writer\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); + return 0; + } + + /* Try to parse information elements */ + len = sizeof(buf); + p = buf; + for (i = 2; i < argc; i++) { + ret = parse_element(argv[i], p, len); + switch (ret) { + case -1: + printf("Element %d: malformed\n", i - 1); + return 3; + case -2: + printf("Element %d: odd character count\n", i - 1); + return 3; + case -3: + printf("Out of EEPROM memory\n"); + return 3; + default: + p += ret; + len -= ret; + } + } + + /* First argument (MAC) is mandatory */ + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + printf("*** MAC address does not match! ***\n"); + return 4; + } + + while (len--) + *p++ = 0; + + write_data((u16 *)buf, sizeof(buf) >> 1); + + return 0; +} diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds new file mode 100644 index 0000000..317550d --- /dev/null +++ b/board/voiceblue/eeprom.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + eeprom_start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S new file mode 100644 index 0000000..8f88de5 --- /dev/null +++ b/board/voiceblue/eeprom_start.S @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2005 2N Telekomunikace + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +.globl _start +_start: b eeprom |