Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

43 files changed, 58 insertions, 1348 deletions

diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 709d41e..3dec315 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -33,14 +33,6 @@
 
 extern void board_pll_init_f(void);
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void cram_bcr_write(u32 wr_val)
 {
@@ -116,10 +108,3 @@ long int initdram(int board_type)
 
 	return (CFG_MBYTES_RAM << 20);
 }
-
-#ifndef CONFIG_NAND_SPL
-int testdram(void)
-{
-	return (0);
-}
-#endif
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 5077187..0c7d69e 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -466,73 +466,6 @@ long int initdram (int board_type)
 #endif
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n, *p32, ctr;
-	const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
-
-	mtmsr(0);
-
-	for (k = 0; k <	CFG_MBYTES_SDRAM*1024;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-
-	/*
-	 * Perform a sequence test to ensure that all
-	 * memory locations are uniquely addressable
-	 */
-	ctr = 0;
-	p32 = 0;
-	while ((unsigned long)p32 != bend) {
-		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
-			printf("Writing	%3d MB\r", (unsigned long)p32 >> 20);
-		*p32++ = ctr++;
-	}
-
-	ctr = 0;
-	p32 = 0;
-	while ((unsigned long)p32 != bend) {
-		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
-			printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
-
-		if (*p32 != ctr) {
-			printf("SDRAM test fails at: %08x\n", p32);
-			return 1;
-		}
-
-		ctr++;
-		p32++;
-	}
-
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index 66e7509..9d508b8 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -66,14 +66,6 @@ int checkboard(void)
 	return (0);
 }
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
 /* -------------------------------------------------------------------------
   initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
@@ -85,11 +77,3 @@ long int initdram(int board_type)
 	ret = spd_sdram();
 	return ret;
 }
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("test: xxx MB - ok\n");
-
-	return (0);
-}
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 0f66061..4e3b349 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -211,44 +211,6 @@ long int initdram(int board_type)
 }
 #endif
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*
  *  pci_target_init
  *
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index ededb3e..c6375ac 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -116,36 +116,6 @@ long int initdram(int board_type)
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 #if !defined(CONFIG_SPD_EEPROM)
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 193083f..3a0b18f 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -258,36 +258,6 @@ u32 ddr_clktr(u32 default_val) {
 	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile
index 39328c2..981ef3a 100644
--- a/board/amcc/kilauea/Makefile
+++ b/board/amcc/kilauea/Makefile
@@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_pll.o memory.o
-SOBJS	= init.o
+COBJS	= $(BOARD).o cmd_pll.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
deleted file mode 100644
index 8cd534c..0000000
--- a/board/amcc/kilauea/init.S
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on code provided from UDTech and AMCC
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#define mtsdram_as(reg, value)		\
-	addi    r4,0,reg	;	\
-	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value@h	;	\
-	ori     r4,r4,value@l	;	\
-	mtdcr   memcfgd,r4	;
-
-	.globl  ext_bus_cntlr_init
-ext_bus_cntlr_init:
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-
-	/*
-	 * DDR2 setup
-	 */
-
-	/* Following the DDR Core Manual, here is the initialization */
-
-	/* Step 1 */
-
-	/* Step 2 */
-
-	/* Step 3 */
-
-	/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
-	mtsdram_as(SDRAM_MB0CF, 0x00006701);
-
-	/* SET SDRAM_MB1CF - Not enabled */
-	mtsdram_as(SDRAM_MB1CF, 0x00000000);
-
-	/* SET SDRAM_MB2CF  - Not enabled */
-	mtsdram_as(SDRAM_MB2CF, 0x00000000);
-
-	/* SET SDRAM_MB3CF  - Not enabled */
-	mtsdram_as(SDRAM_MB3CF, 0x00000000);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
-	mtsdram_as(SDRAM_CLKTR, 0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram_as(SDRAM_RTR, 0x06180000);
-
-	/* SDRAM_SDTR1 */
-	mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram_as(SDRAM_SDTR2, 0x32204232);
-
-	/* SDRAM_SDTR3	*/
-	mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
-
-	mtsdram_as(SDRAM_MMODE, 0x00000442);
-	mtsdram_as(SDRAM_MEMODE, 0x00000404);
-
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram_as(SDRAM_MCOPT1, 0x04322000);
-
-	/* NOP */
-	mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
-	 */
-	mtsdram_as(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram_as(SDRAM_INITPLR11, 0x81000442);
-	mtsdram_as(SDRAM_INITPLR12, 0x81010780);
-	mtsdram_as(SDRAM_INITPLR13, 0x81010400);
-	mtsdram_as(SDRAM_INITPLR14, 0x00000000);
-	mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram_as(SDRAM_CODT, 0x0080f837);
-	mtsdram_as(SDRAM_MODT0, 0x01800000);
-	mtsdram_as(SDRAM_MODT1, 0x00000000);
-
-	mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
-
-pll_wait:
-	bdnz	pll_wait
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram_as(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram_as(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram_as(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
-
-	blr
diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c
deleted file mode 100644
index 1d7a3fa..0000000
--- a/board/amcc/kilauea/memory.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-
-void sdram_init(void)
-{
-	return;
-}
-
-long int initdram(int board_type)
-{
-	return (CFG_MBYTES_SDRAM << 20);
-}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-    printf ("testdram\n");
-#if defined (CONFIG_NAND_U_BOOT)
-    return 0;
-#endif
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x00001000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0xaaaaaaaa;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0x55555555;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-#if !defined (CONFIG_NAND_SPL)
-	printf ("SDRAM test passed!!!\n");
-#endif
-	return 0;
-}
-#endif
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index f964511..b14b6e1 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -126,50 +126,6 @@ u32 ddr_clktr(u32 default_val) {
 }
 
 /*************************************************************************
- *  int testdram()
- *
- ************************************************************************/
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *) 0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-
-	return  0;
-}
-#endif
-
-
-/*************************************************************************
  *  pci_pre_init
  *
  *  This routine is called just prior to registering the hose and gives
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
index 39328c2..4def0d4 100644
--- a/board/amcc/makalu/Makefile
+++ b/board/amcc/makalu/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_pll.o memory.o
+COBJS	= $(BOARD).o cmd_pll.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
index 11c5b19..4d0f460 100644
--- a/board/amcc/makalu/init.S
+++ b/board/amcc/makalu/init.S
@@ -1,8 +1,11 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * Based on code provided from Senao and AMCC
+ * Originally based on code provided from Senao and AMCC
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,126 +26,6 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#define mtsdram_as(reg, value)		\
-	addi    r4,0,reg	;	\
-	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value@h	;	\
-	ori     r4,r4,value@l	;	\
-	mtdcr   memcfgd,r4	;
-
 	.globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
-
-	/*
-	 * DDR2 setup
-	 */
-
-	/* Following the DDR Core Manual, here is the initialization */
-
-	/* Step 1 */
-
-	/* Step 2 */
-
-	/* Step 3 */
-
-	/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
-	mtsdram_as(SDRAM_MB0CF, 0x00005201);
-
-	/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
-	mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
-	mtsdram_as(SDRAM_CLKTR,0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram_as(SDRAM_RTR, 0x06180000);
-
-	/* SDRAM_SDTR1 */
-	mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram_as(SDRAM_SDTR2, 0x32204232);
-
-	/* SDRAM_SDTR3	*/
-	mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
-
-	mtsdram_as(SDRAM_MMODE, 0x00000442);
-	mtsdram_as(SDRAM_MEMODE, 0x00000404);
-
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram_as(SDRAM_MCOPT1, 0x04322000);
-
-	/* NOP */
-	mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
-	 */
-	mtsdram_as(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram_as(SDRAM_INITPLR11, 0x81000442);
-	mtsdram_as(SDRAM_INITPLR12, 0x81010780);
-	mtsdram_as(SDRAM_INITPLR13, 0x81010400);
-	mtsdram_as(SDRAM_INITPLR14, 0x00000000);
-	mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram_as(SDRAM_CODT, 0x0080f837);
-	mtsdram_as(SDRAM_MODT0, 0x01800000);
-#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
-	mtsdram_as(SDRAM_MODT1, 0x00000000);
-#endif
-
-	mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
-
-pll_wait:
-	bdnz	pll_wait
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram_as(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram_as(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram_as(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-
 	blr
diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c
deleted file mode 100644
index b03b60b..0000000
--- a/board/amcc/makalu/memory.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-void sdram_init(void)
-{
-	return;
-}
-
-long int initdram(int board_type)
-{
-	/*
-	 * Same as on Kilauea, Makalu generates exception 0x200
-	 * (machine check) after trap_init() in board_init_f,
-	 * when SDRAM is initialized here (late) and d-cache is
-	 * used earlier as INIT_RAM.
-	 * So for now, initialize DDR2 in init.S very early and
-	 * also use it for INIT_RAM. Then this exception doesn't
-	 * occur.
-	 */
-#if 0
-	u32 val;
-
-	/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
-	mtsdram(SDRAM_MB0CF, 0x00005201);
-
-	/* SET SDRAM_MB1CF - Not enabled */
-	mtsdram(SDRAM_MB1CF, 0x00000000);
-
-	/* SET SDRAM_MB2CF  - Not enabled */
-	mtsdram(SDRAM_MB2CF, 0x00000000);
-
-	/* SET SDRAM_MB3CF  - Not enabled */
-	mtsdram(SDRAM_MB3CF, 0x00000000);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
-	mtsdram(SDRAM_CLKTR, 0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram(SDRAM_RTR, 0x06180000);
-
-	/* SDRAM_SDTR1 */
-	mtsdram(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram(SDRAM_SDTR2, 0x32204232);
-
-	/* SDRAM_SDTR3	*/
-	mtsdram(SDRAM_SDTR3, 0x080b0d1a);
-
-	mtsdram(SDRAM_MMODE, 0x00000442);
-	mtsdram(SDRAM_MEMODE, 0x00000404);
-
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram(SDRAM_MCOPT1, 0x04322000);
-
-	/* NOP */
-	mtsdram(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
-	 */
-	mtsdram(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram(SDRAM_INITPLR11, 0x81000442);
-	mtsdram(SDRAM_INITPLR12, 0x81010780);
-	mtsdram(SDRAM_INITPLR13, 0x81010400);
-	mtsdram(SDRAM_INITPLR14, 0x00000000);
-	mtsdram(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram(SDRAM_CODT, 0x0080f837);
-	mtsdram(SDRAM_MODT0, 0x01800000);
-	mtsdram(SDRAM_MODT1, 0x00000000);
-
-	mtsdram(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	do {
-		mfsdram(SDRAM_MCSTAT, val);
-	} while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mfsdram(SDRAM_MCOPT2, val);
-	val |= SDRAM_MCOPT2_DCEN_ENABLE;
-	mtsdram(SDRAM_MCOPT2, val);
-#endif
-	return (CFG_MBYTES_SDRAM << 20);
-}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-    printf ("testdram\n");
-#if defined (CONFIG_NAND_U_BOOT)
-    return 0;
-#endif
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x00001000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0xaaaaaaaa;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0x55555555;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-#if !defined (CONFIG_NAND_SPL)
-	printf ("SDRAM test passed!!!\n");
-#endif
-	return 0;
-}
-#endif
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 3bd1b81..79c1a1b 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -214,36 +214,6 @@ long int initdram (int board_type)
 }
 
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 #if !defined(CONFIG_SPD_EEPROM)
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
index e62b8d3..5e04ee4 100644
--- a/board/amcc/sequoia/config.mk
+++ b/board/amcc/sequoia/config.mk
@@ -28,6 +28,10 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
 ifndef TEXT_BASE
 TEXT_BASE = 0xFFFA0000
+#
+# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000
+# TEXT_BASE = 0xFFF80000
+#
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 6bcb3ab..5ff9787 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -329,44 +329,6 @@ int checkboard(void)
 	return (0);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_MBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 /*
  * Assign interrupts to PCI devices.
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 891b4d9..e4fdf4a 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -200,45 +200,3 @@ int pci_pre_init(struct pci_controller *hose)
 	return 1;
 }
 #endif /* CONFIG_PCI */
-
-#ifdef CFG_DRAM_TEST
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-	unsigned long msr;
-	unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_EE));
-
-	for (k = 0; k < total_kbytes ;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0)
-			printf("%3d MB\r", k / 1024);
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	mtmsr(msr);
-
-	return 0;
-}
-#endif /* CFG_DRAM_TEST */
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index f00397e..b6c3065 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -196,36 +196,6 @@ int checkboard (void)
 	return (0);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x04000000;
-	uint *pend = (uint *) 0x0fc00000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index 292e026..641987e 100644
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -86,14 +86,6 @@ int checkboard(void)
 }
 
 /*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
-/*
  * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
@@ -101,11 +93,3 @@ long int initdram(int board_type)
 {
 	return spd_sdram();
 }
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("test: xxx MB - ok\n");
-
-	return (0);
-}
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 212fab8..8345537 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -200,7 +200,7 @@ int checkboard(void)
 }
 
 /*************************************************************************
- *  sdram_init -- doesn't use serial presence detect.
+ *  initdram -- doesn't use serial presence detect.
  *
  *  Assumes:    256 MB, ECC, non-registered
  *              PLB @ 133 MHz
@@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-void sdram_init(void)
+long int initdram(int board)
 {
 	register uint reg;
 	int tr1_bank1, tr1_bank2;
@@ -327,57 +327,11 @@ void sdram_init(void)
 
 	sdram_tr1_set(0x00000000, &tr1_bank1);
 	sdram_tr1_set(0x08000000, &tr1_bank2);
-	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
-}
+	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
-/*************************************************************************
- *  long int initdram
- *
- ************************************************************************/
-long int initdram(int board)
-{
-	sdram_init();
 	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 11d1743..6608893 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) {
 	return default_val;
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S
index 3aaa5c2..65f13e1 100644
--- a/board/amirix/ap1000/init.S
+++ b/board/amirix/ap1000/init.S
@@ -28,7 +28,3 @@
 	.globl	ext_bus_cntlr_init
 ext_bus_cntlr_init:
 	blr
-
-	.globl	sdram_init
-sdram_init:
-	blr
diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
index 72a10d3..4b6b3f4 100644
--- a/board/cray/L1/init.S
+++ b/board/cray/L1/init.S
@@ -134,14 +134,3 @@ ext_bus_cntlr_init:
 	mtdcr   ebccfgd,r4
 
 	blr
-
-/*----------------------------------------------------------------------------- */
-/* Function:	sdram_init */
-/* Description:	Configures SDRAM memory banks. */
-/*				NOTE: for CrayL1 we have ECC memory, so enable it. */
-/*....now done in C in L1.c:init_sdram for readability. */
-/*----------------------------------------------------------------------------- */
-	.globl  sdram_init
-
-sdram_init:
- blr
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 24c6f0d..640412d 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -27,6 +27,8 @@
 #include <miiphy.h>
 #include <ppc4xx_enet.h>
 
+void sdram_init(void);
+
 /*
  * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
  *
@@ -124,6 +126,13 @@ long initdram (int board_type)
 	ulong bank_size;
 	ulong tmp;
 
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in cpu/ppc4xx
+	 */
+	sdram_init();
+
 	tot_size = 0;
 
 	mtdcr (memcfga, mem_mb0cf);
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index 833bbce..1fbf17f 100644
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -27,6 +27,8 @@
 #include <miiphy.h>
 #include <ppc4xx_enet.h>
 
+void sdram_init(void);
+
 /*
  * board_early_init_f: do early board initialization
  *
@@ -92,6 +94,13 @@ long initdram (int board_type)
 	ulong bank_size;
 	ulong tmp;
 
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in cpu/ppc4xx
+	 */
+	sdram_init();
+
 	tot_size = 0;
 
 	mtdcr (memcfga, mem_mb0cf);
diff --git a/board/eric/eric.c b/board/eric/eric.c
index 5413ae1..14ba9b0 100644
--- a/board/eric/eric.c
+++ b/board/eric/eric.c
@@ -31,6 +31,8 @@
 #define PPC405GP_GPIO0_ODR     0xef600718	/* GPIO Open Drain */
 #define PPC405GP_GPIO0_IR      0xef60071c	/* GPIO Input */
 
+void sdram_init(void);
+
 int board_early_init_f (void)
 {
 
@@ -127,6 +129,12 @@ long int initdram (int board_type)
 	int TotalSize;
 #endif
 
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in cpu/ppc4xx
+	 */
+	sdram_init();
 
 #ifdef CONFIG_ERIC
 	/*
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
index dfead33..3abcfe6 100644
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -190,28 +190,6 @@ int checkboard (void)
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
-long int initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
 
 #if 1 /* test-only: some internal test routines... */
 /*
diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
index 055a397..30fa605 100644
--- a/board/esd/canbt/canbt.c
+++ b/board/esd/canbt/canbt.c
@@ -181,22 +181,3 @@ int checkboard (void)
 
 	return 0;
 }
-
-/* ------------------------------------------------------------------------- */
-
-long int initdram (int board_type)
-{
-	return (16 * 1024 * 1024);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
index 39a9722..49031cf 100644
--- a/board/exbitgen/exbitgen.c
+++ b/board/exbitgen/exbitgen.c
@@ -3,6 +3,8 @@
 #include <common.h>
 #include "exbitgen.h"
 
+void sdram_init(void);
+
 /* ************************************************************************ */
 int board_early_init_f (void)
 /* ------------------------------------------------------------------------ --
@@ -83,6 +85,13 @@ long int initdram (int board_type)
 	ulong bank_size;
 	ulong tmp;
 
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in cpu/ppc4xx
+	 */
+	sdram_init();
+
 	tot_size = 0;
 
 	mtdcr (memcfga, mem_mb0cf);
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index 2dfd87c..9fcab74 100644
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -149,41 +149,6 @@ long int initdram (int board_type)
 }
 
 
-#if 1 /* test-only */
-void sdram_init(void)
-{
-	init_sdram_static_settings();
-}
-#endif
-
-
-#if 0 /* test-only */
-long int initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-#endif
-
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-
 #if defined(CONFIG_CMD_NAND)
 #include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
diff --git a/board/jse/init.S b/board/jse/init.S
index 231cd1c..c564ed3 100644
--- a/board/jse/init.S
+++ b/board/jse/init.S
@@ -93,13 +93,3 @@ ext_bus_cntlr_init:
 	mtdcr   ebccfgd,r4
 
 	blr
-
-
-/*----------------------------------------------------------------------- */
-/* Function:     sdram_init                                               */
-/* Description:  This function is called by cpu/ppc4xx/start.S code       */
-/*               to get the SDRAM initialized.                            */
-/*----------------------------------------------------------------------- */
-	.globl  sdram_init
-sdram_init:
-	blr
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index b63fbdc..85795b7 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -275,44 +275,6 @@ int checkboard(void)
 	return (0);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_MBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/ml2/init.S b/board/ml2/init.S
index 80f98c5..9064d3b 100644
--- a/board/ml2/init.S
+++ b/board/ml2/init.S
@@ -28,7 +28,3 @@
 	.globl	ext_bus_cntlr_init
 ext_bus_cntlr_init:
 	blr
-
-	.globl  sdram_init
-sdram_init:
-	blr
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index 3351b5b..f00a871 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -178,19 +178,6 @@ ext_bus_cntlr_init:
   nop				/* pass2 DCR errata #8 */
   blr
 
-/*-----------------------------------------------------------------------------
- * Function:     sdram_init
- * Description:  Configures the internal SRAM memory. and setup the
- *               Stackpointer in it.
- *----------------------------------------------------------------------------- */
-	.globl  sdram_init
-
-sdram_init:
-
-
-  blr
-
-
 #if defined(CONFIG_BOOT_PCI)
     .section .bootpg,"ax"
     .globl _start_pci
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
index 39f2ea5..8384325 100644
--- a/board/mpl/pip405/init.S
+++ b/board/mpl/pip405/init.S
@@ -175,19 +175,6 @@
   nop				/* pass2 DCR errata #8 */
   blr
 
-/*-----------------------------------------------------------------------------
- * Function:     sdram_init
- * Description:  Configures the internal SRAM memory. and setup the
- *               Stackpointer in it.
- *----------------------------------------------------------------------------- */
-	.globl  sdram_init
-
-sdram_init:
-
-
-  blr
-
-
 #if defined(CONFIG_BOOT_PCI)
     .section .bootpg,"ax"
     .globl _start_pci
diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index dc526fc..42c7c16 100644
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -121,15 +121,6 @@ void hcu_led_set(u32 value)
 }
 
 /*
- * sdram_init - Dummy implementation for start.S, spd_sdram  or initdram
- *		used for HCUx
- */
-void sdram_init(void)
-{
-	return;
-}
-
-/*
  * hcu_get_slot
  */
 u32 hcu_get_slot(void)
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 6b1b53a..d8817b8 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -40,28 +40,6 @@
 void hcu_led_set(u32 value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 
-#define DDR_DCR_BASE 0x10
-#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
-#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
-
-#define DDR0_01_INT_MASK_MASK             0x000000FF
-#define DDR0_00_INT_ACK_ALL               0x7F000000
-#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
-
-#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
-#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
-
-#define DDR0_22                         0x16
-/* ECC */
-#define DDR0_22_CTRL_RAW_MASK             0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not enabled */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC no correction */
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* Not a ECC RAM*/
-#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC correcting on */
-#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
-
 #define ECC_RAM				0x03267F0B
 #define NO_ECC_RAM			0x00267F0B
 
@@ -111,11 +89,11 @@ static int wait_for_dlllock(void)
 	/* -----------------------------------------------------------+
 	 * Wait for the DCC master delay line to finish calibration
 	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_17);
+	mtdcr(memcfga, DDR0_17);
 	val = DDR0_17_DLLLOCKREG_UNLOCKED;
 
 	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
+		val = mfdcr(memcfgd);
 		if ((val & DDR0_17_DLLLOCKREG_MASK) ==
 		    DDR0_17_DLLLOCKREG_LOCKED)
 			/* dlllockreg bit on */
diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c
index 2b21444..07891f6 100644
--- a/board/netstal/mcu25/mcu25.c
+++ b/board/netstal/mcu25/mcu25.c
@@ -128,15 +128,6 @@ void hcu_led_set(u32 value)
 }
 
 /*
- * sdram_init - Dummy implementation for start.S, spd_sdram  or initdram
- *		used for HCUx
- */
-void sdram_init(void)
-{
-	return;
-}
-
-/*
  * hcu_get_slot
  */
 u32 hcu_get_slot(void)
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 620000a..2b8992e 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -553,44 +553,6 @@ long int initdram (int board_type)
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index 287f32e..8d60936 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -132,36 +132,6 @@ int checkboard (void)
 	return (0);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
index c56c269..7a3d63a 100644
--- a/board/w7o/w7o.c
+++ b/board/w7o/w7o.c
@@ -31,6 +31,7 @@
 #include <watchdog.h>
 
 unsigned long get_dram_size (void);
+void sdram_init(void);
 
 /*
  * Macros to transform values
@@ -153,6 +154,13 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
+	/*
+	 * ToDo: Move the asm init routine sdram_init() to this C file,
+	 * or even better use some common ppc4xx code available
+	 * in cpu/ppc4xx
+	 */
+	sdram_init();
+
 	return get_dram_size ();
 }
 
diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S
index f753df8..a282c9a 100644
--- a/board/xilinx/ml300/init.S
+++ b/board/xilinx/ml300/init.S
@@ -42,7 +42,3 @@
 	.globl ext_bus_cntlr_init
 ext_bus_cntlr_init:
 	blr
-
-	.globl sdram_init
-sdram_init:
-	blr
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index 4ab853f..1239ea0 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -213,51 +213,6 @@ long int initdram (int board_type)
 	return detect_sdram_size();
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-	unsigned long msr;
-	unsigned long total_kbytes;
-
-	total_kbytes = detect_sdram_size();
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_EE));
-
-	for (k = 0; k < total_kbytes ;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	mtmsr(msr);
-
-	return 0;
-}
-#endif
-
 static int default_env_var(char *buf, char *var)
 {
 	char *ptr;