Merge branch 'master' of git://www.denx.de/git/u-boot-at91

11 files changed, 631 insertions, 156 deletions

diff --git a/board/atmel/at91cap9adk/Makefile b/board/atmel/at91cap9adk/Makefile
index 359fdab..3961030 100644
--- a/board/atmel/at91cap9adk/Makefile
+++ b/board/atmel/at91cap9adk/Makefile
@@ -25,10 +25,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= at91cap9adk.o led.o nand.o
+COBJS-y	+= at91cap9adk.o
+COBJS-y	+= led.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c
index 52e62de..24861ba 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -23,7 +23,13 @@
  */
 
 #include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -40,126 +46,106 @@ DECLARE_GLOBAL_DATA_PTR;
 static void at91cap9_serial_hw_init(void)
 {
 #ifdef CONFIG_USART0
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
+	at91_set_A_periph(AT91_PIN_PA22, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PA23, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
 #endif
 
 #ifdef CONFIG_USART1
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
+	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
 #endif
 
 #ifdef CONFIG_USART2
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
+	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
 #endif
 
 #ifdef CONFIG_USART3	/* DBGU */
-	AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
 #endif
-
-
 }
 
 static void at91cap9_nor_hw_init(void)
 {
-	/* Ensure EBI supply is 3.3V */
-	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
+	unsigned long csa;
 
+	/* Ensure EBI supply is 3.3V */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 	/* Configure SMC CS0 for parallel flash */
-	AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
-				     AT91C_FLASH_NCS_WR_SETUP |
-				     AT91C_FLASH_NRD_SETUP |
-				     AT91C_FLASH_NCS_RD_SETUP;
-
-	AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
-				     AT91C_FLASH_NCS_WR_PULSE |
-				     AT91C_FLASH_NRD_PULSE |
-				     AT91C_FLASH_NCS_RD_PULSE;
-
-	AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
-				     AT91C_FLASH_NRD_CYCLE;
-
-	AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
-				     AT91C_SMC_WRITEMODE |
-				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
-				     AT91C_SMC_BAT_BYTE_WRITE |
-				     AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
-				     (AT91C_SMC_TDF & (1 << 16));
+	at91_sys_write(AT91_SMC_SETUP(0),
+		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
+		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
+	at91_sys_write(AT91_SMC_PULSE(0),
+		       AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
+		       AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
+	at91_sys_write(AT91_SMC_CYCLE(0),
+		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+	at91_sys_write(AT91_SMC_MODE(0),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
+		       AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
 }
 
 #ifdef CONFIG_CMD_NAND
 static void at91cap9_nand_hw_init(void)
 {
+	unsigned long csa;
+
 	/* Enable CS3 */
-	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
+		       AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
-				     AT91C_SM_NCS_WR_SETUP |
-				     AT91C_SM_NRD_SETUP |
-				     AT91C_SM_NCS_RD_SETUP;
-
-	AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
-				     AT91C_SM_NCS_WR_PULSE |
-				     AT91C_SM_NRD_PULSE |
-				     AT91C_SM_NCS_RD_PULSE;
-
-	AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
-				     AT91C_SM_NRD_CYCLE;
-
-	AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
-				     AT91C_SMC_WRITEMODE |
-				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
-				     AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
-				     AT91C_SM_TDF;
-
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 
 	/* RDY/BSY is not connected */
 
 	/* Enable NandFlash */
-	AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
-	AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
+	at91_set_gpio_output(AT91_PIN_PD15, 1);
 }
 #endif
 
 #ifdef CONFIG_HAS_DATAFLASH
 static void at91cap9_spi_hw_init(void)
 {
-	AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
-				   AT91C_PD1_SPI0_NPCS3D;
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
-				   AT91C_PD1_SPI0_NPCS3D;
-
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
-	AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
-				   AT91C_PA1_SPI0_MOSI |
-				   AT91C_PA0_SPI0_MISO |
-				   AT91C_PA3_SPI0_NPCS1 |
-				   AT91C_PA5_SPI0_NPCS0 |
-				   AT91C_PA2_SPI0_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
-				   AT91C_PA4_SPI0_NPCS2A |
-				   AT91C_PA1_SPI0_MOSI |
-				   AT91C_PA0_SPI0_MISO |
-				   AT91C_PA3_SPI0_NPCS1 |
-				   AT91C_PA5_SPI0_NPCS0 |
-				   AT91C_PA2_SPI0_SPCK;
-
-	/* Enable Clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+	at91_set_B_periph(AT91_PIN_PA5, 0);	/* SPI0_NPCS0 */
+
+	at91_set_B_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_B_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_B_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void at91cap9_macb_hw_init(void)
 {
-	unsigned int gpio;
-
 	/* Enable clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
 
 	/*
 	 * Disable pull-up on:
@@ -169,54 +155,59 @@ static void at91cap9_macb_hw_init(void)
 	 *
 	 * PHY has internal pull-down
 	 */
-	AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
-				     AT91C_PB25_E_RX0 |
-				     AT91C_PB26_E_RX1;
+	writel(pin_to_mask(AT91_PIN_PB22) |
+	       pin_to_mask(AT91_PIN_PB25) |
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 
 	/* Need to reset PHY -> 500ms reset */
-	AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
-				    (AT91C_RSTC_ERSTL & (0x0D << 8)) |
-				    AT91C_RSTC_URSTEN;
-	AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
-				    AT91C_RSTC_EXTRST;
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 
 	/* Wait for end hardware reset */
-	while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 
 	/* Re-enable pull-up */
-	AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
-				     AT91C_PB25_E_RX0 |
-				     AT91C_PB26_E_RX1;
-
-#ifdef CONFIG_RMII
-	gpio =	AT91C_PB30_E_MDIO |
-		AT91C_PB29_E_MDC  |
-		AT91C_PB21_E_TXCK |
-		AT91C_PB27_E_RXER |
-		AT91C_PB25_E_RX0  |
-		AT91C_PB22_E_RXDV |
-		AT91C_PB26_E_RX1  |
-		AT91C_PB28_E_TXEN |
-		AT91C_PB23_E_TX0  |
-		AT91C_PB24_E_TX1;
-	AT91C_BASE_PIOB->PIO_ASR = gpio;
-	AT91C_BASE_PIOB->PIO_BSR = 0;
-	AT91C_BASE_PIOB->PIO_PDR = gpio;
-#else
-#error AT91CAP9A-DK works only in RMII mode
+	writel(pin_to_mask(AT91_PIN_PB22) |
+	       pin_to_mask(AT91_PIN_PB25) |
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PB30, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PB29, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
 #endif
-
 	/* Unlock EMAC, 3 0 2 1 sequence */
 #define MP_MAC_KEY0	0x5969cb2a
 #define MP_MAC_KEY1	0xb4a1872e
 #define MP_MAC_KEY2	0x05683fbc
 #define MP_MAC_KEY3	0x3634fba4
 #define UNLOCK_MAC	0x00000008
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
+	writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
+	writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
+	writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
+	writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
+	writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
 }
 #endif
 
@@ -229,11 +220,11 @@ static void at91cap9_uhp_hw_init(void)
 #define MP_OHCI_KEY2	0x4823efbc
 #define MP_OHCI_KEY3	0x8651aae4
 #define UNLOCK_OHCI	0x00000010
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
+	writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
+	writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
+	writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
+	writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
+	writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
 }
 #endif
 
diff --git a/board/atmel/at91cap9adk/led.c b/board/atmel/at91cap9adk/led.c
index 8588a91..04de139 100644
--- a/board/atmel/at91cap9adk/led.c
+++ b/board/atmel/at91cap9adk/led.c
@@ -23,58 +23,55 @@
  */
 
 #include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 
-#define	RED_LED		AT91C_PIO_PC29	/* this is the power led */
-#define	GREEN_LED	AT91C_PIO_PA10	/* this is the user1 led */
-#define	YELLOW_LED	AT91C_PIO_PA11	/* this is the user1 led */
+#define	RED_LED		AT91_PIN_PC29	/* this is the power led */
+#define	GREEN_LED	AT91_PIN_PA10	/* this is the user1 led */
+#define	YELLOW_LED	AT91_PIN_PA11	/* this is the user1 led */
 
 void red_LED_on(void)
 {
-	AT91C_BASE_PIOC->PIO_SODR = RED_LED;
+	at91_set_gpio_value(RED_LED, 1);
 }
 
 void red_LED_off(void)
 {
-	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+	at91_set_gpio_value(RED_LED, 0);
 }
 
 void green_LED_on(void)
 {
-	AT91C_BASE_PIOA->PIO_CODR = GREEN_LED;
+	at91_set_gpio_value(GREEN_LED, 0);
 }
 
 void green_LED_off(void)
 {
-	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED;
+	at91_set_gpio_value(GREEN_LED, 1);
 }
 
 void yellow_LED_on(void)
 {
-	AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED;
+	at91_set_gpio_value(YELLOW_LED, 0);
 }
 
 void yellow_LED_off(void)
 {
-	AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED;
+	at91_set_gpio_value(YELLOW_LED, 1);
 }
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 
-	/* Disable peripherals on LEDs */
-	AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED;
-	/* Enable pins as outputs */
-	AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED;
-	/* Turn all LEDs OFF */
-	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED;
+	at91_set_gpio_output(RED_LED, 1);
+	at91_set_gpio_output(GREEN_LED, 1);
+	at91_set_gpio_output(YELLOW_LED, 1);
 
-	/* Disable peripherals on LEDs */
-	AT91C_BASE_PIOC->PIO_PER = RED_LED;
-	/* Enable pins as outputs */
-	AT91C_BASE_PIOC->PIO_OER = RED_LED;
-	/* Turn all LEDs OFF */
-	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+	at91_set_gpio_output(RED_LED, 0);
+	at91_set_gpio_output(GREEN_LED, 1);
+	at91_set_gpio_output(YELLOW_LED, 1);
 }
diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c
index 2f02126..c72b024 100644
--- a/board/atmel/at91cap9adk/nand.c
+++ b/board/atmel/at91cap9adk/nand.c
@@ -25,9 +25,9 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_CMD_NAND
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 
 #include <nand.h>
 
@@ -51,10 +51,10 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 		IO_ADDR_W |= MASK_ALE;
 		break;
 	case NAND_CTL_CLRNCE:
-		AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
+		at91_set_gpio_value(AT91_PIN_PD15, 1);
 		break;
 	case NAND_CTL_SETNCE:
-		AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
+		at91_set_gpio_value(AT91_PIN_PD15, 0);
 		break;
 	}
 	this->IO_ADDR_W = (void *) IO_ADDR_W;
@@ -68,4 +68,3 @@ int board_nand_init(struct nand_chip *nand)
 
 	return 0;
 }
-#endif
diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile
new file mode 100644
index 0000000..8a629b9
--- /dev/null
+++ b/board/atmel/at91sam9260ek/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= at91sam9260ek.o
+COBJS-y	+= led.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
new file mode 100644
index 0000000..a55468e
--- /dev/null
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void at91sam9260ek_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9260ek_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(AT91_PIN_PC13, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(AT91_PIN_PC14, 1);
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void at91sam9260ek_spi_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* SPI0_NPCS1 */
+
+	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9260ek_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 * 	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0 << 8) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PA23, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA24, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
+#endif
+
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91sam9260ek_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9260ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91sam9260ek_spi_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91sam9260ek_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
diff --git a/board/atmel/at91sam9260ek/config.mk b/board/atmel/at91sam9260ek/config.mk
new file mode 100644
index 0000000..ff2cfd1
--- /dev/null
+++ b/board/atmel/at91sam9260ek/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c
new file mode 100644
index 0000000..4c53742
--- /dev/null
+++ b/board/atmel/at91sam9260ek/led.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+#define	RED_LED		AT91_PIN_PA9	/* this is the power led */
+#define	GREEN_LED	AT91_PIN_PA6	/* this is the user led */
+
+void red_LED_on(void)
+{
+	at91_set_gpio_value(RED_LED, 1);
+}
+
+void red_LED_off(void)
+{
+	at91_set_gpio_value(RED_LED, 0);
+}
+
+void green_LED_on(void)
+{
+	at91_set_gpio_value(GREEN_LED, 0);
+}
+
+void green_LED_off(void)
+{
+	at91_set_gpio_value(GREEN_LED, 1);
+}
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
+
+	at91_set_gpio_output(RED_LED, 1);
+	at91_set_gpio_output(GREEN_LED, 1);
+
+	at91_set_gpio_value(RED_LED, 0);
+	at91_set_gpio_value(GREEN_LED, 1);
+}
diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c
new file mode 100644
index 0000000..abb788a
--- /dev/null
+++ b/board/atmel/at91sam9260ek/nand.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		IO_ADDR_W |= MASK_CLE;
+		break;
+	case NAND_CTL_SETALE:
+		IO_ADDR_W |= MASK_ALE;
+		break;
+	case NAND_CTL_CLRNCE:
+		at91_set_gpio_value(AT91_PIN_PC14, 1);
+		break;
+	case NAND_CTL_SETNCE:
+		at91_set_gpio_value(AT91_PIN_PC14, 0);
+		break;
+	}
+	this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+{
+	return at91_get_gpio_value(AT91_PIN_PC13);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+	nand->dev_ready = at91sam9260ek_nand_ready;
+	nand->chip_delay = 20;
+
+	return 0;
+}
diff --git a/board/atmel/at91sam9260ek/u-boot.lds b/board/atmel/at91sam9260ek/u-boot.lds
new file mode 100644
index 0000000..05a6d83
--- /dev/null
+++ b/board/atmel/at91sam9260ek/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S
index 9e174b5..6aea723 100644
--- a/board/m501sk/memsetup.S
+++ b/board/m501sk/memsetup.S
@@ -52,8 +52,8 @@
 #define MC_AASR_VAL 0x00000000
 #define EBI_CFGR 0xFFFFFF64
 #define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR 0xFFFFFF70
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0 0xFFFFFF70
+#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR 0xFFFFFC28
@@ -141,8 +141,8 @@ SMRDATA:
 	.word MC_AASR_VAL
 	.word EBI_CFGR
 	.word EBI_CFGR_VAL
-	.word SMC2_CSR
-	.word SMC2_CSR_VAL
+	.word SMC_CSR0
+	.word SMC_CSR0_VAL
 	.word PLLAR
 	.word PLLAR_VAL
 	.word PLLBR